forked from luck/tmp_suning_uos_patched
x86-32, fpu: Rewrite fpu_save_init()
Rewrite fpu_save_init() to prepare for merging with 64-bit. Signed-off-by: Brian Gerst <brgerst@gmail.com> Acked-by: Pekka Enberg <penberg@kernel.org> Cc: Suresh Siddha <suresh.b.siddha@intel.com> LKML-Reference: <1283563039-3466-12-git-send-email-brgerst@gmail.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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@ -73,6 +73,11 @@ static __always_inline __pure bool use_xsave(void)
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return static_cpu_has(X86_FEATURE_XSAVE);
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}
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static __always_inline __pure bool use_fxsr(void)
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{
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return static_cpu_has(X86_FEATURE_FXSR);
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}
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extern void __sanitize_i387_state(struct task_struct *);
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static inline void sanitize_i387_state(struct task_struct *tsk)
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@ -211,6 +216,12 @@ static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
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return 0;
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}
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static inline void fpu_fxsave(struct fpu *fpu)
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{
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asm volatile("fxsave %[fx]"
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: [fx] "=m" (fpu->state->fxsave));
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}
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/* We need a safe address that is cheap to find and that is already
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in L1 during context switch. The best choices are unfortunately
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different for UP and SMP */
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@ -226,36 +237,24 @@ static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
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static inline void fpu_save_init(struct fpu *fpu)
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{
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if (use_xsave()) {
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struct xsave_struct *xstate = &fpu->state->xsave;
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struct i387_fxsave_struct *fx = &fpu->state->fxsave;
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fpu_xsave(fpu);
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/*
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* xsave header may indicate the init state of the FP.
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*/
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if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
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goto end;
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if (unlikely(fx->swd & X87_FSW_ES))
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asm volatile("fnclex");
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/*
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* we can do a simple return here or be paranoid :)
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*/
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goto clear_state;
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if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
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return;
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} else if (use_fxsr()) {
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fpu_fxsave(fpu);
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} else {
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asm volatile("fsave %[fx]; fwait"
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: [fx] "=m" (fpu->state->fsave));
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return;
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}
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/* Use more nops than strictly needed in case the compiler
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varies code */
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alternative_input(
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"fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
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"fxsave %[fx]\n"
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"bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
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X86_FEATURE_FXSR,
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[fx] "m" (fpu->state->fxsave),
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[fsw] "m" (fpu->state->fxsave.swd) : "memory");
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clear_state:
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if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES))
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asm volatile("fnclex");
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/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
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is pending. Clear the x87 state here by setting it to fixed
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values. safe_address is a random variable that should be in L1 */
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@ -265,8 +264,6 @@ static inline void fpu_save_init(struct fpu *fpu)
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"fildl %[addr]", /* set F?P to defined value */
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X86_FEATURE_FXSAVE_LEAK,
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[addr] "m" (safe_address));
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end:
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;
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}
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#endif /* CONFIG_X86_64 */
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