forked from luck/tmp_suning_uos_patched
drm/i915/psr: Enable PSR1 on gen-9+ HW
We have new tests and fixes in place since the feature was last disabled. Try again for gen-9+ hardware and enable only PSR1 by default as a first step. v2: Remove typo fix and comment improvements (Rodrigo) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Jose Roberto de Souza <jose.souza@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> References: commit2ee7dc497e
("drm/i915: disable PSR by default on HSW/BDW") References: commitdcb2e993f3
("Revert "drm/i915: Enable PSR by default on Valleyview and Cherryview."") Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Tested-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180928061117.12394-1-dhinakaran.pandiyan@intel.com
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@ -71,6 +71,10 @@ static bool psr_global_enabled(u32 debug)
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static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
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const struct intel_crtc_state *crtc_state)
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{
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/* Disable PSR2 by default for all platforms */
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if (i915_modparams.enable_psr == -1)
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return false;
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switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
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case I915_PSR_DEBUG_FORCE_PSR1:
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return false;
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@ -1066,12 +1070,9 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
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if (!dev_priv->psr.sink_support)
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return;
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if (i915_modparams.enable_psr == -1) {
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i915_modparams.enable_psr = dev_priv->vbt.psr.enable;
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/* Per platform default: all disabled. */
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i915_modparams.enable_psr = 0;
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}
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if (i915_modparams.enable_psr == -1)
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if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
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i915_modparams.enable_psr = 0;
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/* Set link_standby x link_off defaults */
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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