forked from luck/tmp_suning_uos_patched
add arch/x86/events/zhaoxin/uncore
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594ce20501
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5a0488aef0
2244
arch/x86/events/zhaoxin/uncore.c
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2244
arch/x86/events/zhaoxin/uncore.c
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File diff suppressed because it is too large
Load Diff
359
arch/x86/events/zhaoxin/uncore.h
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359
arch/x86/events/zhaoxin/uncore.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <asm/apicdef.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/perf_event.h>
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#include "../perf_event.h"
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#define ZHAOXIN_FAM7_ZXD 0x1b
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#define ZHAOXIN_FAM7_ZXE 0x3b
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#define ZHAOXIN_FAM7_CNX 0x5b
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#define UNCORE_PMU_NAME_LEN 32
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#define UNCORE_PMU_HRTIMER_INTERVAL (60LL * NSEC_PER_SEC)
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#define UNCORE_CHX_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)
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#define UNCORE_FIXED_EVENT 0xff
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#define UNCORE_PMC_IDX_MAX_GENERIC 4
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#define UNCORE_PMC_IDX_MAX_FIXED 1
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#define UNCORE_PMC_IDX_FIXED UNCORE_PMC_IDX_MAX_GENERIC
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#define UNCORE_PMC_IDX_MAX (UNCORE_PMC_IDX_FIXED + 1)
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#define UNCORE_PCI_DEV_DATA(type, idx) ((type << 8) | idx)
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#define UNCORE_PCI_DEV_TYPE(data) ((data >> 8) & 0xff)
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#define UNCORE_PCI_DEV_IDX(data) (data & 0xff)
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struct zhaoxin_uncore_ops;
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struct zhaoxin_uncore_pmu;
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struct zhaoxin_uncore_box;
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struct uncore_event_desc;
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struct zhaoxin_uncore_type {
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const char *name;
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int num_counters;
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int num_boxes;
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int perf_ctr_bits;
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int fixed_ctr_bits;
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unsigned int perf_ctr;
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unsigned int event_ctl;
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unsigned int event_mask;
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unsigned int event_mask_ext;
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unsigned int fixed_ctr;
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unsigned int fixed_ctl;
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unsigned int box_ctl;
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unsigned int msr_offset;
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unsigned int num_shared_regs:8;
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unsigned int single_fixed:1;
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unsigned int pair_ctr_ctl:1;
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unsigned int *msr_offsets;
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struct event_constraint unconstrainted;
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struct event_constraint *constraints;
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struct zhaoxin_uncore_pmu *pmus;
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struct zhaoxin_uncore_ops *ops;
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struct uncore_event_desc *event_descs;
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const struct attribute_group *attr_groups[4];
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struct pmu *pmu; /* for custom pmu ops */
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};
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#define pmu_group attr_groups[0]
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#define format_group attr_groups[1]
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#define events_group attr_groups[2]
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struct zhaoxin_uncore_ops {
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void (*init_box)(struct zhaoxin_uncore_box *box);
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void (*exit_box)(struct zhaoxin_uncore_box *box);
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void (*disable_box)(struct zhaoxin_uncore_box *box);
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void (*enable_box)(struct zhaoxin_uncore_box *box);
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void (*disable_event)(struct zhaoxin_uncore_box *box, struct perf_event *event);
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void (*enable_event)(struct zhaoxin_uncore_box *box, struct perf_event *event);
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u64 (*read_counter)(struct zhaoxin_uncore_box *box, struct perf_event *event);
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int (*hw_config)(struct zhaoxin_uncore_box *box, struct perf_event *event);
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struct event_constraint *(*get_constraint)(struct zhaoxin_uncore_box *box,
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struct perf_event *event);
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void (*put_constraint)(struct zhaoxin_uncore_box *box, struct perf_event *event);
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};
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struct zhaoxin_uncore_pmu {
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struct pmu pmu;
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char name[UNCORE_PMU_NAME_LEN];
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int pmu_idx;
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int func_id;
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bool registered;
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atomic_t activeboxes;
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struct zhaoxin_uncore_type *type;
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struct zhaoxin_uncore_box **boxes;
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};
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struct zhaoxin_uncore_extra_reg {
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raw_spinlock_t lock;
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u64 config, config1, config2;
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atomic_t ref;
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};
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struct zhaoxin_uncore_box {
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int pci_phys_id;
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int package_id; /*Package ID */
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int cluster_id;
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int subnode_id;
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int n_active; /* number of active events */
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int n_events;
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int cpu; /* cpu to collect events */
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unsigned long flags;
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atomic_t refcnt;
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struct perf_event *events[UNCORE_PMC_IDX_MAX];
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struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
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struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX];
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unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
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u64 tags[UNCORE_PMC_IDX_MAX];
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struct pci_dev *pci_dev;
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struct zhaoxin_uncore_pmu *pmu;
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u64 hrtimer_duration; /* hrtimer timeout for this box */
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struct hrtimer hrtimer;
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struct list_head list;
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struct list_head active_list;
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void __iomem *io_addr;
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struct zhaoxin_uncore_extra_reg shared_regs[0];
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};
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#define UNCORE_BOX_FLAG_INITIATED 0
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struct uncore_event_desc {
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struct device_attribute attr;
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const char *config;
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};
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struct hw_info {
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u64 config_info;
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u64 active_state;
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};
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ssize_t zx_uncore_event_show(struct device *dev,
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struct device_attribute *attr, char *buf);
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#define ZHAOXIN_UNCORE_EVENT_DESC(_name, _config) \
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{ \
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.attr = __ATTR(_name, 0444, zx_uncore_event_show, NULL), \
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.config = _config, \
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}
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#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format) \
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static ssize_t __uncore_##_var##_show(struct device *dev, \
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struct device_attribute *attr, \
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char *page) \
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{ \
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BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
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return sprintf(page, _format "\n"); \
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} \
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static struct device_attribute format_attr_##_var = \
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__ATTR(_name, 0444, __uncore_##_var##_show, NULL)
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static inline bool uncore_pmc_fixed(int idx)
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{
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return idx == UNCORE_PMC_IDX_FIXED;
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}
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static inline unsigned int uncore_pci_box_ctl(struct zhaoxin_uncore_box *box)
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{
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return box->pmu->type->box_ctl;
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}
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static inline unsigned int uncore_pci_fixed_ctl(struct zhaoxin_uncore_box *box)
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{
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return box->pmu->type->fixed_ctl;
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}
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static inline unsigned int uncore_pci_fixed_ctr(struct zhaoxin_uncore_box *box)
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{
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return box->pmu->type->fixed_ctr;
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}
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static inline
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unsigned int uncore_pci_event_ctl(struct zhaoxin_uncore_box *box, int idx)
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{
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return idx * 4 + box->pmu->type->event_ctl;
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}
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static inline
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unsigned int uncore_pci_perf_ctr(struct zhaoxin_uncore_box *box, int idx)
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{
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return idx * 8 + box->pmu->type->perf_ctr;
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}
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static inline unsigned int uncore_msr_box_offset(struct zhaoxin_uncore_box *box)
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{
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struct zhaoxin_uncore_pmu *pmu = box->pmu;
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return pmu->type->msr_offsets ?
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pmu->type->msr_offsets[pmu->pmu_idx] :
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pmu->type->msr_offset * pmu->pmu_idx;
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}
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static inline unsigned int uncore_msr_box_ctl(struct zhaoxin_uncore_box *box)
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{
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if (!box->pmu->type->box_ctl)
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return 0;
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return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
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}
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static inline unsigned int uncore_msr_fixed_ctl(struct zhaoxin_uncore_box *box)
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{
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if (!box->pmu->type->fixed_ctl)
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return 0;
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return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
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}
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static inline unsigned int uncore_msr_fixed_ctr(struct zhaoxin_uncore_box *box)
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{
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return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
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}
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static inline
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unsigned int uncore_msr_event_ctl(struct zhaoxin_uncore_box *box, int idx)
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{
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return box->pmu->type->event_ctl +
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(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
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uncore_msr_box_offset(box);
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}
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static inline
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unsigned int uncore_msr_perf_ctr(struct zhaoxin_uncore_box *box, int idx)
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{
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return box->pmu->type->perf_ctr +
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(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
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uncore_msr_box_offset(box);
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}
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static inline
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unsigned int uncore_fixed_ctl(struct zhaoxin_uncore_box *box)
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{
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if (box->pci_dev)
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return uncore_pci_fixed_ctl(box);
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else
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return uncore_msr_fixed_ctl(box);
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}
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static inline
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unsigned int uncore_fixed_ctr(struct zhaoxin_uncore_box *box)
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{
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if (box->pci_dev)
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return uncore_pci_fixed_ctr(box);
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else
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return uncore_msr_fixed_ctr(box);
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}
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static inline
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unsigned int uncore_event_ctl(struct zhaoxin_uncore_box *box, int idx)
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{ if (box->pci_dev)
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return uncore_pci_event_ctl(box, idx);
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else
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return uncore_msr_event_ctl(box, idx);
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}
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static inline
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unsigned int uncore_perf_ctr(struct zhaoxin_uncore_box *box, int idx)
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{ if (box->pci_dev)
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return uncore_pci_perf_ctr(box, idx);
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else
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return uncore_msr_perf_ctr(box, idx);
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}
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static inline int uncore_perf_ctr_bits(struct zhaoxin_uncore_box *box)
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{
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return box->pmu->type->perf_ctr_bits;
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}
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static inline int uncore_fixed_ctr_bits(struct zhaoxin_uncore_box *box)
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{
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return box->pmu->type->fixed_ctr_bits;
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}
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static inline int uncore_num_counters(struct zhaoxin_uncore_box *box)
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{
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return box->pmu->type->num_counters;
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}
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static inline void uncore_disable_box(struct zhaoxin_uncore_box *box)
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{
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if (box->pmu->type->ops->disable_box)
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box->pmu->type->ops->disable_box(box);
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}
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static inline void uncore_enable_box(struct zhaoxin_uncore_box *box)
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{
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if (box->pmu->type->ops->enable_box)
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box->pmu->type->ops->enable_box(box);
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}
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static inline void uncore_disable_event(struct zhaoxin_uncore_box *box,
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struct perf_event *event)
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{
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box->pmu->type->ops->disable_event(box, event);
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}
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static inline void uncore_enable_event(struct zhaoxin_uncore_box *box,
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struct perf_event *event)
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{
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box->pmu->type->ops->enable_event(box, event);
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}
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static inline u64 uncore_read_counter(struct zhaoxin_uncore_box *box,
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struct perf_event *event)
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{
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return box->pmu->type->ops->read_counter(box, event);
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}
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static inline void uncore_box_init(struct zhaoxin_uncore_box *box)
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{
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if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
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if (box->pmu->type->ops->init_box)
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box->pmu->type->ops->init_box(box);
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}
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}
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static inline void uncore_box_exit(struct zhaoxin_uncore_box *box)
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{
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if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
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if (box->pmu->type->ops->exit_box)
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box->pmu->type->ops->exit_box(box);
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}
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}
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static inline bool uncore_box_is_fake(struct zhaoxin_uncore_box *box)
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{
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return (box->package_id < 0);
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}
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static inline struct zhaoxin_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
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{
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return container_of(event->pmu, struct zhaoxin_uncore_pmu, pmu);
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}
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static inline struct zhaoxin_uncore_box *uncore_event_to_box(struct perf_event *event)
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{
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return event->pmu_private;
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}
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static struct zhaoxin_uncore_box *uncore_pmu_to_box(struct zhaoxin_uncore_pmu *pmu, int cpu);
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static u64 uncore_msr_read_counter(struct zhaoxin_uncore_box *box, struct perf_event *event);
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static void uncore_pmu_start_hrtimer(struct zhaoxin_uncore_box *box);
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static void uncore_pmu_cancel_hrtimer(struct zhaoxin_uncore_box *box);
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static void uncore_pmu_event_start(struct perf_event *event, int flags);
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static void uncore_pmu_event_stop(struct perf_event *event, int flags);
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static int uncore_pmu_event_add(struct perf_event *event, int flags);
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static void uncore_pmu_event_del(struct perf_event *event, int flags);
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static void uncore_pmu_event_read(struct perf_event *event);
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static void uncore_perf_event_update(struct zhaoxin_uncore_box *box, struct perf_event *event);
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struct event_constraint *
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uncore_get_constraint(struct zhaoxin_uncore_box *box, struct perf_event *event);
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void uncore_put_constraint(struct zhaoxin_uncore_box *box, struct perf_event *event);
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u64 uncore_shared_reg_config(struct zhaoxin_uncore_box *box, int idx);
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void chx_uncore_cpu_init(void);
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void cnx_uncore_cpu_init(void);
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int cnx_uncore_pci_init(void);
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