forked from luck/tmp_suning_uos_patched
ASoC: Move register I/O code into a separate file
For clarity and to help ongoing refactoring in this area create a new file to contain the physical I/O functions, separating them out from the cache operations. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@ti.com>
This commit is contained in:
Mark Brown
parent
f0c4205b54
commit
5bef44f9b4
@ -1,4 +1,5 @@
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snd-soc-core-objs := soc-core.o soc-dapm.o soc-jack.o soc-cache.o soc-utils.o soc-pcm.o
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snd-soc-core-objs := soc-core.o soc-dapm.o soc-jack.o soc-cache.o soc-utils.o
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snd-soc-core-objs += soc-pcm.o soc-io.o
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obj-$(CONFIG_SND_SOC) += snd-soc-core.o
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obj-$(CONFIG_SND_SOC) += codecs/
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@ -20,386 +20,6 @@
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#include <trace/events/asoc.h>
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#ifdef CONFIG_SPI_MASTER
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static int do_spi_write(void *control, const char *data, int len)
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{
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struct spi_device *spi = control;
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int ret;
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ret = spi_write(spi, data, len);
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if (ret < 0)
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return ret;
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return len;
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}
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#endif
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static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value, const void *data, int len)
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{
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int ret;
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if (!snd_soc_codec_volatile_register(codec, reg) &&
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reg < codec->driver->reg_cache_size &&
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!codec->cache_bypass) {
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ret = snd_soc_cache_write(codec, reg, value);
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if (ret < 0)
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return -1;
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}
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if (codec->cache_only) {
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codec->cache_sync = 1;
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return 0;
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}
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ret = codec->hw_write(codec->control_data, data, len);
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if (ret == len)
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return 0;
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if (ret < 0)
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return ret;
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else
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return -EIO;
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}
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static unsigned int hw_read(struct snd_soc_codec *codec, unsigned int reg)
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{
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int ret;
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unsigned int val;
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if (reg >= codec->driver->reg_cache_size ||
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snd_soc_codec_volatile_register(codec, reg) ||
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codec->cache_bypass) {
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if (codec->cache_only)
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return -1;
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BUG_ON(!codec->hw_read);
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return codec->hw_read(codec, reg);
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}
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ret = snd_soc_cache_read(codec, reg, &val);
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if (ret < 0)
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return -1;
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return val;
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}
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static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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u16 data;
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data = cpu_to_be16((reg << 12) | (value & 0xffffff));
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return do_hw_write(codec, reg, value, &data, 2);
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}
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static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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u16 data;
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data = cpu_to_be16((reg << 9) | (value & 0x1ff));
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return do_hw_write(codec, reg, value, &data, 2);
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}
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static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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u8 data[2];
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reg &= 0xff;
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data[0] = reg;
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data[1] = value & 0xff;
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return do_hw_write(codec, reg, value, data, 2);
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}
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static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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u8 data[3];
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u16 val = cpu_to_be16(value);
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data[0] = reg;
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memcpy(&data[1], &val, sizeof(val));
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return do_hw_write(codec, reg, value, data, 3);
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}
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#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
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static unsigned int do_i2c_read(struct snd_soc_codec *codec,
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void *reg, int reglen,
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void *data, int datalen)
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{
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struct i2c_msg xfer[2];
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int ret;
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struct i2c_client *client = codec->control_data;
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/* Write register */
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xfer[0].addr = client->addr;
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xfer[0].flags = 0;
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xfer[0].len = reglen;
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xfer[0].buf = reg;
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/* Read data */
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xfer[1].addr = client->addr;
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xfer[1].flags = I2C_M_RD;
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xfer[1].len = datalen;
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xfer[1].buf = data;
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ret = i2c_transfer(client->adapter, xfer, 2);
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if (ret == 2)
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return 0;
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else if (ret < 0)
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return ret;
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else
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return -EIO;
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}
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#endif
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#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
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static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
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unsigned int r)
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{
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u8 reg = r;
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u8 data;
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int ret;
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ret = do_i2c_read(codec, ®, 1, &data, 1);
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if (ret < 0)
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return 0;
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return data;
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}
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#else
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#define snd_soc_8_8_read_i2c NULL
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#endif
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#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
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static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
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unsigned int r)
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{
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u8 reg = r;
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u16 data;
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int ret;
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ret = do_i2c_read(codec, ®, 1, &data, 2);
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if (ret < 0)
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return 0;
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return (data >> 8) | ((data & 0xff) << 8);
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}
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#else
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#define snd_soc_8_16_read_i2c NULL
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#endif
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#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
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static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
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unsigned int r)
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{
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u16 reg = r;
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u8 data;
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int ret;
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ret = do_i2c_read(codec, ®, 2, &data, 1);
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if (ret < 0)
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return 0;
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return data;
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}
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#else
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#define snd_soc_16_8_read_i2c NULL
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#endif
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static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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u8 data[3];
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u16 rval = cpu_to_be16(reg);
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memcpy(data, &rval, sizeof(rval));
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data[2] = value;
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return do_hw_write(codec, reg, value, data, 3);
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}
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#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
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static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
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unsigned int r)
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{
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u16 reg = cpu_to_be16(r);
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u16 data;
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int ret;
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ret = do_i2c_read(codec, ®, 2, &data, 2);
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if (ret < 0)
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return 0;
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return be16_to_cpu(data);
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}
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#else
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#define snd_soc_16_16_read_i2c NULL
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#endif
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static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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u16 data[2];
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data[0] = cpu_to_be16(reg);
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data[1] = cpu_to_be16(value);
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return do_hw_write(codec, reg, value, data, sizeof(data));
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}
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/* Primitive bulk write support for soc-cache. The data pointed to by
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* `data' needs to already be in the form the hardware expects
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* including any leading register specific data. Any data written
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* through this function will not go through the cache as it only
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* handles writing to volatile or out of bounds registers.
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*/
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static int snd_soc_hw_bulk_write_raw(struct snd_soc_codec *codec, unsigned int reg,
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const void *data, size_t len)
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{
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int ret;
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/* To ensure that we don't get out of sync with the cache, check
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* whether the base register is volatile or if we've directly asked
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* to bypass the cache. Out of bounds registers are considered
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* volatile.
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*/
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if (!codec->cache_bypass
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&& !snd_soc_codec_volatile_register(codec, reg)
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&& reg < codec->driver->reg_cache_size)
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return -EINVAL;
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switch (codec->control_type) {
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#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
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case SND_SOC_I2C:
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ret = i2c_master_send(codec->control_data, data, len);
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break;
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#endif
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#if defined(CONFIG_SPI_MASTER)
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case SND_SOC_SPI:
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ret = spi_write(codec->control_data, data, len);
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break;
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#endif
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default:
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BUG();
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}
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if (ret == len)
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return 0;
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if (ret < 0)
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return ret;
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else
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return -EIO;
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}
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static struct {
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int addr_bits;
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int data_bits;
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int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
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unsigned int (*read)(struct snd_soc_codec *, unsigned int);
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unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
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} io_types[] = {
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{
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.addr_bits = 4, .data_bits = 12,
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.write = snd_soc_4_12_write,
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},
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{
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.addr_bits = 7, .data_bits = 9,
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.write = snd_soc_7_9_write,
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},
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{
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.addr_bits = 8, .data_bits = 8,
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.write = snd_soc_8_8_write,
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.i2c_read = snd_soc_8_8_read_i2c,
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},
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{
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.addr_bits = 8, .data_bits = 16,
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.write = snd_soc_8_16_write,
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.i2c_read = snd_soc_8_16_read_i2c,
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},
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{
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.addr_bits = 16, .data_bits = 8,
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.write = snd_soc_16_8_write,
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.i2c_read = snd_soc_16_8_read_i2c,
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},
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{
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.addr_bits = 16, .data_bits = 16,
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.write = snd_soc_16_16_write,
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.i2c_read = snd_soc_16_16_read_i2c,
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},
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};
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/**
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* snd_soc_codec_set_cache_io: Set up standard I/O functions.
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*
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* @codec: CODEC to configure.
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* @addr_bits: Number of bits of register address data.
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* @data_bits: Number of bits of data per register.
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* @control: Control bus used.
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*
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* Register formats are frequently shared between many I2C and SPI
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* devices. In order to promote code reuse the ASoC core provides
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* some standard implementations of CODEC read and write operations
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* which can be set up using this function.
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*
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* The caller is responsible for allocating and initialising the
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* actual cache.
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*
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* Note that at present this code cannot be used by CODECs with
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* volatile registers.
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*/
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int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
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int addr_bits, int data_bits,
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enum snd_soc_control_type control)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(io_types); i++)
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if (io_types[i].addr_bits == addr_bits &&
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io_types[i].data_bits == data_bits)
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break;
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if (i == ARRAY_SIZE(io_types)) {
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printk(KERN_ERR
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"No I/O functions for %d bit address %d bit data\n",
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addr_bits, data_bits);
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return -EINVAL;
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}
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codec->write = io_types[i].write;
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codec->read = hw_read;
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codec->bulk_write_raw = snd_soc_hw_bulk_write_raw;
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switch (control) {
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case SND_SOC_CUSTOM:
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break;
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case SND_SOC_I2C:
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#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
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codec->hw_write = (hw_write_t)i2c_master_send;
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#endif
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if (io_types[i].i2c_read)
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codec->hw_read = io_types[i].i2c_read;
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codec->control_data = container_of(codec->dev,
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struct i2c_client,
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dev);
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break;
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case SND_SOC_SPI:
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#ifdef CONFIG_SPI_MASTER
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codec->hw_write = do_spi_write;
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#endif
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codec->control_data = container_of(codec->dev,
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struct spi_device,
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dev);
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break;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
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static bool snd_soc_set_cache_val(void *base, unsigned int idx,
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unsigned int val, unsigned int word_size)
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{
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399
sound/soc/soc-io.c
Normal file
399
sound/soc/soc-io.c
Normal file
@ -0,0 +1,399 @@
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/*
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* soc-io.c -- ASoC register I/O helpers
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*
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* Copyright 2009-2011 Wolfson Microelectronics PLC.
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*
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* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/i2c.h>
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#include <linux/spi/spi.h>
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#include <sound/soc.h>
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#include <trace/events/asoc.h>
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#ifdef CONFIG_SPI_MASTER
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static int do_spi_write(void *control, const char *data, int len)
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{
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struct spi_device *spi = control;
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int ret;
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ret = spi_write(spi, data, len);
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if (ret < 0)
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return ret;
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return len;
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}
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#endif
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static int do_hw_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value, const void *data, int len)
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{
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int ret;
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if (!snd_soc_codec_volatile_register(codec, reg) &&
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reg < codec->driver->reg_cache_size &&
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!codec->cache_bypass) {
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ret = snd_soc_cache_write(codec, reg, value);
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if (ret < 0)
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return -1;
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}
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if (codec->cache_only) {
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codec->cache_sync = 1;
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return 0;
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}
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ret = codec->hw_write(codec->control_data, data, len);
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if (ret == len)
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return 0;
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if (ret < 0)
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return ret;
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else
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return -EIO;
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}
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static unsigned int hw_read(struct snd_soc_codec *codec, unsigned int reg)
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{
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int ret;
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unsigned int val;
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if (reg >= codec->driver->reg_cache_size ||
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snd_soc_codec_volatile_register(codec, reg) ||
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codec->cache_bypass) {
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if (codec->cache_only)
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return -1;
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BUG_ON(!codec->hw_read);
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return codec->hw_read(codec, reg);
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}
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ret = snd_soc_cache_read(codec, reg, &val);
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if (ret < 0)
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return -1;
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return val;
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}
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static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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u16 data;
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data = cpu_to_be16((reg << 12) | (value & 0xffffff));
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return do_hw_write(codec, reg, value, &data, 2);
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}
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static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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u16 data;
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data = cpu_to_be16((reg << 9) | (value & 0x1ff));
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return do_hw_write(codec, reg, value, &data, 2);
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}
|
||||
|
||||
static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
|
||||
unsigned int value)
|
||||
{
|
||||
u8 data[2];
|
||||
|
||||
reg &= 0xff;
|
||||
data[0] = reg;
|
||||
data[1] = value & 0xff;
|
||||
|
||||
return do_hw_write(codec, reg, value, data, 2);
|
||||
}
|
||||
|
||||
static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
|
||||
unsigned int value)
|
||||
{
|
||||
u8 data[3];
|
||||
u16 val = cpu_to_be16(value);
|
||||
|
||||
data[0] = reg;
|
||||
memcpy(&data[1], &val, sizeof(val));
|
||||
|
||||
return do_hw_write(codec, reg, value, data, 3);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
|
||||
static unsigned int do_i2c_read(struct snd_soc_codec *codec,
|
||||
void *reg, int reglen,
|
||||
void *data, int datalen)
|
||||
{
|
||||
struct i2c_msg xfer[2];
|
||||
int ret;
|
||||
struct i2c_client *client = codec->control_data;
|
||||
|
||||
/* Write register */
|
||||
xfer[0].addr = client->addr;
|
||||
xfer[0].flags = 0;
|
||||
xfer[0].len = reglen;
|
||||
xfer[0].buf = reg;
|
||||
|
||||
/* Read data */
|
||||
xfer[1].addr = client->addr;
|
||||
xfer[1].flags = I2C_M_RD;
|
||||
xfer[1].len = datalen;
|
||||
xfer[1].buf = data;
|
||||
|
||||
ret = i2c_transfer(client->adapter, xfer, 2);
|
||||
if (ret == 2)
|
||||
return 0;
|
||||
else if (ret < 0)
|
||||
return ret;
|
||||
else
|
||||
return -EIO;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
|
||||
static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
|
||||
unsigned int r)
|
||||
{
|
||||
u8 reg = r;
|
||||
u8 data;
|
||||
int ret;
|
||||
|
||||
ret = do_i2c_read(codec, ®, 1, &data, 1);
|
||||
if (ret < 0)
|
||||
return 0;
|
||||
return data;
|
||||
}
|
||||
#else
|
||||
#define snd_soc_8_8_read_i2c NULL
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
|
||||
static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
|
||||
unsigned int r)
|
||||
{
|
||||
u8 reg = r;
|
||||
u16 data;
|
||||
int ret;
|
||||
|
||||
ret = do_i2c_read(codec, ®, 1, &data, 2);
|
||||
if (ret < 0)
|
||||
return 0;
|
||||
return (data >> 8) | ((data & 0xff) << 8);
|
||||
}
|
||||
#else
|
||||
#define snd_soc_8_16_read_i2c NULL
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
|
||||
static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
|
||||
unsigned int r)
|
||||
{
|
||||
u16 reg = r;
|
||||
u8 data;
|
||||
int ret;
|
||||
|
||||
ret = do_i2c_read(codec, ®, 2, &data, 1);
|
||||
if (ret < 0)
|
||||
return 0;
|
||||
return data;
|
||||
}
|
||||
#else
|
||||
#define snd_soc_16_8_read_i2c NULL
|
||||
#endif
|
||||
|
||||
static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
|
||||
unsigned int value)
|
||||
{
|
||||
u8 data[3];
|
||||
u16 rval = cpu_to_be16(reg);
|
||||
|
||||
memcpy(data, &rval, sizeof(rval));
|
||||
data[2] = value;
|
||||
|
||||
return do_hw_write(codec, reg, value, data, 3);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
|
||||
static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
|
||||
unsigned int r)
|
||||
{
|
||||
u16 reg = cpu_to_be16(r);
|
||||
u16 data;
|
||||
int ret;
|
||||
|
||||
ret = do_i2c_read(codec, ®, 2, &data, 2);
|
||||
if (ret < 0)
|
||||
return 0;
|
||||
return be16_to_cpu(data);
|
||||
}
|
||||
#else
|
||||
#define snd_soc_16_16_read_i2c NULL
|
||||
#endif
|
||||
|
||||
static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
|
||||
unsigned int value)
|
||||
{
|
||||
u16 data[2];
|
||||
|
||||
data[0] = cpu_to_be16(reg);
|
||||
data[1] = cpu_to_be16(value);
|
||||
|
||||
return do_hw_write(codec, reg, value, data, sizeof(data));
|
||||
}
|
||||
|
||||
/* Primitive bulk write support for soc-cache. The data pointed to by
|
||||
* `data' needs to already be in the form the hardware expects
|
||||
* including any leading register specific data. Any data written
|
||||
* through this function will not go through the cache as it only
|
||||
* handles writing to volatile or out of bounds registers.
|
||||
*/
|
||||
static int snd_soc_hw_bulk_write_raw(struct snd_soc_codec *codec, unsigned int reg,
|
||||
const void *data, size_t len)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* To ensure that we don't get out of sync with the cache, check
|
||||
* whether the base register is volatile or if we've directly asked
|
||||
* to bypass the cache. Out of bounds registers are considered
|
||||
* volatile.
|
||||
*/
|
||||
if (!codec->cache_bypass
|
||||
&& !snd_soc_codec_volatile_register(codec, reg)
|
||||
&& reg < codec->driver->reg_cache_size)
|
||||
return -EINVAL;
|
||||
|
||||
switch (codec->control_type) {
|
||||
#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
|
||||
case SND_SOC_I2C:
|
||||
ret = i2c_master_send(codec->control_data, data, len);
|
||||
break;
|
||||
#endif
|
||||
#if defined(CONFIG_SPI_MASTER)
|
||||
case SND_SOC_SPI:
|
||||
ret = spi_write(codec->control_data, data, len);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
|
||||
if (ret == len)
|
||||
return 0;
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
else
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
static struct {
|
||||
int addr_bits;
|
||||
int data_bits;
|
||||
int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
|
||||
unsigned int (*read)(struct snd_soc_codec *, unsigned int);
|
||||
unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
|
||||
} io_types[] = {
|
||||
{
|
||||
.addr_bits = 4, .data_bits = 12,
|
||||
.write = snd_soc_4_12_write,
|
||||
},
|
||||
{
|
||||
.addr_bits = 7, .data_bits = 9,
|
||||
.write = snd_soc_7_9_write,
|
||||
},
|
||||
{
|
||||
.addr_bits = 8, .data_bits = 8,
|
||||
.write = snd_soc_8_8_write,
|
||||
.i2c_read = snd_soc_8_8_read_i2c,
|
||||
},
|
||||
{
|
||||
.addr_bits = 8, .data_bits = 16,
|
||||
.write = snd_soc_8_16_write,
|
||||
.i2c_read = snd_soc_8_16_read_i2c,
|
||||
},
|
||||
{
|
||||
.addr_bits = 16, .data_bits = 8,
|
||||
.write = snd_soc_16_8_write,
|
||||
.i2c_read = snd_soc_16_8_read_i2c,
|
||||
},
|
||||
{
|
||||
.addr_bits = 16, .data_bits = 16,
|
||||
.write = snd_soc_16_16_write,
|
||||
.i2c_read = snd_soc_16_16_read_i2c,
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
* snd_soc_codec_set_cache_io: Set up standard I/O functions.
|
||||
*
|
||||
* @codec: CODEC to configure.
|
||||
* @addr_bits: Number of bits of register address data.
|
||||
* @data_bits: Number of bits of data per register.
|
||||
* @control: Control bus used.
|
||||
*
|
||||
* Register formats are frequently shared between many I2C and SPI
|
||||
* devices. In order to promote code reuse the ASoC core provides
|
||||
* some standard implementations of CODEC read and write operations
|
||||
* which can be set up using this function.
|
||||
*
|
||||
* The caller is responsible for allocating and initialising the
|
||||
* actual cache.
|
||||
*
|
||||
* Note that at present this code cannot be used by CODECs with
|
||||
* volatile registers.
|
||||
*/
|
||||
int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
|
||||
int addr_bits, int data_bits,
|
||||
enum snd_soc_control_type control)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(io_types); i++)
|
||||
if (io_types[i].addr_bits == addr_bits &&
|
||||
io_types[i].data_bits == data_bits)
|
||||
break;
|
||||
if (i == ARRAY_SIZE(io_types)) {
|
||||
printk(KERN_ERR
|
||||
"No I/O functions for %d bit address %d bit data\n",
|
||||
addr_bits, data_bits);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
codec->write = io_types[i].write;
|
||||
codec->read = hw_read;
|
||||
codec->bulk_write_raw = snd_soc_hw_bulk_write_raw;
|
||||
|
||||
switch (control) {
|
||||
case SND_SOC_CUSTOM:
|
||||
break;
|
||||
|
||||
case SND_SOC_I2C:
|
||||
#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
|
||||
codec->hw_write = (hw_write_t)i2c_master_send;
|
||||
#endif
|
||||
if (io_types[i].i2c_read)
|
||||
codec->hw_read = io_types[i].i2c_read;
|
||||
|
||||
codec->control_data = container_of(codec->dev,
|
||||
struct i2c_client,
|
||||
dev);
|
||||
break;
|
||||
|
||||
case SND_SOC_SPI:
|
||||
#ifdef CONFIG_SPI_MASTER
|
||||
codec->hw_write = do_spi_write;
|
||||
#endif
|
||||
|
||||
codec->control_data = container_of(codec->dev,
|
||||
struct spi_device,
|
||||
dev);
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user