forked from luck/tmp_suning_uos_patched
bnx2x: PBA Table Page Alignment Workaround
PBA Table Page Alignment Workaround The PBA table starts on the middle of the page and that's causing very low performance with virtualization. The solution is not to update via the BAR directly but via chip access to the same memory Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Eilon Greenstein
David S. Miller
parent
9dabc4242f
commit
5c86284817
@ -685,7 +685,8 @@ static void bnx2x_int_disable_sync(struct bnx2x *bp)
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static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
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u8 storm, u16 index, u8 op, u8 update)
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{
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u32 igu_addr = (IGU_ADDR_INT_ACK + IGU_FUNC_BASE * BP_FUNC(bp)) * 8;
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u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
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COMMAND_REG_INT_ACK);
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struct igu_ack_register igu_ack;
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igu_ack.status_block_index = index;
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@ -695,9 +696,9 @@ static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
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(update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
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(op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
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DP(BNX2X_MSG_OFF, "write 0x%08x to IGU addr 0x%x\n",
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(*(u32 *)&igu_ack), BAR_IGU_INTMEM + igu_addr);
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REG_WR(bp, BAR_IGU_INTMEM + igu_addr, (*(u32 *)&igu_ack));
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DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
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(*(u32 *)&igu_ack), hc_addr);
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REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
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}
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static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
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@ -719,19 +720,13 @@ static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
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static u16 bnx2x_ack_int(struct bnx2x *bp)
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{
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u32 igu_addr = (IGU_ADDR_SIMD_MASK + IGU_FUNC_BASE * BP_FUNC(bp)) * 8;
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u32 result = REG_RD(bp, BAR_IGU_INTMEM + igu_addr);
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u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
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COMMAND_REG_SIMD_MASK);
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u32 result = REG_RD(bp, hc_addr);
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DP(BNX2X_MSG_OFF, "read 0x%08x from IGU addr 0x%x\n",
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result, BAR_IGU_INTMEM + igu_addr);
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DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
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result, hc_addr);
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#ifdef IGU_DEBUG
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#warning IGU_DEBUG active
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if (result == 0) {
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BNX2X_ERR("read %x from IGU\n", result);
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REG_WR(bp, TM_REG_TIMER_SOFT_RST, 0);
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}
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#endif
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return result;
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}
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@ -2444,8 +2439,8 @@ static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
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static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
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{
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int port = BP_PORT(bp);
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int func = BP_FUNC(bp);
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u32 igu_addr = (IGU_ADDR_ATTN_BITS_SET + IGU_FUNC_BASE * func) * 8;
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u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
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COMMAND_REG_ATTN_BITS_SET);
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u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
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MISC_REG_AEU_MASK_ATTN_FUNC_0;
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u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
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@ -2523,9 +2518,9 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
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} /* if hardwired */
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DP(NETIF_MSG_HW, "about to mask 0x%08x at IGU addr 0x%x\n",
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asserted, BAR_IGU_INTMEM + igu_addr);
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REG_WR(bp, BAR_IGU_INTMEM + igu_addr, asserted);
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DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
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asserted, hc_addr);
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REG_WR(bp, hc_addr, asserted);
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/* now set back the mask */
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if (asserted & ATTN_NIG_FOR_FUNC)
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@ -2764,12 +2759,12 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
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bnx2x_release_alr(bp);
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reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_FUNC_BASE * BP_FUNC(bp)) * 8;
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reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR);
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val = ~deasserted;
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DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
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val, reg_addr);
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REG_WR(bp, BAR_IGU_INTMEM + reg_addr, val);
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REG_WR(bp, reg_addr, val);
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if (~bp->attn_state & deasserted)
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BNX2X_ERR("IGU ERROR\n");
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@ -3998,8 +3993,8 @@ static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
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sizeof(struct cstorm_def_status_block)/4);
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}
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static void bnx2x_init_sb(struct bnx2x *bp, int sb_id,
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struct host_status_block *sb, dma_addr_t mapping)
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static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
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dma_addr_t mapping, int sb_id)
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{
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int port = BP_PORT(bp);
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int func = BP_FUNC(bp);
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@ -4075,7 +4070,6 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
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atten_status_block);
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def_sb->atten_status_block.status_block_id = sb_id;
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bp->def_att_idx = 0;
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bp->attn_state = 0;
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reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
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@ -4109,17 +4103,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
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u_def_status_block);
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def_sb->u_def_status_block.status_block_id = sb_id;
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bp->def_u_idx = 0;
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REG_WR(bp, BAR_USTRORM_INTMEM +
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USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
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REG_WR(bp, BAR_USTRORM_INTMEM +
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((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
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U64_HI(section));
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REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF +
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REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF +
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USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
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REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(func),
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BNX2X_BTR);
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for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
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REG_WR16(bp, BAR_USTRORM_INTMEM +
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@ -4130,17 +4120,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
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c_def_status_block);
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def_sb->c_def_status_block.status_block_id = sb_id;
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bp->def_c_idx = 0;
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REG_WR(bp, BAR_CSTRORM_INTMEM +
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CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
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REG_WR(bp, BAR_CSTRORM_INTMEM +
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((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
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U64_HI(section));
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REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
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REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
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CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
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REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(func),
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BNX2X_BTR);
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for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
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REG_WR16(bp, BAR_CSTRORM_INTMEM +
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@ -4151,17 +4137,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
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t_def_status_block);
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def_sb->t_def_status_block.status_block_id = sb_id;
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bp->def_t_idx = 0;
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REG_WR(bp, BAR_TSTRORM_INTMEM +
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TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
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REG_WR(bp, BAR_TSTRORM_INTMEM +
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((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
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U64_HI(section));
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REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
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REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
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TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
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REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(func),
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BNX2X_BTR);
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for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
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REG_WR16(bp, BAR_TSTRORM_INTMEM +
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@ -4172,17 +4154,13 @@ static void bnx2x_init_def_sb(struct bnx2x *bp,
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x_def_status_block);
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def_sb->x_def_status_block.status_block_id = sb_id;
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bp->def_x_idx = 0;
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REG_WR(bp, BAR_XSTRORM_INTMEM +
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XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
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REG_WR(bp, BAR_XSTRORM_INTMEM +
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((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
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U64_HI(section));
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REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
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REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
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XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
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REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(func),
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BNX2X_BTR);
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for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
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REG_WR16(bp, BAR_XSTRORM_INTMEM +
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@ -4205,21 +4183,25 @@ static void bnx2x_update_coalesce(struct bnx2x *bp)
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/* HC_INDEX_U_ETH_RX_CQ_CONS */
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REG_WR8(bp, BAR_USTRORM_INTMEM +
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USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
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HC_INDEX_U_ETH_RX_CQ_CONS),
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U_SB_ETH_RX_CQ_INDEX),
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bp->rx_ticks/12);
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REG_WR16(bp, BAR_USTRORM_INTMEM +
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USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
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HC_INDEX_U_ETH_RX_CQ_CONS),
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U_SB_ETH_RX_CQ_INDEX),
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bp->rx_ticks ? 0 : 1);
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REG_WR16(bp, BAR_USTRORM_INTMEM +
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USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
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U_SB_ETH_RX_BD_INDEX),
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bp->rx_ticks ? 0 : 1);
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/* HC_INDEX_C_ETH_TX_CQ_CONS */
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REG_WR8(bp, BAR_CSTRORM_INTMEM +
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CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
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HC_INDEX_C_ETH_TX_CQ_CONS),
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C_SB_ETH_TX_CQ_INDEX),
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bp->tx_ticks/12);
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REG_WR16(bp, BAR_CSTRORM_INTMEM +
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CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
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HC_INDEX_C_ETH_TX_CQ_CONS),
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C_SB_ETH_TX_CQ_INDEX),
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bp->tx_ticks ? 0 : 1);
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}
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}
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@ -4494,7 +4476,7 @@ static void bnx2x_init_context(struct bnx2x *bp)
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}
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context->cstorm_st_context.sb_index_number =
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HC_INDEX_C_ETH_TX_CQ_CONS;
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C_SB_ETH_TX_CQ_INDEX;
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context->cstorm_st_context.status_block_id = sb_id;
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context->xstorm_ag_context.cdu_reserved =
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@ -4773,12 +4755,14 @@ static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
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DP(NETIF_MSG_IFUP,
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"bnx2x_init_sb(%p,%p) index %d cl_id %d sb %d\n",
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bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp));
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bnx2x_init_sb(bp, FP_SB_ID(fp), fp->status_blk,
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fp->status_blk_mapping);
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bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
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FP_SB_ID(fp));
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bnx2x_update_fpsb_idx(fp);
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}
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bnx2x_init_def_sb(bp, bp->def_status_blk,
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bp->def_status_blk_mapping, DEF_SB_ID);
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bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
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DEF_SB_ID);
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bnx2x_update_dsb_idx(bp);
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bnx2x_update_coalesce(bp);
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bnx2x_init_rx_rings(bp);
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bnx2x_init_tx_ring(bp);
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@ -740,6 +740,7 @@
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#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
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#define HC_REG_ATTN_NUM_P0 0x108038
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#define HC_REG_ATTN_NUM_P1 0x10803c
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#define HC_REG_COMMAND_REG 0x108180
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#define HC_REG_CONFIG_0 0x108000
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#define HC_REG_CONFIG_1 0x108004
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#define HC_REG_FUNC_NUM_P0 0x1080ac
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@ -5168,59 +5169,73 @@
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#define GRCBASE_MISC_AEU GRCBASE_MISC
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/*the offset of the configuration space in the pci core register*/
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/* offset of configuration space in the pci core register */
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#define PCICFG_OFFSET 0x2000
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#define PCICFG_VENDOR_ID_OFFSET 0x00
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#define PCICFG_DEVICE_ID_OFFSET 0x02
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#define PCICFG_COMMAND_OFFSET 0x04
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#define PCICFG_COMMAND_IO_SPACE (1<<0)
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#define PCICFG_COMMAND_MEM_SPACE (1<<1)
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#define PCICFG_COMMAND_BUS_MASTER (1<<2)
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#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
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#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
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#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
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#define PCICFG_COMMAND_PERR_ENA (1<<6)
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#define PCICFG_COMMAND_STEPPING (1<<7)
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#define PCICFG_COMMAND_SERR_ENA (1<<8)
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#define PCICFG_COMMAND_FAST_B2B (1<<9)
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#define PCICFG_COMMAND_INT_DISABLE (1<<10)
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#define PCICFG_COMMAND_RESERVED (0x1f<<11)
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#define PCICFG_STATUS_OFFSET 0x06
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#define PCICFG_REVESION_ID 0x08
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#define PCICFG_REVESION_ID 0x08
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#define PCICFG_CACHE_LINE_SIZE 0x0c
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#define PCICFG_LATENCY_TIMER 0x0d
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#define PCICFG_BAR_1_LOW 0x10
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#define PCICFG_BAR_1_HIGH 0x14
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#define PCICFG_BAR_2_LOW 0x18
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#define PCICFG_BAR_2_HIGH 0x1c
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#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
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#define PCICFG_BAR_1_LOW 0x10
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#define PCICFG_BAR_1_HIGH 0x14
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#define PCICFG_BAR_2_LOW 0x18
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#define PCICFG_BAR_2_HIGH 0x1c
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#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
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#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
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#define PCICFG_INT_LINE 0x3c
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#define PCICFG_INT_PIN 0x3d
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#define PCICFG_PM_CSR_OFFSET 0x4c
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#define PCICFG_GRC_ADDRESS 0x78
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#define PCICFG_GRC_DATA 0x80
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#define PCICFG_INT_LINE 0x3c
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#define PCICFG_INT_PIN 0x3d
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#define PCICFG_PM_CAPABILITY 0x48
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#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
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#define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
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#define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
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#define PCICFG_PM_CAPABILITY_DSI (1<<21)
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#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
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#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
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#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
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#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
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#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
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#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
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#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
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#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
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#define PCICFG_PM_CSR_OFFSET 0x4c
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#define PCICFG_PM_CSR_STATE (0x3<<0)
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#define PCICFG_PM_CSR_PME_ENABLE (1<<8)
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#define PCICFG_PM_CSR_PME_STATUS (1<<15)
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#define PCICFG_GRC_ADDRESS 0x78
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#define PCICFG_GRC_DATA 0x80
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#define PCICFG_DEVICE_CONTROL 0xb4
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#define PCICFG_LINK_CONTROL 0xbc
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#define PCICFG_COMMAND_IO_SPACE (1<<0)
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#define PCICFG_COMMAND_MEM_SPACE (1<<1)
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#define PCICFG_COMMAND_BUS_MASTER (1<<2)
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#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
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#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
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#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
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#define PCICFG_COMMAND_PERR_ENA (1<<6)
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#define PCICFG_COMMAND_STEPPING (1<<7)
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#define PCICFG_COMMAND_SERR_ENA (1<<8)
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#define PCICFG_COMMAND_FAST_B2B (1<<9)
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#define PCICFG_COMMAND_INT_DISABLE (1<<10)
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#define PCICFG_COMMAND_RESERVED (0x1f<<11)
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#define PCICFG_PM_CSR_STATE (0x3<<0)
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#define PCICFG_PM_CSR_PME_STATUS (1<<15)
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#define BAR_USTRORM_INTMEM 0x400000
|
||||
#define BAR_CSTRORM_INTMEM 0x410000
|
||||
#define BAR_XSTRORM_INTMEM 0x420000
|
||||
#define BAR_TSTRORM_INTMEM 0x430000
|
||||
|
||||
/* for accessing the IGU in case of status block ACK */
|
||||
#define BAR_IGU_INTMEM 0x440000
|
||||
|
||||
#define BAR_DOORBELL_OFFSET 0x800000
|
||||
|
||||
#define BAR_ME_REGISTER 0x450000
|
||||
|
||||
|
||||
#define GRC_CONFIG_2_SIZE_REG 0x408 /* config_2 offset */
|
||||
#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
|
||||
/* config_2 offset */
|
||||
#define GRC_CONFIG_2_SIZE_REG 0x408
|
||||
#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
|
||||
#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
|
||||
#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
|
||||
#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
|
||||
@ -5237,11 +5252,11 @@
|
||||
#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
|
||||
#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
|
||||
#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
|
||||
#define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
|
||||
#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
|
||||
#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
|
||||
#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
|
||||
#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
|
||||
#define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
|
||||
#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
|
||||
#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
|
||||
#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
|
||||
#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
|
||||
#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
|
||||
#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
|
||||
#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
|
||||
@ -5258,46 +5273,44 @@
|
||||
#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
|
||||
#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
|
||||
#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
|
||||
#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
|
||||
#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
|
||||
#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
|
||||
#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
|
||||
|
||||
/* config_3 offset */
|
||||
#define GRC_CONFIG_3_SIZE_REG (0x40c)
|
||||
#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
|
||||
#define PCI_CONFIG_3_FORCE_PME (1L<<24)
|
||||
#define PCI_CONFIG_3_PME_STATUS (1L<<25)
|
||||
#define PCI_CONFIG_3_PME_ENABLE (1L<<26)
|
||||
#define PCI_CONFIG_3_PM_STATE (0x3L<<27)
|
||||
#define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
|
||||
#define PCI_CONFIG_3_PCI_POWER (1L<<31)
|
||||
|
||||
/* config_2 offset */
|
||||
#define GRC_CONFIG_2_SIZE_REG 0x408
|
||||
#define GRC_CONFIG_3_SIZE_REG 0x40c
|
||||
#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
|
||||
#define PCI_CONFIG_3_FORCE_PME (1L<<24)
|
||||
#define PCI_CONFIG_3_PME_STATUS (1L<<25)
|
||||
#define PCI_CONFIG_3_PME_ENABLE (1L<<26)
|
||||
#define PCI_CONFIG_3_PM_STATE (0x3L<<27)
|
||||
#define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
|
||||
#define PCI_CONFIG_3_PCI_POWER (1L<<31)
|
||||
|
||||
#define GRC_BAR2_CONFIG 0x4e0
|
||||
#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
|
||||
#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
|
||||
|
||||
#define PCI_PM_DATA_A 0x410
|
||||
#define PCI_PM_DATA_B 0x414
|
||||
#define PCI_ID_VAL1 0x434
|
||||
#define PCI_ID_VAL2 0x438
|
||||
|
||||
#define PCI_PM_DATA_A (0x410)
|
||||
#define PCI_PM_DATA_B (0x414)
|
||||
#define PCI_ID_VAL1 (0x434)
|
||||
#define PCI_ID_VAL2 (0x438)
|
||||
|
||||
#define MDIO_REG_BANK_CL73_IEEEB0 0x0
|
||||
#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
|
||||
@ -5624,4 +5637,13 @@ Theotherbitsarereservedandshouldbezero*/
|
||||
#define IGU_INT_NOP 2
|
||||
#define IGU_INT_NOP2 3
|
||||
|
||||
#define COMMAND_REG_INT_ACK 0x0
|
||||
#define COMMAND_REG_PROD_UPD 0x4
|
||||
#define COMMAND_REG_ATTN_BITS_UPD 0x8
|
||||
#define COMMAND_REG_ATTN_BITS_SET 0xc
|
||||
#define COMMAND_REG_ATTN_BITS_CLR 0x10
|
||||
#define COMMAND_REG_COALESCE_NOW 0x14
|
||||
#define COMMAND_REG_SIMD_MASK 0x18
|
||||
#define COMMAND_REG_SIMD_NOMASK 0x1c
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user