forked from luck/tmp_suning_uos_patched
powerpc/mm: Split mmu_context handling
This splits the mmu_context handling between 32-bit hash based processors, 64-bit hash based processors and everybody else. This is preliminary work for adding SMP support for BookE processors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt
Paul Mackerras
parent
6d2170be45
commit
5e696617c4
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@ -2,240 +2,26 @@
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#define __ASM_POWERPC_MMU_CONTEXT_H
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#ifdef __KERNEL__
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <asm/mmu.h>
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#include <asm/cputable.h>
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#include <asm-generic/mm_hooks.h>
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#ifndef CONFIG_PPC64
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#include <asm/atomic.h>
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#include <linux/bitops.h>
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#include <asm/cputhreads.h>
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/*
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* On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
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* (virtual segment identifiers) for each context. Although the
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* hardware supports 24-bit VSIDs, and thus >1 million contexts,
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* we only use 32,768 of them. That is ample, since there can be
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* at most around 30,000 tasks in the system anyway, and it means
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* that we can use a bitmap to indicate which contexts are in use.
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* Using a bitmap means that we entirely avoid all of the problems
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* that we used to have when the context number overflowed,
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* particularly on SMP systems.
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* -- paulus.
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* Most if the context management is out of line
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*/
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/*
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* This function defines the mapping from contexts to VSIDs (virtual
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* segment IDs). We use a skew on both the context and the high 4 bits
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* of the 32-bit virtual address (the "effective segment ID") in order
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* to spread out the entries in the MMU hash table. Note, if this
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* function is changed then arch/ppc/mm/hashtable.S will have to be
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* changed to correspond.
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*/
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#define CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \
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& 0xffffff)
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/*
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The MPC8xx has only 16 contexts. We rotate through them on each
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task switch. A better way would be to keep track of tasks that
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own contexts, and implement an LRU usage. That way very active
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tasks don't always have to pay the TLB reload overhead. The
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kernel pages are mapped shared, so the kernel can run on behalf
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of any task that makes a kernel entry. Shared does not mean they
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are not protected, just that the ASID comparison is not performed.
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-- Dan
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The IBM4xx has 256 contexts, so we can just rotate through these
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as a way of "switching" contexts. If the TID of the TLB is zero,
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the PID/TID comparison is disabled, so we can use a TID of zero
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to represent all kernel pages as shared among all contexts.
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-- Dan
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*/
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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#ifdef CONFIG_8xx
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#define NO_CONTEXT 16
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#define LAST_CONTEXT 15
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#define FIRST_CONTEXT 0
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#elif defined(CONFIG_4xx)
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#define NO_CONTEXT 256
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#define LAST_CONTEXT 255
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#define FIRST_CONTEXT 1
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#elif defined(CONFIG_E200) || defined(CONFIG_E500)
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#define NO_CONTEXT 256
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#define LAST_CONTEXT 255
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#define FIRST_CONTEXT 1
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#else
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/* PPC 6xx, 7xx CPUs */
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#define NO_CONTEXT ((unsigned long) -1)
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#define LAST_CONTEXT 32767
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#define FIRST_CONTEXT 1
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#endif
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/*
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* Set the current MMU context.
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* On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by
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* loading up the segment registers for the user part of the address space.
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*
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* Since the PGD is immediately available, it is much faster to simply
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* pass this along as a second parameter, which is required for 8xx and
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* can be used for debugging on all processors (if you happen to have
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* an Abatron).
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*/
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extern void set_context(unsigned long contextid, pgd_t *pgd);
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/*
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* Bitmap of contexts in use.
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* The size of this bitmap is LAST_CONTEXT + 1 bits.
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*/
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extern unsigned long context_map[];
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/*
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* This caches the next context number that we expect to be free.
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* Its use is an optimization only, we can't rely on this context
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* number to be free, but it usually will be.
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*/
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extern unsigned long next_mmu_context;
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/*
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* If we don't have sufficient contexts to give one to every task
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* that could be in the system, we need to be able to steal contexts.
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* These variables support that.
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*/
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#if LAST_CONTEXT < 30000
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#define FEW_CONTEXTS 1
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extern atomic_t nr_free_contexts;
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extern struct mm_struct *context_mm[LAST_CONTEXT+1];
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extern void steal_context(void);
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#endif
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/*
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* Get a new mmu context for the address space described by `mm'.
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*/
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static inline void get_mmu_context(struct mm_struct *mm)
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{
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unsigned long ctx;
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if (mm->context.id != NO_CONTEXT)
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return;
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#ifdef FEW_CONTEXTS
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while (atomic_dec_if_positive(&nr_free_contexts) < 0)
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steal_context();
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#endif
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ctx = next_mmu_context;
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while (test_and_set_bit(ctx, context_map)) {
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ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
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if (ctx > LAST_CONTEXT)
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ctx = 0;
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}
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next_mmu_context = (ctx + 1) & LAST_CONTEXT;
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mm->context.id = ctx;
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#ifdef FEW_CONTEXTS
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context_mm[ctx] = mm;
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#endif
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}
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/*
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* Set up the context for a new address space.
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*/
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static inline int init_new_context(struct task_struct *t, struct mm_struct *mm)
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{
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mm->context.id = NO_CONTEXT;
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return 0;
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}
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/*
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* We're finished using the context for an address space.
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*/
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static inline void destroy_context(struct mm_struct *mm)
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{
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preempt_disable();
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if (mm->context.id != NO_CONTEXT) {
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clear_bit(mm->context.id, context_map);
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mm->context.id = NO_CONTEXT;
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#ifdef FEW_CONTEXTS
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atomic_inc(&nr_free_contexts);
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#endif
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}
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preempt_enable();
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}
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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#ifdef CONFIG_ALTIVEC
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if (cpu_has_feature(CPU_FTR_ALTIVEC))
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asm volatile ("dssall;\n"
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#ifndef CONFIG_POWER4
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"sync;\n" /* G4 needs a sync here, G5 apparently not */
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#endif
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: : );
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#endif /* CONFIG_ALTIVEC */
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tsk->thread.pgdir = next->pgd;
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if (!cpu_isset(smp_processor_id(), next->cpu_vm_mask))
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cpu_set(smp_processor_id(), next->cpu_vm_mask);
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/* No need to flush userspace segments if the mm doesnt change */
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if (prev == next)
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return;
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/* Setup new userspace context */
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get_mmu_context(next);
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set_context(next->context.id, next->pgd);
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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/*
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* After we have set current->mm to a new value, this activates
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* the context for the new mm so we see the new mappings.
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*/
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#define activate_mm(active_mm, mm) switch_mm(active_mm, mm, current)
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extern void mmu_context_init(void);
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#else
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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/*
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* Copyright (C) 2001 PPC 64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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static inline void enter_lazy_tlb(struct mm_struct *mm,
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struct task_struct *tsk)
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{
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}
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/*
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* The proto-VSID space has 2^35 - 1 segments available for user mappings.
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* Each segment contains 2^28 bytes. Each context maps 2^44 bytes,
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* so we can support 2^19-1 contexts (19 == 35 + 28 - 44).
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*/
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#define NO_CONTEXT 0
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#define MAX_CONTEXT ((1UL << 19) - 1)
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extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
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extern void destroy_context(struct mm_struct *mm);
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extern void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
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extern void switch_stab(struct task_struct *tsk, struct mm_struct *mm);
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extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm);
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extern void set_context(unsigned long id, pgd_t *pgd);
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/*
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* switch_mm is the entry point called from the architecture independent
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@ -244,22 +30,39 @@ extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm);
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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if (!cpu_isset(smp_processor_id(), next->cpu_vm_mask))
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cpu_set(smp_processor_id(), next->cpu_vm_mask);
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/* Mark this context has been used on the new CPU */
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cpu_set(smp_processor_id(), next->cpu_vm_mask);
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/* No need to flush userspace segments if the mm doesnt change */
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/* 32-bit keeps track of the current PGDIR in the thread struct */
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#ifdef CONFIG_PPC32
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tsk->thread.pgdir = next->pgd;
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#endif /* CONFIG_PPC32 */
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/* Nothing else to do if we aren't actually switching */
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if (prev == next)
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return;
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/* We must stop all altivec streams before changing the HW
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* context
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*/
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#ifdef CONFIG_ALTIVEC
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if (cpu_has_feature(CPU_FTR_ALTIVEC))
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asm volatile ("dssall");
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#endif /* CONFIG_ALTIVEC */
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/* The actual HW switching method differs between the various
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* sub architectures.
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*/
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#ifdef CONFIG_PPC_STD_MMU_64
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if (cpu_has_feature(CPU_FTR_SLB))
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switch_slb(tsk, next);
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else
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switch_stab(tsk, next);
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#else
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/* Out of line for now */
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switch_mmu_context(prev, next);
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#endif
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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@ -277,6 +80,11 @@ static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
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local_irq_restore(flags);
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}
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#endif /* CONFIG_PPC64 */
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/* We don't currently use enter_lazy_tlb() for anything */
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static inline void enter_lazy_tlb(struct mm_struct *mm,
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struct task_struct *tsk)
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{
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}
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#endif /* __KERNEL__ */
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#endif /* __ASM_POWERPC_MMU_CONTEXT_H */
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@ -60,6 +60,7 @@ int main(void)
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{
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DEFINE(THREAD, offsetof(struct task_struct, thread));
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DEFINE(MM, offsetof(struct task_struct, mm));
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DEFINE(MMCONTEXTID, offsetof(struct mm_struct, context.id));
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#ifdef CONFIG_PPC64
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DEFINE(AUDITCONTEXT, offsetof(struct task_struct, audit_context));
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#else
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@ -31,6 +31,7 @@
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/ptrace.h>
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#include <asm/bug.h>
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/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
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#define LOAD_BAT(n, reg, RA, RB) \
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@ -1070,9 +1071,14 @@ start_here:
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RFI
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/*
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* void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
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*
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* Set up the segment registers for a new context.
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*/
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_ENTRY(set_context)
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_ENTRY(switch_mmu_context)
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lwz r3,MMCONTEXTID(r4)
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cmpwi cr0,r3,0
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blt- 4f
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mulli r3,r3,897 /* multiply context by skew factor */
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rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
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addis r3,r3,0x6000 /* Set Ks, Ku bits */
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@ -1083,6 +1089,7 @@ _ENTRY(set_context)
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/* Context switch the PTE pointer for the Abatron BDI2000.
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* The PGDIR is passed as second argument.
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*/
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lwz r4,MM_PGD(r4)
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lis r5, KERNELBASE@h
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lwz r5, 0xf0(r5)
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stw r4, 0x4(r5)
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@ -1098,6 +1105,9 @@ _ENTRY(set_context)
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sync
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isync
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blr
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4: trap
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EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
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blr
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/*
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* An undocumented "feature" of 604e requires that the v bit
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@ -174,8 +174,7 @@ EXPORT_SYMBOL(cacheable_memcpy);
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#endif
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#ifdef CONFIG_PPC32
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EXPORT_SYMBOL(next_mmu_context);
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EXPORT_SYMBOL(set_context);
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EXPORT_SYMBOL(switch_mmu_context);
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#endif
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#ifdef CONFIG_PPC_STD_MMU_32
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@ -34,6 +34,6 @@ void save_processor_state(void)
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void restore_processor_state(void)
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{
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#ifdef CONFIG_PPC32
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set_context(current->active_mm->context.id, current->active_mm->pgd);
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switch_mmu_context(NULL, current->active_mm);
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#endif
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}
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@ -8,15 +8,16 @@ endif
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obj-y := fault.o mem.o pgtable.o \
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init_$(CONFIG_WORD_SIZE).o \
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pgtable_$(CONFIG_WORD_SIZE).o \
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mmu_context_$(CONFIG_WORD_SIZE).o
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pgtable_$(CONFIG_WORD_SIZE).o
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obj-$(CONFIG_PPC_MMU_NOHASH) += mmu_context_nohash.o
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hash-$(CONFIG_PPC_NATIVE) := hash_native_64.o
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obj-$(CONFIG_PPC64) += hash_utils_64.o \
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slb_low.o slb.o stab.o \
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gup.o mmap.o $(hash-y)
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obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o
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obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \
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tlb_hash$(CONFIG_WORD_SIZE).o
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tlb_hash$(CONFIG_WORD_SIZE).o \
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mmu_context_hash$(CONFIG_WORD_SIZE).o
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obj-$(CONFIG_40x) += 40x_mmu.o
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obj-$(CONFIG_44x) += 44x_mmu.o
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obj-$(CONFIG_FSL_BOOKE) += fsl_booke_mmu.o
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@ -1,84 +0,0 @@
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/*
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* This file contains the routines for handling the MMU on those
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* PowerPC implementations where the MMU substantially follows the
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* architecture specification. This includes the 6xx, 7xx, 7xxx,
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* 8260, and POWER3 implementations but excludes the 8xx and 4xx.
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* -- paulus
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*
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* Derived from arch/ppc/mm/init.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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unsigned long next_mmu_context;
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unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1];
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#ifdef FEW_CONTEXTS
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atomic_t nr_free_contexts;
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struct mm_struct *context_mm[LAST_CONTEXT+1];
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void steal_context(void);
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#endif /* FEW_CONTEXTS */
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/*
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* Initialize the context management stuff.
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*/
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void __init
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mmu_context_init(void)
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{
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/*
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* Some processors have too few contexts to reserve one for
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* init_mm, and require using context 0 for a normal task.
|
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* Other processors reserve the use of context zero for the kernel.
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* This code assumes FIRST_CONTEXT < 32.
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*/
|
||||
context_map[0] = (1 << FIRST_CONTEXT) - 1;
|
||||
next_mmu_context = FIRST_CONTEXT;
|
||||
#ifdef FEW_CONTEXTS
|
||||
atomic_set(&nr_free_contexts, LAST_CONTEXT - FIRST_CONTEXT + 1);
|
||||
#endif /* FEW_CONTEXTS */
|
||||
}
|
||||
|
||||
#ifdef FEW_CONTEXTS
|
||||
/*
|
||||
* Steal a context from a task that has one at the moment.
|
||||
* This is only used on 8xx and 4xx and we presently assume that
|
||||
* they don't do SMP. If they do then this will have to check
|
||||
* whether the MM we steal is in use.
|
||||
* We also assume that this is only used on systems that don't
|
||||
* use an MMU hash table - this is true for 8xx and 4xx.
|
||||
* This isn't an LRU system, it just frees up each context in
|
||||
* turn (sort-of pseudo-random replacement :). This would be the
|
||||
* place to implement an LRU scheme if anyone was motivated to do it.
|
||||
* -- paulus
|
||||
*/
|
||||
void
|
||||
steal_context(void)
|
||||
{
|
||||
struct mm_struct *mm;
|
||||
|
||||
/* free up context `next_mmu_context' */
|
||||
/* if we shouldn't free context 0, don't... */
|
||||
if (next_mmu_context < FIRST_CONTEXT)
|
||||
next_mmu_context = FIRST_CONTEXT;
|
||||
mm = context_mm[next_mmu_context];
|
||||
flush_tlb_mm(mm);
|
||||
destroy_context(mm);
|
||||
}
|
||||
#endif /* FEW_CONTEXTS */
|
||||
103
arch/powerpc/mm/mmu_context_hash32.c
Normal file
103
arch/powerpc/mm/mmu_context_hash32.c
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* This file contains the routines for handling the MMU on those
|
||||
* PowerPC implementations where the MMU substantially follows the
|
||||
* architecture specification. This includes the 6xx, 7xx, 7xxx,
|
||||
* 8260, and POWER3 implementations but excludes the 8xx and 4xx.
|
||||
* -- paulus
|
||||
*
|
||||
* Derived from arch/ppc/mm/init.c:
|
||||
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
|
||||
*
|
||||
* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
|
||||
* and Cort Dougan (PReP) (cort@cs.nmt.edu)
|
||||
* Copyright (C) 1996 Paul Mackerras
|
||||
*
|
||||
* Derived from "arch/i386/mm/init.c"
|
||||
* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
/*
|
||||
* On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
|
||||
* (virtual segment identifiers) for each context. Although the
|
||||
* hardware supports 24-bit VSIDs, and thus >1 million contexts,
|
||||
* we only use 32,768 of them. That is ample, since there can be
|
||||
* at most around 30,000 tasks in the system anyway, and it means
|
||||
* that we can use a bitmap to indicate which contexts are in use.
|
||||
* Using a bitmap means that we entirely avoid all of the problems
|
||||
* that we used to have when the context number overflowed,
|
||||
* particularly on SMP systems.
|
||||
* -- paulus.
|
||||
*/
|
||||
#define NO_CONTEXT ((unsigned long) -1)
|
||||
#define LAST_CONTEXT 32767
|
||||
#define FIRST_CONTEXT 1
|
||||
|
||||
/*
|
||||
* This function defines the mapping from contexts to VSIDs (virtual
|
||||
* segment IDs). We use a skew on both the context and the high 4 bits
|
||||
* of the 32-bit virtual address (the "effective segment ID") in order
|
||||
* to spread out the entries in the MMU hash table. Note, if this
|
||||
* function is changed then arch/ppc/mm/hashtable.S will have to be
|
||||
* changed to correspond.
|
||||
*
|
||||
*
|
||||
* CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \
|
||||
* & 0xffffff)
|
||||
*/
|
||||
|
||||
static unsigned long next_mmu_context;
|
||||
static unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1];
|
||||
|
||||
|
||||
/*
|
||||
* Set up the context for a new address space.
|
||||
*/
|
||||
int init_new_context(struct task_struct *t, struct mm_struct *mm)
|
||||
{
|
||||
unsigned long ctx = next_mmu_context;
|
||||
|
||||
while (test_and_set_bit(ctx, context_map)) {
|
||||
ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
|
||||
if (ctx > LAST_CONTEXT)
|
||||
ctx = 0;
|
||||
}
|
||||
next_mmu_context = (ctx + 1) & LAST_CONTEXT;
|
||||
mm->context.id = ctx;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* We're finished using the context for an address space.
|
||||
*/
|
||||
void destroy_context(struct mm_struct *mm)
|
||||
{
|
||||
preempt_disable();
|
||||
if (mm->context.id != NO_CONTEXT) {
|
||||
clear_bit(mm->context.id, context_map);
|
||||
mm->context.id = NO_CONTEXT;
|
||||
}
|
||||
preempt_enable();
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize the context management stuff.
|
||||
*/
|
||||
void __init mmu_context_init(void)
|
||||
{
|
||||
/* Reserve context 0 for kernel use */
|
||||
context_map[0] = (1 << FIRST_CONTEXT) - 1;
|
||||
next_mmu_context = FIRST_CONTEXT;
|
||||
}
|
||||
|
|
@ -24,6 +24,14 @@
|
|||
static DEFINE_SPINLOCK(mmu_context_lock);
|
||||
static DEFINE_IDR(mmu_context_idr);
|
||||
|
||||
/*
|
||||
* The proto-VSID space has 2^35 - 1 segments available for user mappings.
|
||||
* Each segment contains 2^28 bytes. Each context maps 2^44 bytes,
|
||||
* so we can support 2^19-1 contexts (19 == 35 + 28 - 44).
|
||||
*/
|
||||
#define NO_CONTEXT 0
|
||||
#define MAX_CONTEXT ((1UL << 19) - 1)
|
||||
|
||||
int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
|
||||
{
|
||||
int index;
|
||||
162
arch/powerpc/mm/mmu_context_nohash.c
Normal file
162
arch/powerpc/mm/mmu_context_nohash.c
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
/*
|
||||
* This file contains the routines for handling the MMU on those
|
||||
* PowerPC implementations where the MMU is not using the hash
|
||||
* table, such as 8xx, 4xx, BookE's etc...
|
||||
*
|
||||
* Copyright 2008 Ben Herrenschmidt <benh@kernel.crashing.org>
|
||||
* IBM Corp.
|
||||
*
|
||||
* Derived from previous arch/powerpc/mm/mmu_context.c
|
||||
* and arch/powerpc/include/asm/mmu_context.h
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
/*
|
||||
* The MPC8xx has only 16 contexts. We rotate through them on each
|
||||
* task switch. A better way would be to keep track of tasks that
|
||||
* own contexts, and implement an LRU usage. That way very active
|
||||
* tasks don't always have to pay the TLB reload overhead. The
|
||||
* kernel pages are mapped shared, so the kernel can run on behalf
|
||||
* of any task that makes a kernel entry. Shared does not mean they
|
||||
* are not protected, just that the ASID comparison is not performed.
|
||||
* -- Dan
|
||||
*
|
||||
* The IBM4xx has 256 contexts, so we can just rotate through these
|
||||
* as a way of "switching" contexts. If the TID of the TLB is zero,
|
||||
* the PID/TID comparison is disabled, so we can use a TID of zero
|
||||
* to represent all kernel pages as shared among all contexts.
|
||||
* -- Dan
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_8xx
|
||||
#define NO_CONTEXT 16
|
||||
#define LAST_CONTEXT 15
|
||||
#define FIRST_CONTEXT 0
|
||||
|
||||
#elif defined(CONFIG_4xx)
|
||||
#define NO_CONTEXT 256
|
||||
#define LAST_CONTEXT 255
|
||||
#define FIRST_CONTEXT 1
|
||||
|
||||
#elif defined(CONFIG_E200) || defined(CONFIG_E500)
|
||||
#define NO_CONTEXT 256
|
||||
#define LAST_CONTEXT 255
|
||||
#define FIRST_CONTEXT 1
|
||||
|
||||
#else
|
||||
#error Unsupported processor type
|
||||
#endif
|
||||
|
||||
static unsigned long next_mmu_context;
|
||||
static unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1];
|
||||
static atomic_t nr_free_contexts;
|
||||
static struct mm_struct *context_mm[LAST_CONTEXT+1];
|
||||
static void steal_context(void);
|
||||
|
||||
/* Steal a context from a task that has one at the moment.
|
||||
* This is only used on 8xx and 4xx and we presently assume that
|
||||
* they don't do SMP. If they do then this will have to check
|
||||
* whether the MM we steal is in use.
|
||||
* We also assume that this is only used on systems that don't
|
||||
* use an MMU hash table - this is true for 8xx and 4xx.
|
||||
* This isn't an LRU system, it just frees up each context in
|
||||
* turn (sort-of pseudo-random replacement :). This would be the
|
||||
* place to implement an LRU scheme if anyone was motivated to do it.
|
||||
* -- paulus
|
||||
*/
|
||||
static void steal_context(void)
|
||||
{
|
||||
struct mm_struct *mm;
|
||||
|
||||
/* free up context `next_mmu_context' */
|
||||
/* if we shouldn't free context 0, don't... */
|
||||
if (next_mmu_context < FIRST_CONTEXT)
|
||||
next_mmu_context = FIRST_CONTEXT;
|
||||
mm = context_mm[next_mmu_context];
|
||||
flush_tlb_mm(mm);
|
||||
destroy_context(mm);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Get a new mmu context for the address space described by `mm'.
|
||||
*/
|
||||
static inline void get_mmu_context(struct mm_struct *mm)
|
||||
{
|
||||
unsigned long ctx;
|
||||
|
||||
if (mm->context.id != NO_CONTEXT)
|
||||
return;
|
||||
|
||||
while (atomic_dec_if_positive(&nr_free_contexts) < 0)
|
||||
steal_context();
|
||||
|
||||
ctx = next_mmu_context;
|
||||
while (test_and_set_bit(ctx, context_map)) {
|
||||
ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
|
||||
if (ctx > LAST_CONTEXT)
|
||||
ctx = 0;
|
||||
}
|
||||
next_mmu_context = (ctx + 1) & LAST_CONTEXT;
|
||||
mm->context.id = ctx;
|
||||
context_mm[ctx] = mm;
|
||||
}
|
||||
|
||||
void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
|
||||
{
|
||||
get_mmu_context(next);
|
||||
|
||||
set_context(next->context.id, next->pgd);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set up the context for a new address space.
|
||||
*/
|
||||
int init_new_context(struct task_struct *t, struct mm_struct *mm)
|
||||
{
|
||||
mm->context.id = NO_CONTEXT;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* We're finished using the context for an address space.
|
||||
*/
|
||||
void destroy_context(struct mm_struct *mm)
|
||||
{
|
||||
preempt_disable();
|
||||
if (mm->context.id != NO_CONTEXT) {
|
||||
clear_bit(mm->context.id, context_map);
|
||||
mm->context.id = NO_CONTEXT;
|
||||
atomic_inc(&nr_free_contexts);
|
||||
}
|
||||
preempt_enable();
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Initialize the context management stuff.
|
||||
*/
|
||||
void __init mmu_context_init(void)
|
||||
{
|
||||
/*
|
||||
* Some processors have too few contexts to reserve one for
|
||||
* init_mm, and require using context 0 for a normal task.
|
||||
* Other processors reserve the use of context zero for the kernel.
|
||||
* This code assumes FIRST_CONTEXT < 32.
|
||||
*/
|
||||
context_map[0] = (1 << FIRST_CONTEXT) - 1;
|
||||
next_mmu_context = FIRST_CONTEXT;
|
||||
atomic_set(&nr_free_contexts, LAST_CONTEXT - FIRST_CONTEXT + 1);
|
||||
}
|
||||
|
||||
|
|
@ -195,13 +195,21 @@ config SPE
|
|||
|
||||
config PPC_STD_MMU
|
||||
bool
|
||||
depends on 6xx || POWER3 || POWER4 || PPC64
|
||||
depends on 6xx || PPC64
|
||||
default y
|
||||
|
||||
config PPC_STD_MMU_32
|
||||
def_bool y
|
||||
depends on PPC_STD_MMU && PPC32
|
||||
|
||||
config PPC_STD_MMU_64
|
||||
def_bool y
|
||||
depends on PPC_STD_MMU && PPC64
|
||||
|
||||
config PPC_MMU_NOHASH
|
||||
def_bool y
|
||||
depends on !PPC_STD_MMU
|
||||
|
||||
config PPC_MM_SLICES
|
||||
bool
|
||||
default y if HUGETLB_PAGE || PPC_64K_PAGES
|
||||
|
|
|
|||
|
|
@ -310,7 +310,7 @@ static int pmu_set_cpu_speed(int low_speed)
|
|||
_set_L3CR(save_l3cr);
|
||||
|
||||
/* Restore userland MMU context */
|
||||
set_context(current->active_mm->context.id, current->active_mm->pgd);
|
||||
switch_mmu_context(NULL, current->active_mm);
|
||||
|
||||
#ifdef DEBUG_FREQ
|
||||
printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
|
||||
|
|
|
|||
|
|
@ -1814,7 +1814,7 @@ static int powerbook_sleep_grackle(void)
|
|||
_set_L2CR(save_l2cr);
|
||||
|
||||
/* Restore userland MMU context */
|
||||
set_context(current->active_mm->context.id, current->active_mm->pgd);
|
||||
switch_mmu_context(NULL, current->active_mm);
|
||||
|
||||
/* Power things up */
|
||||
pmu_unlock();
|
||||
|
|
@ -1903,7 +1903,7 @@ powerbook_sleep_Core99(void)
|
|||
_set_L3CR(save_l3cr);
|
||||
|
||||
/* Restore userland MMU context */
|
||||
set_context(current->active_mm->context.id, current->active_mm->pgd);
|
||||
switch_mmu_context(NULL, current->active_mm);
|
||||
|
||||
/* Tell PMU we are ready */
|
||||
pmu_unlock();
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user