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MIPS: Avoid pipeline stalls on some MIPS32R2 cores.

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The architecture specification says that an EHB instruction is
needed to avoid a hazard when writing TLB entries. However, some
cores do not have this hazard, and thus the EHB instruction causes
a costly pipeline stall. Detect these cores and do not use the EHB
instruction.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
This commit is contained in:
Steven J. Hill 2012-08-28 23:20:08 -05:00
parent 3234f44669
commit 625c0a2170
1 changed files with 13 additions and 1 deletions
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14
arch/mips/mm/tlbex.c
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@ -449,8 +449,20 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
}
if (cpu_has_mips_r2) {
if (cpu_has_mips_r2_exec_hazard)
/*
* The architecture spec says an ehb is required here,
* but a number of cores do not have the hazard and
* using an ehb causes an expensive pipeline stall.
*/
switch (current_cpu_type()) {
case CPU_M14KC:
case CPU_74K:
break;
default:
uasm_i_ehb(p);
break;
}
tlbw(p);
return;
}