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ARM: SoC fixes

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A slightly larger set of fixes have accrued in the last two weeks.
 Mostly a collection of the usual smaller fixes:
 
  - Marvell Armada: USB phy setup issues on Turris Mox
 
  - Broadcom: GPIO/pinmux DT mapping corrections for Stingray, MMC bus
  width fix for RPi Zero W, GPIO LED removal for RPI CM3. Also some
  maintainer updates.
 
  - OMAP: Fixlets for display config, interrupt settings for wifi, some
    clock/PM pieces. Also IOMMU regression fix and a ti-sysc no-watchdog
    regression fix.
 
  - i.MX: A few fixes around PM/settings, some devicetree fixlets and
  catching up with config option changes in DRM
 
  - Rockchip: RockRro64 misc DT fixups, Hugsun X99 USB-C, Kevin display
  panel settings
 
 ... and some smaller fixes for Davinci (backlight, McBSP DMA), Allwinner
 (phy regulators, PMU removal on A64, etc).
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Olof Johansson:
 "A slightly larger set of fixes have accrued in the last two weeks.
  Mostly a collection of the usual smaller fixes:

   - Marvell Armada: USB phy setup issues on Turris Mox

   - Broadcom: GPIO/pinmux DT mapping corrections for Stingray, MMC bus
     width fix for RPi Zero W, GPIO LED removal for RPI CM3. Also some
     maintainer updates.

   - OMAP: Fixlets for display config, interrupt settings for wifi, some
     clock/PM pieces. Also IOMMU regression fix and a ti-sysc
     no-watchdog regression fix.

   - i.MX: A few fixes around PM/settings, some devicetree fixlets and
     catching up with config option changes in DRM

   - Rockchip: RockRro64 misc DT fixups, Hugsun X99 USB-C, Kevin display
     panel settings

  ... and some smaller fixes for Davinci (backlight, McBSP DMA),
  Allwinner (phy regulators, PMU removal on A64, etc)"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (42 commits)
  ARM: dts: stm32: relax qspi pins slew-rate for stm32mp157
  MAINTAINERS: Update the Spreadtrum SoC maintainer
  MAINTAINERS: Remove Gregory and Brian for ARCH_BRCMSTB
  ARM: dts: bcm2837-rpi-cm3: Avoid leds-gpio probing issue
  bus: ti-sysc: Fix watchdog quirk handling
  ARM: OMAP2+: Add pdata for OMAP3 ISP IOMMU
  ARM: OMAP2+: Plug in device_enable/idle ops for IOMMUs
  ARM: davinci_all_defconfig: enable GPIO backlight
  ARM: davinci: dm365: Fix McBSP dma_slave_map entry
  ARM: dts: bcm2835-rpi-zero-w: Fix bus-width of sdhci
  ARM: imx_v6_v7_defconfig: Enable CONFIG_DRM_MSM
  arm64: dts: imx8mn: Use correct clock for usdhc's ipg clk
  arm64: dts: imx8mm: Use correct clock for usdhc's ipg clk
  arm64: dts: imx8mq: Use correct clock for usdhc's ipg clk
  ARM: dts: imx7s: Correct GPT's ipg clock source
  ARM: dts: vf610-zii-scu4-aib: Specify 'i2c-mux-idle-disconnect'
  ARM: dts: imx6q-logicpd: Re-Enable SNVS power key
  arm64: dts: lx2160a: Correct CPU core idle state name
  mailmap: Add Simon Arlott (replacement for expired email address)
  arm64: dts: rockchip: Fix override mode for rk3399-kevin panel
  ...
This commit is contained in:
Linus Torvalds 2019-10-25 16:00:47 -04:00
commit 63cbb3b364
40 changed files with 145 additions and 107 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.mailmap
View File

@ -229,6 +229,7 @@ Shuah Khan <shuah@kernel.org> <shuahkhan@gmail.com>
Shuah Khan <shuah@kernel.org> <shuah.khan@hp.com> Shuah Khan <shuah@kernel.org> <shuah.khan@hp.com>
Shuah Khan <shuah@kernel.org> <shuahkh@osg.samsung.com> Shuah Khan <shuah@kernel.org> <shuahkh@osg.samsung.com>
Shuah Khan <shuah@kernel.org> <shuah.kh@samsung.com> Shuah Khan <shuah@kernel.org> <shuah.kh@samsung.com>
Simon Arlott <simon@octiron.net> <simon@fire.lp0.eu>
Simon Kelley <simon@thekelleys.org.uk> Simon Kelley <simon@thekelleys.org.uk>
Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr> Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
Stephen Hemminger <shemminger@osdl.org> Stephen Hemminger <shemminger@osdl.org>

4
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@ -496,12 +496,12 @@ properties:
- description: Theobroma Systems RK3368-uQ7 with Haikou baseboard - description: Theobroma Systems RK3368-uQ7 with Haikou baseboard
items: items:
- const: tsd,rk3368-uq7-haikou - const: tsd,rk3368-lion-haikou
- const: rockchip,rk3368 - const: rockchip,rk3368
- description: Theobroma Systems RK3399-Q7 with Haikou baseboard - description: Theobroma Systems RK3399-Q7 with Haikou baseboard
items: items:
- const: tsd,rk3399-q7-haikou - const: tsd,rk3399-puma-haikou
- const: rockchip,rk3399 - const: rockchip,rk3399
- description: Tronsmart Orion R68 Meta - description: Tronsmart Orion R68 Meta

9
Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2 %YAML 1.2
--- ---
$id: http://devicetree.org/schemas/arm/allwinner,sun4i-a10-csi.yaml# $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 CMOS Sensor Interface (CSI) Device Tree Bindings title: Allwinner A10 CMOS Sensor Interface (CSI) Device Tree Bindings
@ -27,14 +27,12 @@ properties:
clocks: clocks:
items: items:
- description: The CSI interface clock - description: The CSI interface clock
- description: The CSI module clock
- description: The CSI ISP clock - description: The CSI ISP clock
- description: The CSI DRAM clock - description: The CSI DRAM clock
clock-names: clock-names:
items: items:
- const: bus - const: bus
- const: mod
- const: isp - const: isp
- const: ram - const: ram
@ -89,9 +87,8 @@ examples:
compatible = "allwinner,sun7i-a20-csi0"; compatible = "allwinner,sun7i-a20-csi0";
reg = <0x01c09000 0x1000>; reg = <0x01c09000 0x1000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>, clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
<&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; clock-names = "bus", "isp", "ram";
clock-names = "bus", "mod", "isp", "ram";
resets = <&ccu RST_CSI0>; resets = <&ccu RST_CSI0>;
port { port {

9
MAINTAINERS
View File

@ -2323,11 +2323,13 @@ F: drivers/edac/altera_edac.
ARM/SPREADTRUM SoC SUPPORT ARM/SPREADTRUM SoC SUPPORT
M: Orson Zhai <orsonzhai@gmail.com> M: Orson Zhai <orsonzhai@gmail.com>
M: Baolin Wang <baolin.wang@linaro.org> M: Baolin Wang <baolin.wang7@gmail.com>
M: Chunyan Zhang <zhang.lyra@gmail.com> M: Chunyan Zhang <zhang.lyra@gmail.com>
S: Maintained S: Maintained
F: arch/arm64/boot/dts/sprd F: arch/arm64/boot/dts/sprd
N: sprd N: sprd
N: sc27xx
N: sc2731
ARM/STI ARCHITECTURE ARM/STI ARCHITECTURE
M: Patrice Chotard <patrice.chotard@st.com> M: Patrice Chotard <patrice.chotard@st.com>
@ -3183,7 +3185,7 @@ N: bcm216*
N: kona N: kona
F: arch/arm/mach-bcm/ F: arch/arm/mach-bcm/
BROADCOM BCM2835 ARM ARCHITECTURE BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE
M: Eric Anholt <eric@anholt.net> M: Eric Anholt <eric@anholt.net>
M: Stefan Wahren <wahrenst@gmx.net> M: Stefan Wahren <wahrenst@gmx.net>
L: bcm-kernel-feedback-list@broadcom.com L: bcm-kernel-feedback-list@broadcom.com
@ -3191,6 +3193,7 @@ L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
T: git git://github.com/anholt/linux T: git git://github.com/anholt/linux
S: Maintained S: Maintained
N: bcm2711
N: bcm2835 N: bcm2835
F: drivers/staging/vc04_services F: drivers/staging/vc04_services
@ -3237,8 +3240,6 @@ S: Maintained
F: drivers/usb/gadget/udc/bcm63xx_udc.* F: drivers/usb/gadget/udc/bcm63xx_udc.*
BROADCOM BCM7XXX ARM ARCHITECTURE BROADCOM BCM7XXX ARM ARCHITECTURE
M: Brian Norris <computersforpeace@gmail.com>
M: Gregory Fong <gregory.0xf0@gmail.com>
M: Florian Fainelli <f.fainelli@gmail.com> M: Florian Fainelli <f.fainelli@gmail.com>
M: bcm-kernel-feedback-list@broadcom.com M: bcm-kernel-feedback-list@broadcom.com
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

9
arch/arm/boot/dts/am3874-iceboard.dts
View File

@ -111,13 +111,13 @@ pca9548@70 {
reg = <0x70>; reg = <0x70>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
i2c-mux-idle-disconnect;
i2c@0 { i2c@0 {
/* FMC A */ /* FMC A */
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0>; reg = <0>;
i2c-mux-idle-disconnect;
}; };
i2c@1 { i2c@1 {
@ -125,7 +125,6 @@ i2c@1 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <1>; reg = <1>;
i2c-mux-idle-disconnect;
}; };
i2c@2 { i2c@2 {
@ -133,7 +132,6 @@ i2c@2 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <2>; reg = <2>;
i2c-mux-idle-disconnect;
}; };
i2c@3 { i2c@3 {
@ -141,7 +139,6 @@ i2c@3 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <3>; reg = <3>;
i2c-mux-idle-disconnect;
}; };
i2c@4 { i2c@4 {
@ -149,14 +146,12 @@ i2c@4 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <4>; reg = <4>;
i2c-mux-idle-disconnect;
}; };
i2c@5 { i2c@5 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <5>; reg = <5>;
i2c-mux-idle-disconnect;
ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; }; ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; };
ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; }; ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; };
@ -182,14 +177,12 @@ i2c@6 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <6>; reg = <6>;
i2c-mux-idle-disconnect;
}; };
i2c@7 { i2c@7 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <7>; reg = <7>;
i2c-mux-idle-disconnect;
u41: pca9575@20 { u41: pca9575@20 {
compatible = "nxp,pca9575"; compatible = "nxp,pca9575";

1
arch/arm/boot/dts/bcm2835-rpi-zero-w.dts
View File

@ -113,6 +113,7 @@ &sdhci {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
bus-width = <4>;
mmc-pwrseq = <&wifi_pwrseq>; mmc-pwrseq = <&wifi_pwrseq>;
non-removable; non-removable;
status = "okay"; status = "okay";

8
arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi
View File

@ -9,6 +9,14 @@ memory@0 {
reg = <0 0x40000000>; reg = <0 0x40000000>;
}; };
leds {
/*
* Since there is no upstream GPIO driver yet,
* remove the incomplete node.
*/
/delete-node/ act;
};
reg_3v3: fixed-regulator { reg_3v3: fixed-regulator {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "3V3"; regulator-name = "3V3";

4
arch/arm/boot/dts/imx6-logicpd-som.dtsi
View File

@ -207,6 +207,10 @@ &reg_soc
vin-supply = <&sw1c_reg>; vin-supply = <&sw1c_reg>;
}; };
&snvs_poweroff {
status = "okay";
};
&iomuxc { &iomuxc {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>; pinctrl-0 = <&pinctrl_hog>;

8
arch/arm/boot/dts/imx7s.dtsi
View File

@ -448,7 +448,7 @@ gpt1: gpt@302d0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302d0000 0x10000>; reg = <0x302d0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>, clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
<&clks IMX7D_GPT1_ROOT_CLK>; <&clks IMX7D_GPT1_ROOT_CLK>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
}; };
@ -457,7 +457,7 @@ gpt2: gpt@302e0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302e0000 0x10000>; reg = <0x302e0000 0x10000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>, clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
<&clks IMX7D_GPT2_ROOT_CLK>; <&clks IMX7D_GPT2_ROOT_CLK>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
status = "disabled"; status = "disabled";
@ -467,7 +467,7 @@ gpt3: gpt@302f0000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x302f0000 0x10000>; reg = <0x302f0000 0x10000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>, clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
<&clks IMX7D_GPT3_ROOT_CLK>; <&clks IMX7D_GPT3_ROOT_CLK>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
status = "disabled"; status = "disabled";
@ -477,7 +477,7 @@ gpt4: gpt@30300000 {
compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
reg = <0x30300000 0x10000>; reg = <0x30300000 0x10000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>, clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
<&clks IMX7D_GPT4_ROOT_CLK>; <&clks IMX7D_GPT4_ROOT_CLK>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
status = "disabled"; status = "disabled";

4
arch/arm/boot/dts/logicpd-torpedo-som.dtsi
View File

@ -192,3 +192,7 @@ twl_power: power {
&twl_gpio { &twl_gpio {
ti,use-leds; ti,use-leds;
}; };
&twl_keypad {
status = "disabled";
};

2
arch/arm/boot/dts/omap4-droid4-xt894.dts
View File

@ -369,7 +369,7 @@ wlcore: wlcore@2 {
compatible = "ti,wl1285", "ti,wl1283"; compatible = "ti,wl1285", "ti,wl1283";
reg = <2>; reg = <2>;
/* gpio_100 with gpmc_wait2 pad as wakeirq */ /* gpio_100 with gpmc_wait2 pad as wakeirq */
interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>, interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>,
<&omap4_pmx_core 0x4e>; <&omap4_pmx_core 0x4e>;
interrupt-names = "irq", "wakeup"; interrupt-names = "irq", "wakeup";
ref-clock-frequency = <26000000>; ref-clock-frequency = <26000000>;

2
arch/arm/boot/dts/omap4-panda-common.dtsi
View File

@ -474,7 +474,7 @@ wlcore: wlcore@2 {
compatible = "ti,wl1271"; compatible = "ti,wl1271";
reg = <2>; reg = <2>;
/* gpio_53 with gpmc_ncs3 pad as wakeup */ /* gpio_53 with gpmc_ncs3 pad as wakeup */
interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_RISING>, interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_HIGH>,
<&omap4_pmx_core 0x3a>; <&omap4_pmx_core 0x3a>;
interrupt-names = "irq", "wakeup"; interrupt-names = "irq", "wakeup";
ref-clock-frequency = <38400000>; ref-clock-frequency = <38400000>;

2
arch/arm/boot/dts/omap4-sdp.dts
View File

@ -512,7 +512,7 @@ wlcore: wlcore@2 {
compatible = "ti,wl1281"; compatible = "ti,wl1281";
reg = <2>; reg = <2>;
interrupt-parent = <&gpio1>; interrupt-parent = <&gpio1>;
interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 53 */ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
ref-clock-frequency = <26000000>; ref-clock-frequency = <26000000>;
tcxo-clock-frequency = <26000000>; tcxo-clock-frequency = <26000000>;
}; };

2
arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi
View File

@ -69,7 +69,7 @@ wlcore: wlcore@2 {
compatible = "ti,wl1271"; compatible = "ti,wl1271";
reg = <2>; reg = <2>;
interrupt-parent = <&gpio2>; interrupt-parent = <&gpio2>;
interrupts = <9 IRQ_TYPE_EDGE_RISING>; /* gpio 41 */ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */
ref-clock-frequency = <38400000>; ref-clock-frequency = <38400000>;
}; };
}; };

2
arch/arm/boot/dts/omap5-board-common.dtsi
View File

@ -362,7 +362,7 @@ wlcore: wlcore@2 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&wlcore_irq_pin>; pinctrl-0 = <&wlcore_irq_pin>;
interrupt-parent = <&gpio1>; interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_EDGE_RISING>; /* gpio 14 */ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */
ref-clock-frequency = <26000000>; ref-clock-frequency = <26000000>;
}; };
}; };

2
arch/arm/boot/dts/omap54xx-clocks.dtsi
View File

@ -1146,7 +1146,7 @@ dss_clkctrl: clk@20 {
}; };
}; };
gpu_cm: clock-controller@1500 { gpu_cm: gpu_cm@1500 {
compatible = "ti,omap4-cm"; compatible = "ti,omap4-cm";
reg = <0x1500 0x100>; reg = <0x1500 0x100>;
#address-cells = <1>; #address-cells = <1>;

8
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
View File

@ -609,13 +609,13 @@ pins1 {
<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
bias-disable; bias-disable;
drive-push-pull; drive-push-pull;
slew-rate = <3>; slew-rate = <1>;
}; };
pins2 { pins2 {
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
bias-pull-up; bias-pull-up;
drive-push-pull; drive-push-pull;
slew-rate = <3>; slew-rate = <1>;
}; };
}; };
@ -637,13 +637,13 @@ pins1 {
<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */ <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
bias-disable; bias-disable;
drive-push-pull; drive-push-pull;
slew-rate = <3>; slew-rate = <1>;
}; };
pins2 { pins2 {
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
bias-pull-up; bias-pull-up;
drive-push-pull; drive-push-pull;
slew-rate = <3>; slew-rate = <1>;
}; };
}; };

5
arch/arm/boot/dts/sun7i-a20.dtsi
View File

@ -380,9 +380,8 @@ csi0: csi@1c09000 {
compatible = "allwinner,sun7i-a20-csi0"; compatible = "allwinner,sun7i-a20-csi0";
reg = <0x01c09000 0x1000>; reg = <0x01c09000 0x1000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>, clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
<&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; clock-names = "bus", "isp", "ram";
clock-names = "bus", "mod", "isp", "ram";
resets = <&ccu RST_CSI0>; resets = <&ccu RST_CSI0>;
status = "disabled"; status = "disabled";
}; };

2
arch/arm/boot/dts/vf610-zii-scu4-aib.dts
View File

@ -602,6 +602,7 @@ tca9548@70 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0x70>; reg = <0x70>;
i2c-mux-idle-disconnect;
sff0_i2c: i2c@1 { sff0_i2c: i2c@1 {
#address-cells = <1>; #address-cells = <1>;
@ -640,6 +641,7 @@ tca9548@71 {
reg = <0x71>; reg = <0x71>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
i2c-mux-idle-disconnect;
sff5_i2c: i2c@1 { sff5_i2c: i2c@1 {
#address-cells = <1>; #address-cells = <1>;

1
arch/arm/configs/davinci_all_defconfig
View File

@ -167,6 +167,7 @@ CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y CONFIG_FIRMWARE_EDID=y
CONFIG_FB_DA8XX=y CONFIG_FB_DA8XX=y
CONFIG_BACKLIGHT_PWM=m CONFIG_BACKLIGHT_PWM=m
CONFIG_BACKLIGHT_GPIO=m
CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y CONFIG_LOGO=y
CONFIG_SOUND=m CONFIG_SOUND=m

1
arch/arm/configs/imx_v6_v7_defconfig
View File

@ -276,6 +276,7 @@ CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m CONFIG_VIDEO_OV5645=m
CONFIG_IMX_IPUV3_CORE=y CONFIG_IMX_IPUV3_CORE=y
CONFIG_DRM=y CONFIG_DRM=y
CONFIG_DRM_MSM=y
CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_LVDS=y
CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_SEIKO_43WVF1G=y CONFIG_DRM_PANEL_SEIKO_43WVF1G=y

12
arch/arm/configs/omap2plus_defconfig
View File

@ -356,15 +356,15 @@ CONFIG_DRM_OMAP_CONNECTOR_HDMI=m
CONFIG_DRM_OMAP_CONNECTOR_ANALOG_TV=m CONFIG_DRM_OMAP_CONNECTOR_ANALOG_TV=m
CONFIG_DRM_OMAP_PANEL_DPI=m CONFIG_DRM_OMAP_PANEL_DPI=m
CONFIG_DRM_OMAP_PANEL_DSI_CM=m CONFIG_DRM_OMAP_PANEL_DSI_CM=m
CONFIG_DRM_OMAP_PANEL_SONY_ACX565AKM=m
CONFIG_DRM_OMAP_PANEL_LGPHILIPS_LB035Q02=m
CONFIG_DRM_OMAP_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_OMAP_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_OMAP_PANEL_TPO_TD043MTEA1=m
CONFIG_DRM_OMAP_PANEL_NEC_NL8048HL11=m
CONFIG_DRM_TILCDC=m CONFIG_DRM_TILCDC=m
CONFIG_DRM_PANEL_SIMPLE=m CONFIG_DRM_PANEL_SIMPLE=m
CONFIG_DRM_TI_TFP410=m CONFIG_DRM_TI_TFP410=m
CONFIG_DRM_PANEL_LG_LB035Q02=m
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
CONFIG_FB=y CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y CONFIG_FIRMWARE_EDID=y
CONFIG_FB_MODE_HELPERS=y CONFIG_FB_MODE_HELPERS=y

4
arch/arm/mach-davinci/dm365.c
View File

@ -462,8 +462,8 @@ static s8 dm365_queue_priority_mapping[][2] = {
}; };
static const struct dma_slave_map dm365_edma_map[] = { static const struct dma_slave_map dm365_edma_map[] = {
{ "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) }, { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
{ "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) }, { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
{ "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) }, { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
{ "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) }, { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
{ "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) }, { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },

11
arch/arm/mach-omap2/pdata-quirks.c
View File

@ -89,6 +89,13 @@ static struct iommu_platform_data omap3_iommu_pdata = {
.reset_name = "mmu", .reset_name = "mmu",
.assert_reset = omap_device_assert_hardreset, .assert_reset = omap_device_assert_hardreset,
.deassert_reset = omap_device_deassert_hardreset, .deassert_reset = omap_device_deassert_hardreset,
.device_enable = omap_device_enable,
.device_idle = omap_device_idle,
};
static struct iommu_platform_data omap3_iommu_isp_pdata = {
.device_enable = omap_device_enable,
.device_idle = omap_device_idle,
}; };
static int omap3_sbc_t3730_twl_callback(struct device *dev, static int omap3_sbc_t3730_twl_callback(struct device *dev,
@ -424,6 +431,8 @@ static struct iommu_platform_data omap4_iommu_pdata = {
.reset_name = "mmu_cache", .reset_name = "mmu_cache",
.assert_reset = omap_device_assert_hardreset, .assert_reset = omap_device_assert_hardreset,
.deassert_reset = omap_device_deassert_hardreset, .deassert_reset = omap_device_deassert_hardreset,
.device_enable = omap_device_enable,
.device_idle = omap_device_idle,
}; };
#endif #endif
@ -617,6 +626,8 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = {
#ifdef CONFIG_ARCH_OMAP3 #ifdef CONFIG_ARCH_OMAP3
OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu", OF_DEV_AUXDATA("ti,omap2-iommu", 0x5d000000, "5d000000.mmu",
&omap3_iommu_pdata), &omap3_iommu_pdata),
OF_DEV_AUXDATA("ti,omap2-iommu", 0x480bd400, "480bd400.mmu",
&omap3_iommu_isp_pdata),
OF_DEV_AUXDATA("ti,omap3-smartreflex-core", 0x480cb000, OF_DEV_AUXDATA("ti,omap3-smartreflex-core", 0x480cb000,
"480cb000.smartreflex", &omap_sr_pdata[OMAP_SR_CORE]), "480cb000.smartreflex", &omap_sr_pdata[OMAP_SR_CORE]),
OF_DEV_AUXDATA("ti,omap3-smartreflex-mpu-iva", 0x480c9000, OF_DEV_AUXDATA("ti,omap3-smartreflex-mpu-iva", 0x480c9000,

9
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
View File

@ -63,3 +63,12 @@ ext_rgmii_phy: ethernet-phy@1 {
reg = <1>; reg = <1>;
}; };
}; };
&reg_dc1sw {
/*
* Ethernet PHY needs 30ms to properly power up and some more
* to initialize. 100ms should be plenty of time to finish
* whole process.
*/
regulator-enable-ramp-delay = <100000>;
};

6
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
View File

@ -159,6 +159,12 @@ &ohci1 {
}; };
&reg_dc1sw { &reg_dc1sw {
/*
* Ethernet PHY needs 30ms to properly power up and some more
* to initialize. 100ms should be plenty of time to finish
* whole process.
*/
regulator-enable-ramp-delay = <100000>;
regulator-name = "vcc-phy"; regulator-name = "vcc-phy";
}; };

9
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@ -142,15 +142,6 @@ osc32k: osc32k_clk {
clock-output-names = "ext-osc32k"; clock-output-names = "ext-osc32k";
}; };
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci { psci {
compatible = "arm,psci-0.2"; compatible = "arm,psci-0.2";
method = "smc"; method = "smc";

5
arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi
View File

@ -42,13 +42,14 @@ pinconf: pinconf@140000 {
pinmux: pinmux@14029c { pinmux: pinmux@14029c {
compatible = "pinctrl-single"; compatible = "pinctrl-single";
reg = <0x0014029c 0x250>; reg = <0x0014029c 0x26c>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
pinctrl-single,register-width = <32>; pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xf>; pinctrl-single,function-mask = <0xf>;
pinctrl-single,gpio-range = < pinctrl-single,gpio-range = <
&range 0 154 MODE_GPIO &range 0 91 MODE_GPIO
&range 95 60 MODE_GPIO
>; >;
range: gpio-range { range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>; #pinctrl-single,gpio-range-cells = <3>;

3
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
View File

@ -464,8 +464,7 @@ gpio_hsls: gpio@d0000 {
<&pinmux 108 16 27>, <&pinmux 108 16 27>,
<&pinmux 135 77 6>, <&pinmux 135 77 6>,
<&pinmux 141 67 4>, <&pinmux 141 67 4>,
<&pinmux 145 149 6>, <&pinmux 145 149 6>;
<&pinmux 151 91 4>;
}; };
i2c1: i2c@e0000 { i2c1: i2c@e0000 {

36
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@ -33,7 +33,7 @@ cpu@0 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>; next-level-cache = <&cluster0_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@1 { cpu@1 {
@ -49,7 +49,7 @@ cpu@1 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>; next-level-cache = <&cluster0_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@100 { cpu@100 {
@ -65,7 +65,7 @@ cpu@100 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>; next-level-cache = <&cluster1_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@101 { cpu@101 {
@ -81,7 +81,7 @@ cpu@101 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>; next-level-cache = <&cluster1_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@200 { cpu@200 {
@ -97,7 +97,7 @@ cpu@200 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>; next-level-cache = <&cluster2_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@201 { cpu@201 {
@ -113,7 +113,7 @@ cpu@201 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>; next-level-cache = <&cluster2_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@300 { cpu@300 {
@ -129,7 +129,7 @@ cpu@300 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>; next-level-cache = <&cluster3_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@301 { cpu@301 {
@ -145,7 +145,7 @@ cpu@301 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>; next-level-cache = <&cluster3_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@400 { cpu@400 {
@ -161,7 +161,7 @@ cpu@400 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>; next-level-cache = <&cluster4_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@401 { cpu@401 {
@ -177,7 +177,7 @@ cpu@401 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>; next-level-cache = <&cluster4_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@500 { cpu@500 {
@ -193,7 +193,7 @@ cpu@500 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>; next-level-cache = <&cluster5_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@501 { cpu@501 {
@ -209,7 +209,7 @@ cpu@501 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>; next-level-cache = <&cluster5_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@600 { cpu@600 {
@ -225,7 +225,7 @@ cpu@600 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>; next-level-cache = <&cluster6_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@601 { cpu@601 {
@ -241,7 +241,7 @@ cpu@601 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>; next-level-cache = <&cluster6_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@700 { cpu@700 {
@ -257,7 +257,7 @@ cpu@700 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>; next-level-cache = <&cluster7_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cpu@701 { cpu@701 {
@ -273,7 +273,7 @@ cpu@701 {
i-cache-line-size = <64>; i-cache-line-size = <64>;
i-cache-sets = <192>; i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>; next-level-cache = <&cluster7_l2>;
cpu-idle-states = <&cpu_pw20>; cpu-idle-states = <&cpu_pw15>;
}; };
cluster0_l2: l2-cache0 { cluster0_l2: l2-cache0 {
@ -340,9 +340,9 @@ cluster7_l2: l2-cache7 {
cache-level = <2>; cache-level = <2>;
}; };
cpu_pw20: cpu-pw20 { cpu_pw15: cpu-pw15 {
compatible = "arm,idle-state"; compatible = "arm,idle-state";
idle-state-name = "PW20"; idle-state-name = "PW15";
arm,psci-suspend-param = <0x0>; arm,psci-suspend-param = <0x0>;
entry-latency-us = <2000>; entry-latency-us = <2000>;
exit-latency-us = <2000>; exit-latency-us = <2000>;

6
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -694,7 +694,7 @@ usdhc1: mmc@30b40000 {
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>; reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_DUMMY>, clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
<&clk IMX8MM_CLK_NAND_USDHC_BUS>, <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC1_ROOT>; <&clk IMX8MM_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
@ -710,7 +710,7 @@ usdhc2: mmc@30b50000 {
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>; reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_DUMMY>, clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
<&clk IMX8MM_CLK_NAND_USDHC_BUS>, <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC2_ROOT>; <&clk IMX8MM_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
@ -724,7 +724,7 @@ usdhc3: mmc@30b60000 {
compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b60000 0x10000>; reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_DUMMY>, clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
<&clk IMX8MM_CLK_NAND_USDHC_BUS>, <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
<&clk IMX8MM_CLK_USDHC3_ROOT>; <&clk IMX8MM_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";

6
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@ -569,7 +569,7 @@ usdhc1: mmc@30b40000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>; reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_DUMMY>, clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
<&clk IMX8MN_CLK_NAND_USDHC_BUS>, <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC1_ROOT>; <&clk IMX8MN_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
@ -585,7 +585,7 @@ usdhc2: mmc@30b50000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>; reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_DUMMY>, clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
<&clk IMX8MN_CLK_NAND_USDHC_BUS>, <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC2_ROOT>; <&clk IMX8MN_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
@ -599,7 +599,7 @@ usdhc3: mmc@30b60000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b60000 0x10000>; reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_DUMMY>, clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
<&clk IMX8MN_CLK_NAND_USDHC_BUS>, <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC3_ROOT>; <&clk IMX8MN_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";

4
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
View File

@ -89,8 +89,8 @@ reg_arm: regulator-arm {
regulator-min-microvolt = <900000>; regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>; regulator-max-microvolt = <1000000>;
gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
states = <1000000 0x0 states = <1000000 0x1
900000 0x1>; 900000 0x0>;
regulator-always-on; regulator-always-on;
}; };
}; };

4
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -850,7 +850,7 @@ usdhc1: mmc@30b40000 {
"fsl,imx7d-usdhc"; "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>; reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_DUMMY>, clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>, <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
<&clk IMX8MQ_CLK_USDHC1_ROOT>; <&clk IMX8MQ_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";
@ -867,7 +867,7 @@ usdhc2: mmc@30b50000 {
"fsl,imx7d-usdhc"; "fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>; reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_DUMMY>, clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
<&clk IMX8MQ_CLK_NAND_USDHC_BUS>, <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
<&clk IMX8MQ_CLK_USDHC2_ROOT>; <&clk IMX8MQ_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per"; clock-names = "ipg", "ahb", "per";

13
arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
View File

@ -60,11 +60,6 @@ exp_usb3_vbus: usb3-vbus {
gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>; gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
}; };
usb3_phy: usb3-phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&exp_usb3_vbus>;
};
vsdc_reg: vsdc-reg { vsdc_reg: vsdc-reg {
compatible = "regulator-gpio"; compatible = "regulator-gpio";
regulator-name = "vsdc"; regulator-name = "vsdc";
@ -255,10 +250,16 @@ &usb2 {
status = "okay"; status = "okay";
}; };
&comphy2 {
connector {
compatible = "usb-a-connector";
phy-supply = <&exp_usb3_vbus>;
};
};
&usb3 { &usb3 {
status = "okay"; status = "okay";
phys = <&comphy2 0>; phys = <&comphy2 0>;
usb-phy = <&usb3_phy>;
}; };
&mdio { &mdio {

2
arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
View File

@ -44,7 +44,7 @@ edp_panel: edp-panel {
power-supply = <&pp3300_disp>; power-supply = <&pp3300_disp>;
panel-timing { panel-timing {
clock-frequency = <266604720>; clock-frequency = <266666667>;
hactive = <2400>; hactive = <2400>;
hfront-porch = <48>; hfront-porch = <48>;
hback-porch = <84>; hback-porch = <84>;

4
arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts
View File

@ -644,7 +644,7 @@ &u2phy0 {
status = "okay"; status = "okay";
u2phy0_host: host-port { u2phy0_host: host-port {
phy-supply = <&vcc5v0_host>; phy-supply = <&vcc5v0_typec>;
status = "okay"; status = "okay";
}; };
@ -712,7 +712,7 @@ &usbdrd3_0 {
&usbdrd_dwc3_0 { &usbdrd_dwc3_0 {
status = "okay"; status = "okay";
dr_mode = "otg"; dr_mode = "host";
}; };
&usbdrd3_1 { &usbdrd3_1 {

12
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts
View File

@ -173,7 +173,7 @@ vdd_log: vdd-log {
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <800000>; regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>; regulator-max-microvolt = <1700000>;
vin-supply = <&vcc5v0_sys>; vin-supply = <&vcc5v0_sys>;
}; };
}; };
@ -247,8 +247,8 @@ &i2c0 {
rk808: pmic@1b { rk808: pmic@1b {
compatible = "rockchip,rk808"; compatible = "rockchip,rk808";
reg = <0x1b>; reg = <0x1b>;
interrupt-parent = <&gpio1>; interrupt-parent = <&gpio3>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>; interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>; #clock-cells = <1>;
clock-output-names = "xin32k", "rk808-clkout2"; clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default"; pinctrl-names = "default";
@ -574,7 +574,7 @@ pcie_pwr_en: pcie-pwr-en {
pmic { pmic {
pmic_int_l: pmic-int-l { pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
}; };
vsel1_gpio: vsel1-gpio { vsel1_gpio: vsel1-gpio {
@ -624,7 +624,6 @@ &saradc {
&sdmmc { &sdmmc {
bus-width = <4>; bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed; cap-sd-highspeed;
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
disable-wp; disable-wp;
@ -636,8 +635,7 @@ &sdmmc {
&sdhci { &sdhci {
bus-width = <8>; bus-width = <8>;
mmc-hs400-1_8v; mmc-hs200-1_8v;
mmc-hs400-enhanced-strobe;
non-removable; non-removable;
status = "okay"; status = "okay";
}; };

18
drivers/bus/ti-sysc.c
View File

@ -74,6 +74,7 @@ static const char * const clock_names[SYSC_MAX_CLOCKS] = {
* @clk_disable_quirk: module specific clock disable quirk * @clk_disable_quirk: module specific clock disable quirk
* @reset_done_quirk: module specific reset done quirk * @reset_done_quirk: module specific reset done quirk
* @module_enable_quirk: module specific enable quirk * @module_enable_quirk: module specific enable quirk
* @module_disable_quirk: module specific disable quirk
*/ */
struct sysc { struct sysc {
struct device *dev; struct device *dev;
@ -100,6 +101,7 @@ struct sysc {
void (*clk_disable_quirk)(struct sysc *sysc); void (*clk_disable_quirk)(struct sysc *sysc);
void (*reset_done_quirk)(struct sysc *sysc); void (*reset_done_quirk)(struct sysc *sysc);
void (*module_enable_quirk)(struct sysc *sysc); void (*module_enable_quirk)(struct sysc *sysc);
void (*module_disable_quirk)(struct sysc *sysc);
}; };
static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
@ -959,6 +961,9 @@ static int sysc_disable_module(struct device *dev)
if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
return 0; return 0;
if (ddata->module_disable_quirk)
ddata->module_disable_quirk(ddata);
regbits = ddata->cap->regbits; regbits = ddata->cap->regbits;
reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
@ -1248,6 +1253,9 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
SYSC_MODULE_QUIRK_SGX), SYSC_MODULE_QUIRK_SGX),
SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
SYSC_MODULE_QUIRK_WDT), SYSC_MODULE_QUIRK_WDT),
/* Watchdog on am3 and am4 */
SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
#ifdef DEBUG #ifdef DEBUG
SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0), SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
@ -1440,14 +1448,14 @@ static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
!(val & 0x10), 100, !(val & 0x10), 100,
MAX_MODULE_SOFTRESET_WAIT); MAX_MODULE_SOFTRESET_WAIT);
if (error) if (error)
dev_warn(ddata->dev, "wdt disable spr failed\n"); dev_warn(ddata->dev, "wdt disable step1 failed\n");
sysc_write(ddata, wps, 0x5555); sysc_write(ddata, spr, 0x5555);
error = readl_poll_timeout(ddata->module_va + wps, val, error = readl_poll_timeout(ddata->module_va + wps, val,
!(val & 0x10), 100, !(val & 0x10), 100,
MAX_MODULE_SOFTRESET_WAIT); MAX_MODULE_SOFTRESET_WAIT);
if (error) if (error)
dev_warn(ddata->dev, "wdt disable wps failed\n"); dev_warn(ddata->dev, "wdt disable step2 failed\n");
} }
static void sysc_init_module_quirks(struct sysc *ddata) static void sysc_init_module_quirks(struct sysc *ddata)
@ -1471,8 +1479,10 @@ static void sysc_init_module_quirks(struct sysc *ddata)
if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX) if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
ddata->module_enable_quirk = sysc_module_enable_quirk_sgx; ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
}
} }
static int sysc_clockdomain_init(struct sysc *ddata) static int sysc_clockdomain_init(struct sysc *ddata)

2
drivers/soc/imx/soc-imx-scu.c
View File

@ -46,7 +46,7 @@ static ssize_t soc_uid_show(struct device *dev,
hdr->func = IMX_SC_MISC_FUNC_UNIQUE_ID; hdr->func = IMX_SC_MISC_FUNC_UNIQUE_ID;
hdr->size = 1; hdr->size = 1;
ret = imx_scu_call_rpc(soc_ipc_handle, &msg, false); ret = imx_scu_call_rpc(soc_ipc_handle, &msg, true);
if (ret) { if (ret) {
pr_err("%s: get soc uid failed, ret %d\n", __func__, ret); pr_err("%s: get soc uid failed, ret %d\n", __func__, ret);
return ret; return ret;