forked from luck/tmp_suning_uos_patched
riscv: cacheinfo: Fix using smp_processor_id() in preemptible
[ Upstream commit 80709af7325d179b433817f421c85449f2454046 ] Use raw_smp_processor_id instead of smp_processor_id() to fix warning, BUG: using smp_processor_id() in preemptible [00000000] code: init/1 caller is debug_smp_processor_id+0x1c/0x26 CPU: 0 PID: 1 Comm: init Not tainted 5.10.0-rc4 #211 Call Trace: walk_stackframe+0x0/0xaa show_stack+0x32/0x3e dump_stack+0x76/0x90 check_preemption_disabled+0xaa/0xac debug_smp_processor_id+0x1c/0x26 get_cache_size+0x18/0x68 load_elf_binary+0x868/0xece bprm_execve+0x224/0x498 kernel_execve+0xdc/0x142 run_init_process+0x90/0x9e try_to_run_init_process+0x12/0x3c kernel_init+0xb4/0xf8 ret_from_exception+0x0/0xc The issue is found when CONFIG_DEBUG_PREEMPT enabled. Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> [Palmer: Added a comment.] Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -26,7 +26,16 @@ cache_get_priv_group(struct cacheinfo *this_leaf)
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static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type)
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{
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(smp_processor_id());
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/*
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* Using raw_smp_processor_id() elides a preemptability check, but this
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* is really indicative of a larger problem: the cacheinfo UABI assumes
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* that cores have a homonogenous view of the cache hierarchy. That
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* happens to be the case for the current set of RISC-V systems, but
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* likely won't be true in general. Since there's no way to provide
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* correct information for these systems via the current UABI we're
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* just eliding the check for now.
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*/
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(raw_smp_processor_id());
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struct cacheinfo *this_leaf;
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int index;
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