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irqchip: crossbar: Introduce ti, irqs-skip to skip irqs that bypass crossbar

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When, in the system due to varied reasons, interrupts might be unusable
due to hardware behavior, but register maps do exist, then those interrupts
should be skipped while mapping irq to crossbars.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Link: https://lkml.kernel.org/r/1403766634-18543-4-git-send-email-r.sricharan@ti.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Nishanth Menon 2014-06-26 12:40:21 +05:30 committed by Jason Cooper
parent 6f16fc878a
commit 64e0f8ba5c
2 changed files with 26 additions and 0 deletions
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6
Documentation/devicetree/bindings/arm/omap/crossbar.txt
View File

@ -17,6 +17,11 @@ Required properties:
so crossbar bar driver should not consider them as free
lines.
Optional properties:
- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
crossbar. These irqs have a crossbar register, but still cannot be used.
Examples:
crossbar_mpu: @4a020000 {
compatible = "ti,irq-crossbar";
@ -24,4 +29,5 @@ Examples:
ti,max-irqs = <160>;
ti,reg-size = <2>;
ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
ti,irqs-skip = <10 133 139 140>;
};

20
drivers/irqchip/irq-crossbar.c
View File

@ -18,6 +18,7 @@
#define IRQ_FREE -1
#define IRQ_RESERVED -2
#define IRQ_SKIP -3
#define GIC_IRQ_START 32
/*
@ -160,6 +161,25 @@ static int __init crossbar_of_init(struct device_node *node)
}
}
/* Skip irqs hardwired to bypass the crossbar */
irqsr = of_get_property(node, "ti,irqs-skip", &size);
if (irqsr) {
size /= sizeof(__be32);
for (i = 0; i < size; i++) {
of_property_read_u32_index(node,
"ti,irqs-skip",
i, &entry);
if (entry > max) {
pr_err("Invalid skip entry\n");
ret = -EINVAL;
goto err3;
}
cb->irq_map[entry] = IRQ_SKIP;
}
}
cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL);
if (!cb->register_offsets)
goto err3;