forked from luck/tmp_suning_uos_patched
[media] mt2063: Remove several unused parameters
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Mauro Carvalho Chehab
parent
fd1126cac0
commit
66aea30d32
@ -124,18 +124,6 @@ enum MT2063_Mask_Bits {
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* specifies the tuning algorithm parameter to be read/written.
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*/
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enum MT2063_Param {
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/* tuner address set by MT2063_Open() */
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MT2063_IC_ADDR,
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/* max number of MT2063 tuners set by MT_TUNER_CNT in mt_userdef.h */
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MT2063_MAX_OPEN,
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/* current number of open MT2063 tuners set by MT2063_Open() */
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MT2063_NUM_OPEN,
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/* crystal frequency (default: 16000000 Hz) */
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MT2063_SRO_FREQ,
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/* min tuning step size (default: 50000 Hz) */
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MT2063_STEPSIZE,
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@ -145,66 +133,15 @@ enum MT2063_Param {
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/* LO1 Frequency set by MT2063_Tune() */
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MT2063_LO1_FREQ,
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/* LO1 minimum step size (default: 250000 Hz) */
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MT2063_LO1_STEPSIZE,
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/* LO1 FracN keep-out region (default: 999999 Hz) */
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MT2063_LO1_FRACN_AVOID_PARAM,
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/* Current 1st IF in use set by MT2063_Tune() */
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MT2063_IF1_ACTUAL,
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/* Requested 1st IF set by MT2063_Tune() */
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MT2063_IF1_REQUEST,
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/* Center of 1st IF SAW filter (default: 1218000000 Hz) */
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MT2063_IF1_CENTER,
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/* Bandwidth of 1st IF SAW filter (default: 20000000 Hz) */
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MT2063_IF1_BW,
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/* zero-IF bandwidth (default: 2000000 Hz) */
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MT2063_ZIF_BW,
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/* LO2 Frequency set by MT2063_Tune() */
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MT2063_LO2_FREQ,
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/* LO2 minimum step size (default: 50000 Hz) */
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MT2063_LO2_STEPSIZE,
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/* LO2 FracN keep-out region (default: 374999 Hz) */
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MT2063_LO2_FRACN_AVOID,
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/* output center frequency set by MT2063_Tune() */
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MT2063_OUTPUT_FREQ,
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/* output bandwidth set by MT2063_Tune() */
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MT2063_OUTPUT_BW,
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/* min inter-tuner LO separation (default: 1000000 Hz) */
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MT2063_LO_SEPARATION,
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/* ID of avoid-spurs algorithm in use compile-time constant */
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MT2063_AS_ALG,
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/* max # of intra-tuner harmonics (default: 15) */
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MT2063_MAX_HARM1,
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/* max # of inter-tuner harmonics (default: 7) */
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MT2063_MAX_HARM2,
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/* # of 1st IF exclusion zones used set by MT2063_Tune() */
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MT2063_EXCL_ZONES,
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/* # of spurs found/avoided set by MT2063_Tune() */
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MT2063_NUM_SPURS,
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/* >0 spurs avoided set by MT2063_Tune() */
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MT2063_SPUR_AVOIDED,
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/* >0 spurs in output (mathematically) set by MT2063_Tune() */
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MT2063_SPUR_PRESENT,
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/* Receiver Mode for some parameters. 1 is DVB-T */
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MT2063_RCVR_MODE,
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@ -247,24 +184,6 @@ enum MT2063_Param {
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/* Selects, which DNC is activ */
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MT2063_DNC_OUTPUT_ENABLE,
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/* VGA gain code */
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MT2063_VGAGC,
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/* VGA bias current */
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MT2063_VGAOI,
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/* TAGC, determins the speed of the AGC */
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MT2063_TAGC,
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/* AMP gain code */
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MT2063_AMPGC,
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/* Control setting to avoid DECT freqs (default: MT_AVOID_BOTH) */
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MT2063_AVOID_DECT,
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/* Cleartune filter selection: 0 - by IC (default), 1 - by software */
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MT2063_CTFILT_SW,
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MT2063_EOP /* last entry in enumerated list */
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};
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@ -1184,16 +1103,10 @@ static u32 MT2063_AvoidSpurs(void *h, struct MT2063_AvoidSpursData_t * pAS_Info)
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return (status);
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}
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//end of mt2063_spuravoid.c
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//=================================================================
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//#################################################################
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//=================================================================
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/*
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** The expected version of MT_AvoidSpursData_t
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** If the version is different, an updated file is needed from Microtune
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*/
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/* Expecting version 1.21 of the Spur Avoidance API */
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typedef enum {
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MT2063_SET_ATTEN,
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@ -1201,9 +1114,8 @@ typedef enum {
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MT2063_DECR_ATTEN
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} MT2063_ATTEN_CNTL_MODE;
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//#define TUNER_MT2063_OPTIMIZATION
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/*
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** Constants used by the tuning algorithm
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* Constants used by the tuning algorithm
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*/
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#define MT2063_REF_FREQ (16000000UL) /* Reference oscillator Frequency (in Hz) */
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#define MT2063_IF1_BW (22000000UL) /* The IF1 filter bandwidth (in Hz) */
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@ -1232,16 +1144,6 @@ typedef enum {
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#define MT2063_B2 (0x9D)
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#define MT2063_B3 (0x9E)
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/*
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** The number of Tuner Registers
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*/
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static const u32 MT2063_Num_Registers = MT2063_REG_END_REGS;
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#define USE_GLOBAL_TUNER 0
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static u32 nMT2063MaxTuners = 1;
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static u32 nMT2063OpenTuners = 0;
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/*
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** Constants for setting receiver modes.
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** (6 modes defined at this time, enumerated by MT2063_RCVR_MODES)
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@ -1372,8 +1274,6 @@ static u32 MT2063_GetLocked(struct mt2063_state *state)
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** param Description
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** ---------------------- --------------------------------
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** MT2063_IC_ADDR Serial Bus address of this tuner
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** MT2063_MAX_OPEN Max # of MT2063's allowed open
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** MT2063_NUM_OPEN # of MT2063's open
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** MT2063_SRO_FREQ crystal frequency
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** MT2063_STEPSIZE minimum tuning step size
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** MT2063_INPUT_FREQ input center frequency
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@ -1457,31 +1357,6 @@ static u32 MT2063_GetParam(struct mt2063_state *state, enum MT2063_Param param,
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return -EINVAL;
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switch (param) {
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/* Serial Bus address of this tuner */
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case MT2063_IC_ADDR:
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*pValue = state->config->tuner_address;
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break;
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/* Max # of MT2063's allowed to be open */
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case MT2063_MAX_OPEN:
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*pValue = nMT2063MaxTuners;
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break;
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/* # of MT2063's open */
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case MT2063_NUM_OPEN:
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*pValue = nMT2063OpenTuners;
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break;
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/* crystal frequency */
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case MT2063_SRO_FREQ:
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*pValue = state->AS_Data.f_ref;
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break;
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/* minimum tuning step size */
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case MT2063_STEPSIZE:
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*pValue = state->AS_Data.f_LO2_Step;
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break;
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/* input center frequency */
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case MT2063_INPUT_FREQ:
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*pValue = state->AS_Data.f_in;
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@ -1506,31 +1381,6 @@ static u32 MT2063_GetParam(struct mt2063_state *state, enum MT2063_Param param,
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*pValue = state->AS_Data.f_LO1;
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break;
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/* LO1 minimum step size */
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case MT2063_LO1_STEPSIZE:
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*pValue = state->AS_Data.f_LO1_Step;
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break;
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/* LO1 FracN keep-out region */
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case MT2063_LO1_FRACN_AVOID_PARAM:
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*pValue = state->AS_Data.f_LO1_FracN_Avoid;
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break;
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/* Current 1st IF in use */
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case MT2063_IF1_ACTUAL:
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*pValue = state->f_IF1_actual;
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break;
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/* Requested 1st IF */
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case MT2063_IF1_REQUEST:
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*pValue = state->AS_Data.f_if1_Request;
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break;
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/* Center of 1st IF SAW filter */
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case MT2063_IF1_CENTER:
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*pValue = state->AS_Data.f_if1_Center;
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break;
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/* Bandwidth of 1st IF SAW filter */
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case MT2063_IF1_BW:
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*pValue = state->AS_Data.f_if1_bw;
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@ -1568,11 +1418,6 @@ static u32 MT2063_GetParam(struct mt2063_state *state, enum MT2063_Param param,
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*pValue = state->AS_Data.f_LO2;
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break;
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/* LO2 minimum step size */
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case MT2063_LO2_STEPSIZE:
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*pValue = state->AS_Data.f_LO2_Step;
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break;
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/* LO2 FracN keep-out region */
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case MT2063_LO2_FRACN_AVOID:
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*pValue = state->AS_Data.f_LO2_FracN_Avoid;
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@ -1588,41 +1433,6 @@ static u32 MT2063_GetParam(struct mt2063_state *state, enum MT2063_Param param,
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*pValue = state->AS_Data.f_out_bw - 750000;
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break;
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/* min inter-tuner LO separation */
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case MT2063_LO_SEPARATION:
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*pValue = state->AS_Data.f_min_LO_Separation;
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break;
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/* max # of intra-tuner harmonics */
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case MT2063_MAX_HARM1:
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*pValue = state->AS_Data.maxH1;
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break;
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/* max # of inter-tuner harmonics */
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case MT2063_MAX_HARM2:
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*pValue = state->AS_Data.maxH2;
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break;
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/* # of 1st IF exclusion zones */
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case MT2063_EXCL_ZONES:
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*pValue = state->AS_Data.nZones;
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break;
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/* # of spurs found/avoided */
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case MT2063_NUM_SPURS:
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*pValue = state->AS_Data.nSpursFound;
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break;
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/* >0 spurs avoided */
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case MT2063_SPUR_AVOIDED:
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*pValue = state->AS_Data.bSpurAvoided;
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break;
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/* >0 spurs in output (mathematically) */
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case MT2063_SPUR_PRESENT:
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*pValue = state->AS_Data.bSpurPresent;
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break;
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/* Predefined receiver setup combination */
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case MT2063_RCVR_MODE:
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*pValue = state->rcvr_mode;
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@ -1766,37 +1576,6 @@ static u32 MT2063_GetParam(struct mt2063_state *state, enum MT2063_Param param,
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}
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break;
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/* Get VGA Gain Code */
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case MT2063_VGAGC:
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*pValue = ((state->reg[MT2063_REG_VGA_GAIN] & 0x0C) >> 2);
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break;
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/* Get VGA bias current */
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case MT2063_VGAOI:
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*pValue = (state->reg[MT2063_REG_RSVD_31] & 0x07);
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break;
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/* Get TAGC setting */
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case MT2063_TAGC:
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*pValue = (state->reg[MT2063_REG_RSVD_1E] & 0x03);
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break;
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/* Get AMP Gain Code */
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case MT2063_AMPGC:
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*pValue = (state->reg[MT2063_REG_TEMP_SEL] & 0x03);
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break;
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/* Avoid DECT Frequencies */
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case MT2063_AVOID_DECT:
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*pValue = state->AS_Data.avoidDECT;
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break;
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/* Cleartune filter selection: 0 - by IC (default), 1 - by software */
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case MT2063_CTFILT_SW:
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*pValue = state->ctfilt_sw;
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break;
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case MT2063_EOP:
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default:
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status |= -ERANGE;
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}
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@ -2136,22 +1915,6 @@ static u32 MT2063_SetParam(struct mt2063_state *state,
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u8 val = 0;
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switch (param) {
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/* crystal frequency */
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case MT2063_SRO_FREQ:
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state->AS_Data.f_ref = nValue;
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state->AS_Data.f_LO1_FracN_Avoid = 0;
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state->AS_Data.f_LO2_FracN_Avoid = nValue / 80 - 1;
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state->AS_Data.f_LO1_Step = nValue / 64;
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state->AS_Data.f_if1_Center =
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(state->AS_Data.f_ref / 8) *
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(state->reg[MT2063_REG_FIFFC] + 640);
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break;
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/* minimum tuning step size */
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case MT2063_STEPSIZE:
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state->AS_Data.f_LO2_Step = nValue;
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break;
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/* LO1 frequency */
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case MT2063_LO1_FREQ:
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{
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@ -2245,21 +2008,6 @@ static u32 MT2063_SetParam(struct mt2063_state *state,
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}
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break;
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/* LO1 minimum step size */
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case MT2063_LO1_STEPSIZE:
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state->AS_Data.f_LO1_Step = nValue;
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break;
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/* LO1 FracN keep-out region */
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case MT2063_LO1_FRACN_AVOID_PARAM:
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state->AS_Data.f_LO1_FracN_Avoid = nValue;
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break;
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/* Requested 1st IF */
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case MT2063_IF1_REQUEST:
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state->AS_Data.f_if1_Request = nValue;
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break;
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/* zero-IF bandwidth */
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case MT2063_ZIF_BW:
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state->AS_Data.f_zif_bw = nValue;
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@ -2352,11 +2100,6 @@ static u32 MT2063_SetParam(struct mt2063_state *state,
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}
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break;
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/* LO2 minimum step size */
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case MT2063_LO2_STEPSIZE:
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state->AS_Data.f_LO2_Step = nValue;
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break;
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/* LO2 FracN keep-out region */
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case MT2063_LO2_FRACN_AVOID:
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state->AS_Data.f_LO2_FracN_Avoid = nValue;
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@ -2372,21 +2115,6 @@ static u32 MT2063_SetParam(struct mt2063_state *state,
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state->AS_Data.f_out_bw = nValue + 750000;
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break;
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/* min inter-tuner LO separation */
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case MT2063_LO_SEPARATION:
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state->AS_Data.f_min_LO_Separation = nValue;
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break;
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/* max # of intra-tuner harmonics */
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case MT2063_MAX_HARM1:
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state->AS_Data.maxH1 = nValue;
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break;
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/* max # of inter-tuner harmonics */
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case MT2063_MAX_HARM2:
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state->AS_Data.maxH2 = nValue;
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break;
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case MT2063_RCVR_MODE:
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status |=
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MT2063_SetReceiverMode(state,
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@ -2610,94 +2338,6 @@ static u32 MT2063_SetParam(struct mt2063_state *state,
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}
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break;
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case MT2063_VGAGC:
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/* Set VGA gain code */
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val =
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(state->
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reg[MT2063_REG_VGA_GAIN] & (u8) ~ 0x0C) |
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((nValue & 0x03) << 2);
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if (state->reg[MT2063_REG_VGA_GAIN] != val) {
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status |=
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MT2063_SetReg(state, MT2063_REG_VGA_GAIN,
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val);
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}
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break;
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case MT2063_VGAOI:
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/* Set VGA bias current */
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val =
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(state->
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reg[MT2063_REG_RSVD_31] & (u8) ~ 0x07) |
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(nValue & 0x07);
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if (state->reg[MT2063_REG_RSVD_31] != val) {
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status |=
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MT2063_SetReg(state, MT2063_REG_RSVD_31,
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val);
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}
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break;
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case MT2063_TAGC:
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/* Set TAGC */
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val =
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(state->
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reg[MT2063_REG_RSVD_1E] & (u8) ~ 0x03) |
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(nValue & 0x03);
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if (state->reg[MT2063_REG_RSVD_1E] != val) {
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status |=
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MT2063_SetReg(state, MT2063_REG_RSVD_1E,
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val);
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}
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break;
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case MT2063_AMPGC:
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/* Set Amp gain code */
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val =
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(state->
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reg[MT2063_REG_TEMP_SEL] & (u8) ~ 0x03) |
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(nValue & 0x03);
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if (state->reg[MT2063_REG_TEMP_SEL] != val) {
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status |=
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MT2063_SetReg(state, MT2063_REG_TEMP_SEL,
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val);
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}
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break;
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/* Avoid DECT Frequencies */
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case MT2063_AVOID_DECT:
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{
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enum MT2063_DECT_Avoid_Type newAvoidSetting =
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(enum MT2063_DECT_Avoid_Type)nValue;
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if ((newAvoidSetting >=
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MT2063_NO_DECT_AVOIDANCE)
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&& (newAvoidSetting <= MT2063_AVOID_BOTH)) {
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state->AS_Data.avoidDECT =
|
||||
newAvoidSetting;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
/* Cleartune filter selection: 0 - by IC (default), 1 - by software */
|
||||
case MT2063_CTFILT_SW:
|
||||
state->ctfilt_sw = (nValue & 0x01);
|
||||
break;
|
||||
|
||||
/* These parameters are read-only */
|
||||
case MT2063_IC_ADDR:
|
||||
case MT2063_MAX_OPEN:
|
||||
case MT2063_NUM_OPEN:
|
||||
case MT2063_INPUT_FREQ:
|
||||
case MT2063_IF1_ACTUAL:
|
||||
case MT2063_IF1_CENTER:
|
||||
case MT2063_IF1_BW:
|
||||
case MT2063_AS_ALG:
|
||||
case MT2063_EXCL_ZONES:
|
||||
case MT2063_SPUR_AVOIDED:
|
||||
case MT2063_NUM_SPURS:
|
||||
case MT2063_SPUR_PRESENT:
|
||||
case MT2063_ACLNA:
|
||||
case MT2063_ACRF:
|
||||
case MT2063_ACFIF:
|
||||
case MT2063_EOP:
|
||||
default:
|
||||
status |= -ERANGE;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user