forked from luck/tmp_suning_uos_patched
dt-bindings: spi: meson: convert to yaml
Now that we have the DT validation in place, let's convert the device tree bindings for the Amlogic SPI controllers over to two separate YAML schemas. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Neil Armstrong
Rob Herring
parent
78db5580af
commit
66de150a88
|
|
@ -0,0 +1,67 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
# Copyright 2019 BayLibre, SAS
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/spi/amlogic,meson-gx-spicc.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Amlogic Meson SPI Communication Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "spi-controller.yaml#"
|
||||
|
||||
description: |
|
||||
The Meson SPICC is a generic SPI controller for general purpose Full-Duplex
|
||||
communications with dedicated 16 words RX/TX PIO FIFOs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amlogic,meson-gx-spicc # SPICC controller on Amlogic GX and compatible SoCs
|
||||
- amlogic,meson-axg-spicc # SPICC controller on Amlogic AXG and compatible SoCs
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
description: input clock for the baud rate generator
|
||||
items:
|
||||
- const: core
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi@c1108d80 {
|
||||
compatible = "amlogic,meson-gx-spicc";
|
||||
reg = <0xc1108d80 0x80>;
|
||||
interrupts = <112>;
|
||||
clocks = <&clk81>;
|
||||
clock-names = "core";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethernet-switch@0 {
|
||||
compatible = "micrel,ks8995m";
|
||||
spi-max-frequency = <1000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
# Copyright 2019 BayLibre, SAS
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Amlogic Meson SPI Flash Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "spi-controller.yaml#"
|
||||
|
||||
description: |
|
||||
The Meson SPIFC is a controller optimized for communication with SPI
|
||||
NOR memories, without DMA support and a 64-byte unified transmit /
|
||||
receive buffer.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amlogic,meson6-spifc # SPI Flash Controller on Meson6 and compatible SoCs
|
||||
- amlogic,meson-gxbb-spifc # SPI Flash Controller on GXBB and compatible SoCs
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi@c1108c80 {
|
||||
compatible = "amlogic,meson6-spifc";
|
||||
reg = <0xc1108c80 0x80>;
|
||||
clocks = <&clk81>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
flash: flash@0 {
|
||||
compatible = "spansion,m25p80", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
Amlogic Meson SPI controllers
|
||||
|
||||
* SPIFC (SPI Flash Controller)
|
||||
|
||||
The Meson SPIFC is a controller optimized for communication with SPI
|
||||
NOR memories, without DMA support and a 64-byte unified transmit /
|
||||
receive buffer.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "amlogic,meson6-spifc" or "amlogic,meson-gxbb-spifc"
|
||||
- reg: physical base address and length of the controller registers
|
||||
- clocks: phandle of the input clock for the baud rate generator
|
||||
- #address-cells: should be 1
|
||||
- #size-cells: should be 0
|
||||
|
||||
spi@c1108c80 {
|
||||
compatible = "amlogic,meson6-spifc";
|
||||
reg = <0xc1108c80 0x80>;
|
||||
clocks = <&clk81>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
* SPICC (SPI Communication Controller)
|
||||
|
||||
The Meson SPICC is generic SPI controller for general purpose Full-Duplex
|
||||
communications with dedicated 16 words RX/TX PIO FIFOs.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be:
|
||||
"amlogic,meson-gx-spicc" on Amlogic GX and compatible SoCs.
|
||||
"amlogic,meson-axg-spicc" on Amlogic AXG and compatible SoCs
|
||||
- reg: physical base address and length of the controller registers
|
||||
- interrupts: The interrupt specifier
|
||||
- clock-names: Must contain "core"
|
||||
- clocks: phandle of the input clock for the baud rate generator
|
||||
- #address-cells: should be 1
|
||||
- #size-cells: should be 0
|
||||
|
||||
Optional properties:
|
||||
- resets: phandle of the internal reset line
|
||||
|
||||
See ../spi/spi-bus.txt for more details on SPI bus master and slave devices
|
||||
required and optional properties.
|
||||
|
||||
Example :
|
||||
spi@c1108d80 {
|
||||
compatible = "amlogic,meson-gx-spicc";
|
||||
reg = <0xc1108d80 0x80>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "core";
|
||||
clocks = <&clk81>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user