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clk: rockchip: fix incorrect rk3228 clock registers

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Due to copy and paste carelessly, RK3288_CLKxxx references are incorrect,
we need to fix them.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Xing Zheng 2016-06-21 12:53:27 +08:00 committed by Heiko Stuebner
parent 26e0ee1c62
commit 67de7901c4
1 changed files with 9 additions and 9 deletions
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18
drivers/clk/rockchip/clk-rk3228.c
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@ -335,7 +335,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(2), 6, GFLAGS), RK2928_CLKGATE_CON(2), 6, GFLAGS),
GATE(0, "sclk_hsadc", "ext_hsadc", 0, GATE(0, "sclk_hsadc", "ext_hsadc", 0,
RK3288_CLKGATE_CON(10), 12, GFLAGS), RK2928_CLKGATE_CON(10), 12, GFLAGS),
COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS, RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
@ -380,8 +380,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS, RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 3, GFLAGS), RK2928_CLKGATE_CON(0), 3, GFLAGS),
COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(8), 0, RK2928_CLKSEL_CON(8), 0,
RK3288_CLKGATE_CON(0), 4, GFLAGS), RK2928_CLKGATE_CON(0), 4, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0, COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0,
RK2928_CLKSEL_CON(9), 8, 2, MFLAGS, RK2928_CLKSEL_CON(9), 8, 2, MFLAGS,
RK2928_CLKGATE_CON(0), 5, GFLAGS), RK2928_CLKGATE_CON(0), 5, GFLAGS),
@ -390,8 +390,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS, RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 10, GFLAGS), RK2928_CLKGATE_CON(0), 10, GFLAGS),
COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(7), 0, RK2928_CLKSEL_CON(7), 0,
RK3288_CLKGATE_CON(0), 11, GFLAGS), RK2928_CLKGATE_CON(0), 11, GFLAGS),
MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0, MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0,
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0, GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0,
@ -404,8 +404,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS, RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 7, GFLAGS), RK2928_CLKGATE_CON(0), 7, GFLAGS),
COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(30), 0, RK2928_CLKSEL_CON(30), 0,
RK3288_CLKGATE_CON(0), 8, GFLAGS), RK2928_CLKGATE_CON(0), 8, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0, COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0,
RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, RK2928_CLKSEL_CON(16), 8, 2, MFLAGS,
RK2928_CLKGATE_CON(0), 9, GFLAGS), RK2928_CLKGATE_CON(0), 9, GFLAGS),
@ -414,8 +414,8 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS, RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(2), 10, GFLAGS), RK2928_CLKGATE_CON(2), 10, GFLAGS),
COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
RK3288_CLKSEL_CON(20), 0, RK2928_CLKSEL_CON(20), 0,
RK3288_CLKGATE_CON(2), 12, GFLAGS), RK2928_CLKGATE_CON(2), 12, GFLAGS),
MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0, MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
RK2928_CLKSEL_CON(6), 8, 2, MFLAGS), RK2928_CLKSEL_CON(6), 8, 2, MFLAGS),