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drm/i915: enable cacheable objects on Ivybridge

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IVB supports these bits as well.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Keith Packard <keithp@keithp.com>
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Jesse Barnes 2011-11-03 14:15:13 -07:00 committed by Keith Packard
parent 4b9de737fa
commit 680da876f4
1 changed files with 1 additions and 1 deletions
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drivers/gpu/drm/i915/i915_gem.c
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@ -3613,7 +3613,7 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
obj->base.write_domain = I915_GEM_DOMAIN_CPU;
obj->base.read_domains = I915_GEM_DOMAIN_CPU;
if (IS_GEN6(dev)) {
if (IS_GEN6(dev) || IS_GEN7(dev)) {
/* On Gen6, we can have the GPU use the LLC (the CPU
* cache) for about a 10% performance improvement
* compared to uncached. Graphics requests other than