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[PATCH] ARM: bitops

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Convert ARM bitop assembly to a macro.  All bitops follow the same
format, so it's silly duplicating the code when only one or two
instructions are different.

Signed-off-by: Russell King <rmk@arm.linux.org.uk>
This commit is contained in:
Russell King 2005-04-17 15:51:02 +01:00
parent 652a12ef98
commit 684f970e2f
6 changed files with 12 additions and 68 deletions
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11
arch/arm/lib/changebit.S
View File

@ -9,6 +9,7 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include "bitops.h"
.text
/* Purpose : Function to change a bit
@ -17,12 +18,4 @@
ENTRY(_change_bit_be)
eor r0, r0, #0x18 @ big endian byte ordering
ENTRY(_change_bit_le)
and r2, r0, #7
mov r3, #1
mov r3, r3, lsl r2
save_and_disable_irqs ip, r2
ldrb r2, [r1, r0, lsr #3]
eor r2, r2, r3
strb r2, [r1, r0, lsr #3]
restore_irqs ip
RETINSTR(mov,pc,lr)
bitop eor

13
arch/arm/lib/clearbit.S
View File

@ -9,6 +9,7 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include "bitops.h"
.text
/*
@ -18,14 +19,4 @@
ENTRY(_clear_bit_be)
eor r0, r0, #0x18 @ big endian byte ordering
ENTRY(_clear_bit_le)
and r2, r0, #7
mov r3, #1
mov r3, r3, lsl r2
save_and_disable_irqs ip, r2
ldrb r2, [r1, r0, lsr #3]
bic r2, r2, r3
strb r2, [r1, r0, lsr #3]
restore_irqs ip
RETINSTR(mov,pc,lr)
bitop bic

11
arch/arm/lib/setbit.S
View File

@ -9,6 +9,7 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include "bitops.h"
.text
/*
@ -18,12 +19,4 @@
ENTRY(_set_bit_be)
eor r0, r0, #0x18 @ big endian byte ordering
ENTRY(_set_bit_le)
and r2, r0, #7
mov r3, #1
mov r3, r3, lsl r2
save_and_disable_irqs ip, r2
ldrb r2, [r1, r0, lsr #3]
orr r2, r2, r3
strb r2, [r1, r0, lsr #3]
restore_irqs ip
RETINSTR(mov,pc,lr)
bitop orr

15
arch/arm/lib/testchangebit.S
View File

@ -9,21 +9,10 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include "bitops.h"
.text
ENTRY(_test_and_change_bit_be)
eor r0, r0, #0x18 @ big endian byte ordering
ENTRY(_test_and_change_bit_le)
add r1, r1, r0, lsr #3
and r3, r0, #7
mov r0, #1
save_and_disable_irqs ip, r2
ldrb r2, [r1]
tst r2, r0, lsl r3
eor r2, r2, r0, lsl r3
strb r2, [r1]
restore_irqs ip
moveq r0, #0
RETINSTR(mov,pc,lr)
testop eor, strb

15
arch/arm/lib/testclearbit.S
View File

@ -9,21 +9,10 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include "bitops.h"
.text
ENTRY(_test_and_clear_bit_be)
eor r0, r0, #0x18 @ big endian byte ordering
ENTRY(_test_and_clear_bit_le)
add r1, r1, r0, lsr #3 @ Get byte offset
and r3, r0, #7 @ Get bit offset
mov r0, #1
save_and_disable_irqs ip, r2
ldrb r2, [r1]
tst r2, r0, lsl r3
bic r2, r2, r0, lsl r3
strb r2, [r1]
restore_irqs ip
moveq r0, #0
RETINSTR(mov,pc,lr)
testop bicne, strneb

15
arch/arm/lib/testsetbit.S
View File

@ -9,21 +9,10 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include "bitops.h"
.text
ENTRY(_test_and_set_bit_be)
eor r0, r0, #0x18 @ big endian byte ordering
ENTRY(_test_and_set_bit_le)
add r1, r1, r0, lsr #3 @ Get byte offset
and r3, r0, #7 @ Get bit offset
mov r0, #1
save_and_disable_irqs ip, r2
ldrb r2, [r1]
tst r2, r0, lsl r3
orr r2, r2, r0, lsl r3
strb r2, [r1]
restore_irqs ip
moveq r0, #0
RETINSTR(mov,pc,lr)
testop orreq, streqb