forked from luck/tmp_suning_uos_patched
serial: mvebu-uart: add function to change baudrate
Until now, the first UART port baudrate was set by the bootloader. Add a function allowing to change the baudrate. Changes may be done from userspace but also at probe time by the kernel. Use the simplest method: baudrate divisor. Works for all UART ports until 230400 baud. To achieve higher baudrates, software should implement the fractional divisor feature that allows more accuracy for higher rates. Signed-off-by: Allen Yan <yanwei@marvell.com> [<miquel.raynal@free-electrons.com>: changed termios handling] Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -72,6 +72,7 @@
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| STAT_PAR_ERR | STAT_OVR_ERR)
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#define UART_BRDV 0x10
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#define BRDV_BAUD_MASK 0x3FF
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#define MVEBU_NR_UARTS 1
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@ -344,6 +345,31 @@ static void mvebu_uart_shutdown(struct uart_port *port)
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free_irq(port->irq, port);
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}
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static int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud)
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{
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struct mvebu_uart *mvuart = to_mvuart(port);
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unsigned int baud_rate_div;
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u32 brdv;
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if (IS_ERR(mvuart->clk))
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return -PTR_ERR(mvuart->clk);
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/*
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* The UART clock is divided by the value of the divisor to generate
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* UCLK_OUT clock, which is 16 times faster than the baudrate.
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* This prescaler can achieve all standard baudrates until 230400.
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* Higher baudrates could be achieved for the extended UART by using the
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* programmable oversampling stack (also called fractional divisor).
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*/
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baud_rate_div = DIV_ROUND_UP(port->uartclk, baud * 16);
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brdv = readl(port->membase + UART_BRDV);
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brdv &= ~BRDV_BAUD_MASK;
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brdv |= baud_rate_div;
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writel(brdv, port->membase + UART_BRDV);
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return 0;
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}
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static void mvebu_uart_set_termios(struct uart_port *port,
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struct ktermios *termios,
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struct ktermios *old)
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@ -367,11 +393,30 @@ static void mvebu_uart_set_termios(struct uart_port *port,
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if ((termios->c_cflag & CREAD) == 0)
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port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR;
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if (old)
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tty_termios_copy_hw(termios, old);
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/*
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* Maximum achievable frequency with simple baudrate divisor is 230400.
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* Since the error per bit frame would be of more than 15%, achieving
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* higher frequencies would require to implement the fractional divisor
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* feature.
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*/
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baud = uart_get_baud_rate(port, termios, old, 0, 230400);
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if (mvebu_uart_baud_rate_set(port, baud)) {
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/* No clock available, baudrate cannot be changed */
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if (old)
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baud = uart_get_baud_rate(port, old, NULL, 0, 230400);
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} else {
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tty_termios_encode_baud_rate(termios, baud, baud);
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uart_update_timeout(port, termios->c_cflag, baud);
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}
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baud = uart_get_baud_rate(port, termios, old, 0, 460800);
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uart_update_timeout(port, termios->c_cflag, baud);
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/* Only the following flag changes are supported */
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if (old) {
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termios->c_iflag &= INPCK | IGNPAR;
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termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR);
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termios->c_cflag &= CREAD | CBAUD;
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termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD);
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termios->c_lflag = old->c_lflag;
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}
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spin_unlock_irqrestore(&port->lock, flags);
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}
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@ -654,12 +699,28 @@ static int mvebu_uart_probe(struct platform_device *pdev)
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if (!mvuart)
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return -ENOMEM;
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/* Get controller data depending on the compatible string */
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mvuart->data = (struct mvebu_uart_driver_data *)match->data;
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mvuart->port = port;
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port->private_data = mvuart;
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platform_set_drvdata(pdev, mvuart);
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/* Get fixed clock frequency */
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mvuart->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(mvuart->clk)) {
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if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER)
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return PTR_ERR(mvuart->clk);
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if (IS_EXTENDED(port)) {
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dev_err(&pdev->dev, "unable to get UART clock\n");
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return PTR_ERR(mvuart->clk);
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}
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} else {
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if (!clk_prepare_enable(mvuart->clk))
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port->uartclk = clk_get_rate(mvuart->clk);
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}
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/* UART Soft Reset*/
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writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
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udelay(1);
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