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clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates

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Default clock configuration applied by the bootloader for TM2 and TM2e
boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure
such configuration for those boards with 'assigned-clock-*' properties,
parameters for those two additional rates are needed.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Marek Szyprowski 2017-01-26 13:37:53 +01:00 committed by Sylwester Nawrocki
parent 5ccb58968b
commit 698e0d1d22
1 changed files with 2 additions and 0 deletions
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drivers/clk/samsung/clk-exynos5433.c
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@ -739,7 +739,9 @@ static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst =
PLL_35XX_RATE(350000000U, 350, 6, 2), PLL_35XX_RATE(350000000U, 350, 6, 2),
PLL_35XX_RATE(333000000U, 222, 4, 2), PLL_35XX_RATE(333000000U, 222, 4, 2),
PLL_35XX_RATE(300000000U, 500, 5, 3), PLL_35XX_RATE(300000000U, 500, 5, 3),
PLL_35XX_RATE(278000000U, 556, 6, 3),
PLL_35XX_RATE(266000000U, 532, 6, 3), PLL_35XX_RATE(266000000U, 532, 6, 3),
PLL_35XX_RATE(250000000U, 500, 6, 3),
PLL_35XX_RATE(200000000U, 400, 6, 3), PLL_35XX_RATE(200000000U, 400, 6, 3),
PLL_35XX_RATE(166000000U, 332, 6, 3), PLL_35XX_RATE(166000000U, 332, 6, 3),
PLL_35XX_RATE(160000000U, 320, 6, 3), PLL_35XX_RATE(160000000U, 320, 6, 3),