forked from luck/tmp_suning_uos_patched
KVM/arm64 fixes for 5.10, take #1
- Force PTE mapping on device pages provided via VFIO - Fix detection of cacheable mapping at S2 - Fallback to PMD/PTE mappings for composite huge pages - Fix accounting of Stage-2 PGD allocation - Fix AArch32 handling of some of the debug registers - Simplify host HYP entry - Fix stray pointer conversion on nVHE TLB invalidation - Fix initialization of the nVHE code - Simplify handling of capabilities exposed to HYP - Nuke VCPUs caught using a forbidden AArch32 EL0 -----BEGIN PGP SIGNATURE----- iQJDBAABCgAtFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAl+cO3oPHG1hekBrZXJu ZWwub3JnAAoJECPQ0LrRPXpDJdoP/jiKYR8iVkq/RmIsQl383KwQiJGTMi0iL2Zw /tHnf8bKowAPyG8bqyXMJqlWOb7tcp6U3m+WhENAZHWH02r2M921q0DGVW5p48ou Ek4zJnFF1iL5ryOBgROKK1nymUZOi3W1a1SsD6ZPImQsKsjNGbqKgWsGs8i9ft0P vkNZwlqebzJp+OR3agJemc8dkXcGlcRHk7fffdMcU8jsF5RJ9zC0XU0+scKryxhV o8PzKSlwCeisyL+Vz+s7POzoD3Rt+P+qjblz5NWqy/NHuLh+V9hzUSDOjWbZb70f Er29vGv7Yjb4nKK2KUzNqirSfXsRylfsjGr+YibP6uKEUMuUm/V41DqzT7nMalIm cOBGtPk6W9wOL8JNDmlyVGCfATI+5RrErQ8nFClrPu3qw4Hv4pb1Ad5OgAhNE0u1 PfUyBBtQKNAjTdVCRfSuFL4d2yegy1rrpCmYWrvdQjLlXemwgYgKnSQN98cZHgjA foCAP5gJpAWGualyhKJx2CkY/5deeWKS39ISiNgHo5eRvKsGEnMN7j9UX77VbhRr PkwCmeUJ3kjzaAfmtcBN/iLjwQbWypidjX2Vbfl5WoVdLuiYXFZIvsdaqRHGl56F 5zhYxM8DKODNEJKMl7a89oEFGKy8x1PQ0kqer9a6GBWkNDrQMOSL4+FkxCyM2m9g RoHtmdy0 =gVaX -----END PGP SIGNATURE----- Merge tag 'kvmarm-fixes-5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD KVM/arm64 fixes for 5.10, take #1 - Force PTE mapping on device pages provided via VFIO - Fix detection of cacheable mapping at S2 - Fallback to PMD/PTE mappings for composite huge pages - Fix accounting of Stage-2 PGD allocation - Fix AArch32 handling of some of the debug registers - Simplify host HYP entry - Fix stray pointer conversion on nVHE TLB invalidation - Fix initialization of the nVHE code - Simplify handling of capabilities exposed to HYP - Nuke VCPUs caught using a forbidden AArch32 EL0
This commit is contained in:
Paolo Bonzini
commit
699116c45e
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@ -375,6 +375,23 @@ cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry,
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return false;
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}
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static __always_inline bool is_vhe_hyp_code(void)
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{
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/* Only defined for code run in VHE hyp context */
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return __is_defined(__KVM_VHE_HYPERVISOR__);
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}
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static __always_inline bool is_nvhe_hyp_code(void)
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{
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/* Only defined for code run in NVHE hyp context */
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return __is_defined(__KVM_NVHE_HYPERVISOR__);
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}
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static __always_inline bool is_hyp_code(void)
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{
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return is_vhe_hyp_code() || is_nvhe_hyp_code();
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}
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extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
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extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
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extern struct static_key_false arm64_const_caps_ready;
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@ -427,22 +444,6 @@ static __always_inline bool __cpus_have_const_cap(int num)
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return static_branch_unlikely(&cpu_hwcap_keys[num]);
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}
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/*
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* Test for a capability, possibly with a runtime check.
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*
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* Before capabilities are finalized, this behaves as cpus_have_cap().
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* After capabilities are finalized, this is patched to avoid a runtime check.
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*
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* @num must be a compile-time constant.
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*/
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static __always_inline bool cpus_have_const_cap(int num)
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{
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if (system_capabilities_finalized())
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return __cpus_have_const_cap(num);
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else
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return cpus_have_cap(num);
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}
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/*
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* Test for a capability without a runtime check.
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*
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@ -459,6 +460,27 @@ static __always_inline bool cpus_have_final_cap(int num)
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BUG();
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}
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/*
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* Test for a capability, possibly with a runtime check for non-hyp code.
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*
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* For hyp code, this behaves the same as cpus_have_final_cap().
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*
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* For non-hyp code:
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* Before capabilities are finalized, this behaves as cpus_have_cap().
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* After capabilities are finalized, this is patched to avoid a runtime check.
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*
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* @num must be a compile-time constant.
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*/
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static __always_inline bool cpus_have_const_cap(int num)
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{
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if (is_hyp_code())
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return cpus_have_final_cap(num);
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else if (system_capabilities_finalized())
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return __cpus_have_const_cap(num);
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else
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return cpus_have_cap(num);
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}
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static inline void cpus_set_cap(unsigned int num)
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{
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if (num >= ARM64_NCAPS) {
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@ -239,6 +239,7 @@ enum vcpu_sysreg {
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#define cp14_DBGWCR0 (DBGWCR0_EL1 * 2)
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#define cp14_DBGWVR0 (DBGWVR0_EL1 * 2)
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#define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
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#define cp14_DBGVCR (DBGVCR32_EL2 * 2)
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#define NR_COPRO_REGS (NR_SYS_REGS * 2)
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@ -86,13 +86,12 @@ static inline bool is_kernel_in_hyp_mode(void)
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static __always_inline bool has_vhe(void)
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{
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/*
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* The following macros are defined for code specic to VHE/nVHE.
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* If has_vhe() is inlined into those compilation units, it can
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* be determined statically. Otherwise fall back to caps.
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* Code only run in VHE/NVHE hyp context can assume VHE is present or
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* absent. Otherwise fall back to caps.
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*/
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if (__is_defined(__KVM_VHE_HYPERVISOR__))
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if (is_vhe_hyp_code())
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return true;
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else if (__is_defined(__KVM_NVHE_HYPERVISOR__))
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else if (is_nvhe_hyp_code())
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return false;
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else
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return cpus_have_final_cap(ARM64_HAS_VIRT_HOST_EXTN);
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@ -87,7 +87,6 @@ KVM_NVHE_ALIAS(__icache_flags);
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/* Kernel symbols needed for cpus_have_final/const_caps checks. */
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KVM_NVHE_ALIAS(arm64_const_caps_ready);
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KVM_NVHE_ALIAS(cpu_hwcap_keys);
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KVM_NVHE_ALIAS(cpu_hwcaps);
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/* Static keys which are set if a vGIC trap should be handled in hyp. */
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KVM_NVHE_ALIAS(vgic_v2_cpuif_trap);
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@ -808,6 +808,25 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
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preempt_enable();
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/*
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* The ARMv8 architecture doesn't give the hypervisor
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* a mechanism to prevent a guest from dropping to AArch32 EL0
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* if implemented by the CPU. If we spot the guest in such
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* state and that we decided it wasn't supposed to do so (like
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* with the asymmetric AArch32 case), return to userspace with
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* a fatal error.
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*/
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if (!system_supports_32bit_el0() && vcpu_mode_is_32bit(vcpu)) {
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/*
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* As we have caught the guest red-handed, decide that
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* it isn't fit for purpose anymore by making the vcpu
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* invalid. The VMM can try and fix it by issuing a
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* KVM_ARM_VCPU_INIT if it really wants to.
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*/
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vcpu->arch.target = -1;
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ret = ARM_EXCEPTION_IL;
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}
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ret = handle_exit(vcpu, ret);
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}
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@ -17,8 +17,6 @@ SYM_FUNC_START(__host_exit)
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get_host_ctxt x0, x1
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ALTERNATIVE(nop, SET_PSTATE_PAN(1), ARM64_HAS_PAN, CONFIG_ARM64_PAN)
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/* Store the host regs x2 and x3 */
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stp x2, x3, [x0, #CPU_XREG_OFFSET(2)]
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@ -57,16 +57,25 @@ __do_hyp_init:
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cmp x0, #HVC_STUB_HCALL_NR
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b.lo __kvm_handle_stub_hvc
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/* Set tpidr_el2 for use by HYP to free a register */
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msr tpidr_el2, x2
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// We only actively check bits [24:31], and everything
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// else has to be zero, which we check at build time.
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#if (KVM_HOST_SMCCC_FUNC(__kvm_hyp_init) & 0xFFFFFFFF00FFFFFF)
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#error Unexpected __KVM_HOST_SMCCC_FUNC___kvm_hyp_init value
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#endif
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mov x2, #KVM_HOST_SMCCC_FUNC(__kvm_hyp_init)
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cmp x0, x2
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b.eq 1f
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ror x0, x0, #24
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eor x0, x0, #((KVM_HOST_SMCCC_FUNC(__kvm_hyp_init) >> 24) & 0xF)
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ror x0, x0, #4
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eor x0, x0, #((KVM_HOST_SMCCC_FUNC(__kvm_hyp_init) >> 28) & 0xF)
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cbz x0, 1f
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mov x0, #SMCCC_RET_NOT_SUPPORTED
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eret
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1: phys_to_ttbr x0, x1
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1:
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/* Set tpidr_el2 for use by HYP to free a register */
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msr tpidr_el2, x2
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phys_to_ttbr x0, x1
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alternative_if ARM64_HAS_CNP
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orr x0, x0, #TTBR_CNP_BIT
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alternative_else_nop_endif
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@ -128,7 +128,6 @@ void __kvm_tlb_flush_local_vmid(struct kvm_s2_mmu *mmu)
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struct tlb_inv_context cxt;
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/* Switch to requested VMID */
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mmu = kern_hyp_va(mmu);
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__tlb_switch_to_guest(mmu, &cxt);
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__tlbi(vmalle1);
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@ -635,7 +635,7 @@ static void stage2_flush_dcache(void *addr, u64 size)
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static bool stage2_pte_cacheable(kvm_pte_t pte)
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{
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u64 memattr = FIELD_GET(KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR, pte);
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u64 memattr = pte & KVM_PTE_LEAF_ATTR_LO_S2_MEMATTR;
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return memattr == PAGE_S2_MEMATTR(NORMAL);
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}
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@ -846,7 +846,7 @@ int kvm_pgtable_stage2_init(struct kvm_pgtable *pgt, struct kvm *kvm)
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u32 start_level = VTCR_EL2_TGRAN_SL0_BASE - sl0;
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pgd_sz = kvm_pgd_pages(ia_bits, start_level) * PAGE_SIZE;
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pgt->pgd = alloc_pages_exact(pgd_sz, GFP_KERNEL | __GFP_ZERO);
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pgt->pgd = alloc_pages_exact(pgd_sz, GFP_KERNEL_ACCOUNT | __GFP_ZERO);
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if (!pgt->pgd)
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return -ENOMEM;
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@ -787,14 +787,26 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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vma_shift = PAGE_SHIFT;
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}
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if (vma_shift == PUD_SHIFT &&
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!fault_supports_stage2_huge_mapping(memslot, hva, PUD_SIZE))
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vma_shift = PMD_SHIFT;
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if (vma_shift == PMD_SHIFT &&
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!fault_supports_stage2_huge_mapping(memslot, hva, PMD_SIZE)) {
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force_pte = true;
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switch (vma_shift) {
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case PUD_SHIFT:
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if (fault_supports_stage2_huge_mapping(memslot, hva, PUD_SIZE))
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break;
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fallthrough;
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case CONT_PMD_SHIFT:
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vma_shift = PMD_SHIFT;
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fallthrough;
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case PMD_SHIFT:
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if (fault_supports_stage2_huge_mapping(memslot, hva, PMD_SIZE))
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break;
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fallthrough;
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case CONT_PTE_SHIFT:
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vma_shift = PAGE_SHIFT;
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force_pte = true;
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fallthrough;
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case PAGE_SHIFT:
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break;
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default:
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WARN_ONCE(1, "Unknown vma_shift %d", vma_shift);
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}
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vma_pagesize = 1UL << vma_shift;
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@ -839,6 +851,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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if (kvm_is_device_pfn(pfn)) {
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device = true;
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force_pte = true;
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} else if (logging_active && !write_fault) {
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/*
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* Only actually map the page as writable if this was a write
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@ -1897,9 +1897,9 @@ static const struct sys_reg_desc cp14_regs[] = {
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{ Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
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DBG_BCR_BVR_WCR_WVR(1),
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/* DBGDCCINT */
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{ Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
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{ Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32, NULL, cp14_DBGDCCINT },
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/* DBGDSCRext */
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{ Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
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{ Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32, NULL, cp14_DBGDSCRext },
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DBG_BCR_BVR_WCR_WVR(2),
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/* DBGDTR[RT]Xint */
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{ Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
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@ -1914,7 +1914,7 @@ static const struct sys_reg_desc cp14_regs[] = {
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{ Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
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DBG_BCR_BVR_WCR_WVR(6),
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/* DBGVCR */
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{ Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
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{ Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32, NULL, cp14_DBGVCR },
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DBG_BCR_BVR_WCR_WVR(7),
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DBG_BCR_BVR_WCR_WVR(8),
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DBG_BCR_BVR_WCR_WVR(9),
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