forked from luck/tmp_suning_uos_patched
arm/imx6q: add smp and cpu hotplug support
It adds smp and cpu hotplug support for imx6q. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
parent
9fbbe6890c
commit
69c31b7a6e
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@ -611,6 +611,7 @@ config SOC_IMX6Q
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select ARM_GIC
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select CACHE_L2X0
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select CPU_V7
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select HAVE_ARM_SCU
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select HAVE_IMX_GPC
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select HAVE_IMX_MMDC
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select HAVE_IMX_SRC
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@ -65,4 +65,9 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
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obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
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obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
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obj-$(CONFIG_HAVE_IMX_SRC) += src.o
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obj-$(CONFIG_CPU_V7) += head-v7.o
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AFLAGS_head-v7.o :=-Wa,-march=armv7-a
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obj-$(CONFIG_SMP) += platsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
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obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o
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71
arch/arm/mach-imx/head-v7.S
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71
arch/arm/mach-imx/head-v7.S
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@ -0,0 +1,71 @@
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/hardware/cache-l2x0.h>
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.section ".text.head", "ax"
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__CPUINIT
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/*
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* The secondary kernel init calls v7_flush_dcache_all before it enables
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* the L1; however, the L1 comes out of reset in an undefined state, so
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* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
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* of cache lines with uninitialized data and uninitialized tags to get
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* written out to memory, which does really unpleasant things to the main
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* processor. We fix this by performing an invalidate, rather than a
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* clean + invalidate, before jumping into the kernel.
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*
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* This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
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* to be called for both secondary cores startup and primary core resume
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* procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S.
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*/
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ENTRY(v7_invalidate_l1)
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mov r0, #0
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mcr p15, 2, r0, c0, c0, 0
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mrc p15, 1, r0, c0, c0, 0
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ldr r1, =0x7fff
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and r2, r1, r0, lsr #13
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ldr r1, =0x3ff
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and r3, r1, r0, lsr #3 @ NumWays - 1
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add r2, r2, #1 @ NumSets
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and r0, r0, #0x7
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add r0, r0, #4 @ SetShift
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clz r1, r3 @ WayShift
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add r4, r3, #1 @ NumWays
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1: sub r2, r2, #1 @ NumSets--
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mov r3, r4 @ Temp = NumWays
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2: subs r3, r3, #1 @ Temp--
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mov r5, r3, lsl r1
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mov r6, r2, lsl r0
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orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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mcr p15, 0, r5, c7, c6, 2
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bgt 2b
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cmp r2, #0
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bgt 1b
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dsb
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isb
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mov pc, lr
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ENDPROC(v7_invalidate_l1)
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#ifdef CONFIG_SMP
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ENTRY(v7_secondary_startup)
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bl v7_invalidate_l1
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b secondary_startup
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ENDPROC(v7_secondary_startup)
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#endif
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44
arch/arm/mach-imx/hotplug.c
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44
arch/arm/mach-imx/hotplug.c
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@ -0,0 +1,44 @@
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/errno.h>
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#include <asm/cacheflush.h>
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#include <mach/common.h>
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int platform_cpu_kill(unsigned int cpu)
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{
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return 1;
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}
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/*
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* platform-specific code to shutdown a CPU
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*
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* Called with IRQs disabled
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*/
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void platform_cpu_die(unsigned int cpu)
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{
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flush_cache_all();
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imx_enable_cpu(cpu, false);
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cpu_do_idle();
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/* We should never return from idle */
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panic("cpu %d unexpectedly exit from shutdown\n", cpu);
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}
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int platform_cpu_disable(unsigned int cpu)
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{
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/*
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* we don't allow CPU 0 to be shutdown (it is still too special
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* e.g. clock tick interrupts)
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*/
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return cpu == 0 ? -EPERM : 0;
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}
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35
arch/arm/mach-imx/localtimer.c
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35
arch/arm/mach-imx/localtimer.c
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@ -0,0 +1,35 @@
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/clockchips.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/smp_twd.h>
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/*
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* Setup the local clock events for a CPU.
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*/
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int __cpuinit local_timer_setup(struct clock_event_device *evt)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "arm,smp-twd");
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if (!twd_base) {
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twd_base = of_iomap(np, 0);
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WARN_ON(!twd_base);
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}
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evt->irq = irq_of_parse_and_map(np, 0);
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twd_timer_setup(evt);
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return 0;
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}
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85
arch/arm/mach-imx/platsmp.c
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85
arch/arm/mach-imx/platsmp.c
Normal file
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@ -0,0 +1,85 @@
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/page.h>
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#include <asm/smp_scu.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach/map.h>
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#include <mach/common.h>
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#include <mach/hardware.h>
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static void __iomem *scu_base;
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static struct map_desc scu_io_desc __initdata = {
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/* .virtual and .pfn are run-time assigned */
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.length = SZ_4K,
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.type = MT_DEVICE,
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};
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void __init imx_scu_map_io(void)
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{
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unsigned long base;
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/* Get SCU base */
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
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scu_io_desc.virtual = IMX_IO_P2V(base);
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scu_io_desc.pfn = __phys_to_pfn(base);
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iotable_init(&scu_io_desc, 1);
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scu_base = IMX_IO_ADDRESS(base);
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}
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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imx_set_cpu_jump(cpu, v7_secondary_startup);
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imx_enable_cpu(cpu, true);
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return 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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void __init smp_init_cpus(void)
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{
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int i, ncores;
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ncores = scu_get_core_count(scu_base);
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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void imx_smp_prepare(void)
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{
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scu_enable(scu_base);
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}
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void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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{
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imx_smp_prepare();
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}
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@ -99,4 +99,9 @@ void gic_handle_irq(struct pt_regs *);
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#define imx53_handle_irq tzic_handle_irq
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#define imx6q_handle_irq gic_handle_irq
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extern void imx_enable_cpu(int cpu, bool enable);
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extern void imx_set_cpu_jump(int cpu, void *jump_addr);
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#ifdef CONFIG_SMP
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extern void v7_secondary_startup(void);
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#endif
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#endif
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