forked from luck/tmp_suning_uos_patched
MIPS: Introduce accessors for MSA vector registers
Introduce accessor functions allowing the kernel to access arbitrary vector registers using an arbitrary data format. The accessors are implemented in assembly, using macros to avoid massive duplication, in order to make use of the existing support for MSA with & without toolchain support. The accessors will be used in a later patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Manuel Lauss <manuel.lauss@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10572/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton
Ralf Baechle
parent
6701ca2df4
commit
6b35e11442
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@ -232,6 +232,30 @@
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.set pop
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.endm
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.macro ld_b wd, off, base
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.set push
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.set mips32r2
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.set msa
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ld.b $w\wd, \off(\base)
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.set pop
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.endm
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.macro ld_h wd, off, base
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.set push
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.set mips32r2
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.set msa
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ld.h $w\wd, \off(\base)
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.set pop
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.endm
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.macro ld_w wd, off, base
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.set push
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.set mips32r2
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.set msa
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ld.w $w\wd, \off(\base)
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.set pop
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.endm
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.macro ld_d wd, off, base
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.set push
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.set mips32r2
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@ -241,6 +265,30 @@
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.set pop
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.endm
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.macro st_b wd, off, base
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.set push
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.set mips32r2
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.set msa
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st.b $w\wd, \off(\base)
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.set pop
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.endm
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.macro st_h wd, off, base
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.set push
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.set mips32r2
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.set msa
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st.h $w\wd, \off(\base)
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.set pop
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.endm
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.macro st_w wd, off, base
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.set push
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.set mips32r2
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.set msa
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st.w $w\wd, \off(\base)
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.set pop
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.endm
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.macro st_d wd, off, base
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.set push
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.set mips32r2
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@ -290,7 +338,13 @@
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#ifdef CONFIG_CPU_MICROMIPS
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#define CFC_MSA_INSN 0x587e0056
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#define CTC_MSA_INSN 0x583e0816
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#define LDB_MSA_INSN 0x58000807
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#define LDH_MSA_INSN 0x58000817
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#define LDW_MSA_INSN 0x58000827
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#define LDD_MSA_INSN 0x58000837
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#define STB_MSA_INSN 0x5800080f
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#define STH_MSA_INSN 0x5800081f
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#define STW_MSA_INSN 0x5800082f
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#define STD_MSA_INSN 0x5800083f
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#define COPY_UW_MSA_INSN 0x58f00056
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#define COPY_UD_MSA_INSN 0x58f80056
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@ -299,7 +353,13 @@
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#else
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#define CFC_MSA_INSN 0x787e0059
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#define CTC_MSA_INSN 0x783e0819
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#define LDB_MSA_INSN 0x78000820
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#define LDH_MSA_INSN 0x78000821
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#define LDW_MSA_INSN 0x78000822
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#define LDD_MSA_INSN 0x78000823
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#define STB_MSA_INSN 0x78000824
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#define STH_MSA_INSN 0x78000825
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#define STW_MSA_INSN 0x78000826
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#define STD_MSA_INSN 0x78000827
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#define COPY_UW_MSA_INSN 0x78f00059
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#define COPY_UD_MSA_INSN 0x78f80059
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@ -329,6 +389,33 @@
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.set pop
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.endm
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.macro ld_b wd, off, base
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.set push
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.set noat
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SET_HARDFLOAT
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addu $1, \base, \off
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.word LDB_MSA_INSN | (\wd << 6)
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.set pop
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.endm
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.macro ld_h wd, off, base
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.set push
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.set noat
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SET_HARDFLOAT
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addu $1, \base, \off
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.word LDH_MSA_INSN | (\wd << 6)
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.set pop
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.endm
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.macro ld_w wd, off, base
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.set push
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.set noat
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SET_HARDFLOAT
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addu $1, \base, \off
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.word LDW_MSA_INSN | (\wd << 6)
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.set pop
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.endm
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.macro ld_d wd, off, base
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.set push
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.set noat
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@ -338,6 +425,33 @@
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.set pop
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.endm
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.macro st_b wd, off, base
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.set push
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.set noat
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SET_HARDFLOAT
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addu $1, \base, \off
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.word STB_MSA_INSN | (\wd << 6)
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.set pop
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.endm
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.macro st_h wd, off, base
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.set push
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.set noat
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SET_HARDFLOAT
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addu $1, \base, \off
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.word STH_MSA_INSN | (\wd << 6)
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.set pop
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.endm
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.macro st_w wd, off, base
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.set push
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.set noat
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SET_HARDFLOAT
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addu $1, \base, \off
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.word STW_MSA_INSN | (\wd << 6)
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.set pop
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.endm
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.macro st_d wd, off, base
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.set push
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.set noat
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@ -14,10 +14,90 @@
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#ifndef __ASSEMBLY__
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#include <asm/inst.h>
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extern void _save_msa(struct task_struct *);
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extern void _restore_msa(struct task_struct *);
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extern void _init_msa_upper(void);
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extern void read_msa_wr_b(unsigned idx, union fpureg *to);
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extern void read_msa_wr_h(unsigned idx, union fpureg *to);
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extern void read_msa_wr_w(unsigned idx, union fpureg *to);
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extern void read_msa_wr_d(unsigned idx, union fpureg *to);
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/**
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* read_msa_wr() - Read a single MSA vector register
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* @idx: The index of the vector register to read
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* @to: The FPU register union to store the registers value in
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* @fmt: The format of the data in the vector register
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*
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* Read the value of MSA vector register idx into the FPU register
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* union to, using the format fmt.
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*/
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static inline void read_msa_wr(unsigned idx, union fpureg *to,
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enum msa_2b_fmt fmt)
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{
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switch (fmt) {
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case msa_fmt_b:
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read_msa_wr_b(idx, to);
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break;
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case msa_fmt_h:
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read_msa_wr_h(idx, to);
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break;
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case msa_fmt_w:
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read_msa_wr_w(idx, to);
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break;
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case msa_fmt_d:
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read_msa_wr_d(idx, to);
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break;
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default:
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BUG();
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}
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}
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extern void write_msa_wr_b(unsigned idx, union fpureg *from);
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extern void write_msa_wr_h(unsigned idx, union fpureg *from);
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extern void write_msa_wr_w(unsigned idx, union fpureg *from);
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extern void write_msa_wr_d(unsigned idx, union fpureg *from);
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/**
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* write_msa_wr() - Write a single MSA vector register
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* @idx: The index of the vector register to write
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* @from: The FPU register union to take the registers value from
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* @fmt: The format of the data in the vector register
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*
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* Write the value from the FPU register union from into MSA vector
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* register idx, using the format fmt.
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*/
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static inline void write_msa_wr(unsigned idx, union fpureg *from,
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enum msa_2b_fmt fmt)
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{
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switch (fmt) {
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case msa_fmt_b:
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write_msa_wr_b(idx, from);
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break;
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case msa_fmt_h:
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write_msa_wr_h(idx, from);
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break;
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case msa_fmt_w:
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write_msa_wr_w(idx, from);
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break;
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case msa_fmt_d:
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write_msa_wr_d(idx, from);
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break;
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default:
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BUG();
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}
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}
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static inline void enable_msa(void)
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{
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if (cpu_has_msa) {
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@ -13,6 +13,7 @@
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* Copyright (C) 1999, 2001 Silicon Graphics, Inc.
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*/
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/errno.h>
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#include <asm/fpregdef.h>
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#include <asm/mipsregs.h>
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@ -274,6 +275,72 @@ LEAF(_restore_fp_context32)
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END(_restore_fp_context32)
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#endif
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#ifdef CONFIG_CPU_HAS_MSA
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.macro op_one_wr op, idx, base
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.align 4
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\idx: \op \idx, 0, \base
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jr ra
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nop
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.endm
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.macro op_msa_wr name, op
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LEAF(\name)
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.set push
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.set noreorder
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sll t0, a0, 4
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PTR_LA t1, 0f
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PTR_ADDU t0, t0, t1
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jr t0
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nop
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op_one_wr \op, 0, a1
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op_one_wr \op, 1, a1
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op_one_wr \op, 2, a1
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op_one_wr \op, 3, a1
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op_one_wr \op, 4, a1
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op_one_wr \op, 5, a1
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op_one_wr \op, 6, a1
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op_one_wr \op, 7, a1
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op_one_wr \op, 8, a1
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op_one_wr \op, 9, a1
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op_one_wr \op, 10, a1
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op_one_wr \op, 11, a1
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op_one_wr \op, 12, a1
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op_one_wr \op, 13, a1
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op_one_wr \op, 14, a1
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op_one_wr \op, 15, a1
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op_one_wr \op, 16, a1
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op_one_wr \op, 17, a1
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op_one_wr \op, 18, a1
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op_one_wr \op, 19, a1
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op_one_wr \op, 20, a1
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op_one_wr \op, 21, a1
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op_one_wr \op, 22, a1
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op_one_wr \op, 23, a1
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op_one_wr \op, 24, a1
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op_one_wr \op, 25, a1
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op_one_wr \op, 26, a1
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op_one_wr \op, 27, a1
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op_one_wr \op, 28, a1
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op_one_wr \op, 29, a1
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op_one_wr \op, 30, a1
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op_one_wr \op, 31, a1
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.set pop
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END(\name)
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.endm
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op_msa_wr read_msa_wr_b, st_b
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op_msa_wr read_msa_wr_h, st_h
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op_msa_wr read_msa_wr_w, st_w
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op_msa_wr read_msa_wr_d, st_d
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op_msa_wr write_msa_wr_b, ld_b
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op_msa_wr write_msa_wr_h, ld_h
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op_msa_wr write_msa_wr_w, ld_w
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op_msa_wr write_msa_wr_d, ld_d
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#endif /* CONFIG_CPU_HAS_MSA */
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.set reorder
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.type fault@function
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