forked from luck/tmp_suning_uos_patched
KVM/arm fixes for 5.8, take #2
- Make sure a vcpu becoming non-resident doesn't race against the doorbell delivery - Only advertise pvtime if accounting is enabled - Return the correct error code if reset fails with SVE - Make sure that pseudo-NMI functions are annotated as __always_inline -----BEGIN PGP SIGNATURE----- iQJDBAABCgAtFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAl76E48PHG1hekBrZXJu ZWwub3JnAAoJECPQ0LrRPXpDFsAP/1jFBCusd/axezuE/LVhEj72789I7uFlC+/+ sf5ebrw2xTS2/qj+MpU5sDmof9lnRO5z4MTr/VOlEMikSE38JvKPxqNzklnyheso kroX6L+DpjTdBGaur2VU8TLme88pcSrZwRR8trSy5Li3nuc3kT19VhV2tkt0ruyT tzliJxRKLosZkFTx+LeXnm08JUYClvCs7DCH+F2PfvbRJoWQzWlq3gdp0sjBkWX7 OsAOwiShNFBk/AiR40811WgcEOsPrHDePlBfQjh6BmEZvxZF73rtNkA7zKXjchs3 v5Tfl2rlMxXc5EcsylNgjOcXJ/wKYJP89Bq9DLmhPQigckKUWiDmbKhaJ3B0X1FV PuTUl4PTEoiTa+vgiZgsaDa/ivpDX/oQYAVsVs3/lTc2Jm9iCFIn6Ph+G5HVblwt ZsJ9lrAgahByuKXFg5vjiq02gB+4s7HdffNtvMms1Vathdi/kRRAe7nCohcozcw+ xSbyasytL78/zM5Q9zQxMpEnWQoJbIj2cV6+JdBfMQ6XmBveYstpRKfVnfHCmmfL 6cL3rPSTKReLX7mBK+05B1RXcp7l1rF58lB4XsZ55vNj6ttt8dL0HP3LUwBgnSUY 10HaBDRxuG4aKxreIkV2ew0Rwp/potGEM5rwEshmpDrDoNd0lTg5eS7clRFeiaDd CECRXaY6 =ZjTT -----END PGP SIGNATURE----- Merge tag 'kvmarm-fixes-5.8-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-master KVM/arm fixes for 5.8, take #2 - Make sure a vcpu becoming non-resident doesn't race against the doorbell delivery - Only advertise pvtime if accounting is enabled - Return the correct error code if reset fails with SVE - Make sure that pseudo-NMI functions are annotated as __always_inline
This commit is contained in:
commit
6e1d72f1ea
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@ -109,7 +109,7 @@ static inline u32 gic_read_pmr(void)
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return read_sysreg_s(SYS_ICC_PMR_EL1);
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}
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static inline void gic_write_pmr(u32 val)
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static __always_inline void gic_write_pmr(u32 val)
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{
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write_sysreg_s(val, SYS_ICC_PMR_EL1);
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}
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@ -675,7 +675,7 @@ static inline bool system_supports_generic_auth(void)
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cpus_have_const_cap(ARM64_HAS_GENERIC_AUTH);
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}
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static inline bool system_uses_irq_prio_masking(void)
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static __always_inline bool system_uses_irq_prio_masking(void)
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{
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return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
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cpus_have_const_cap(ARM64_HAS_IRQ_PRIO_MASKING);
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@ -3,6 +3,7 @@
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#include <linux/arm-smccc.h>
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#include <linux/kvm_host.h>
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#include <linux/sched/stat.h>
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#include <asm/kvm_mmu.h>
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#include <asm/pvclock-abi.h>
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@ -73,6 +74,11 @@ gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu)
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return base;
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}
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static bool kvm_arm_pvtime_supported(void)
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{
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return !!sched_info_on();
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}
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int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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@ -82,7 +88,8 @@ int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
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int ret = 0;
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int idx;
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if (attr->attr != KVM_ARM_VCPU_PVTIME_IPA)
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if (!kvm_arm_pvtime_supported() ||
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attr->attr != KVM_ARM_VCPU_PVTIME_IPA)
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return -ENXIO;
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if (get_user(ipa, user))
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@ -110,7 +117,8 @@ int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
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u64 __user *user = (u64 __user *)attr->addr;
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u64 ipa;
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if (attr->attr != KVM_ARM_VCPU_PVTIME_IPA)
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if (!kvm_arm_pvtime_supported() ||
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attr->attr != KVM_ARM_VCPU_PVTIME_IPA)
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return -ENXIO;
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ipa = vcpu->arch.steal.base;
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@ -125,7 +133,8 @@ int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
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{
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switch (attr->attr) {
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case KVM_ARM_VCPU_PVTIME_IPA:
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return 0;
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if (kvm_arm_pvtime_supported())
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return 0;
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}
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return -ENXIO;
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}
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@ -245,7 +245,7 @@ static int kvm_vcpu_enable_ptrauth(struct kvm_vcpu *vcpu)
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*/
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int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
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{
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int ret = -EINVAL;
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int ret;
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bool loaded;
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u32 pstate;
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@ -269,15 +269,19 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
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if (test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, vcpu->arch.features) ||
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test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, vcpu->arch.features)) {
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if (kvm_vcpu_enable_ptrauth(vcpu))
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if (kvm_vcpu_enable_ptrauth(vcpu)) {
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ret = -EINVAL;
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goto out;
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}
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}
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switch (vcpu->arch.target) {
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default:
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if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
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if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1))
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if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1)) {
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ret = -EINVAL;
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goto out;
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}
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pstate = VCPU_RESET_PSTATE_SVC;
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} else {
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pstate = VCPU_RESET_PSTATE_EL1;
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@ -90,7 +90,15 @@ static irqreturn_t vgic_v4_doorbell_handler(int irq, void *info)
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!irqd_irq_disabled(&irq_to_desc(irq)->irq_data))
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disable_irq_nosync(irq);
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/*
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* The v4.1 doorbell can fire concurrently with the vPE being
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* made non-resident. Ensure we only update pending_last
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* *after* the non-residency sequence has completed.
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*/
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raw_spin_lock(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vpe_lock);
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vcpu->arch.vgic_cpu.vgic_v3.its_vpe.pending_last = true;
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raw_spin_unlock(&vcpu->arch.vgic_cpu.vgic_v3.its_vpe.vpe_lock);
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kvm_make_request(KVM_REQ_IRQ_PENDING, vcpu);
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kvm_vcpu_kick(vcpu);
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@ -4054,16 +4054,24 @@ static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
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u64 val;
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if (info->req_db) {
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unsigned long flags;
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/*
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* vPE is going to block: make the vPE non-resident with
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* PendingLast clear and DB set. The GIC guarantees that if
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* we read-back PendingLast clear, then a doorbell will be
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* delivered when an interrupt comes.
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*
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* Note the locking to deal with the concurrent update of
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* pending_last from the doorbell interrupt handler that can
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* run concurrently.
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*/
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raw_spin_lock_irqsave(&vpe->vpe_lock, flags);
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val = its_clear_vpend_valid(vlpi_base,
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GICR_VPENDBASER_PendingLast,
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GICR_VPENDBASER_4_1_DB);
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vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
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raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
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} else {
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/*
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* We're not blocking, so just make the vPE non-resident
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