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V4L/DVB (10958): cx231xx: some additional CodingStyle and minor fixes

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changed the pcb-config.c/h to pcb-cfg.c/h for short names.

Signed-off-by: Srinivasa Deevi <srinivasa.deevi@conexant.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Sri Deevi 2009-03-10 21:16:26 -03:00 committed by Mauro Carvalho Chehab
parent b925517645
commit 6e4f574ba4
14 changed files with 1973 additions and 981 deletions
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2
drivers/media/video/Kconfig
View File

@ -807,6 +807,8 @@ source "drivers/media/video/hdpvr/Kconfig"
source "drivers/media/video/em28xx/Kconfig" source "drivers/media/video/em28xx/Kconfig"
source "drivers/media/video/cx231xx/Kconfig"
source "drivers/media/video/usbvision/Kconfig" source "drivers/media/video/usbvision/Kconfig"
source "drivers/media/video/usbvideo/Kconfig" source "drivers/media/video/usbvideo/Kconfig"

50
drivers/media/video/cx231xx/Kconfig
View File

@ -1,35 +1,35 @@
config VIDEO_CX231XX config VIDEO_CX231XX
tristate "Conexant cx231xx USB video capture support" tristate "Conexant cx231xx USB video capture support"
depends on VIDEO_DEV && I2C && INPUT depends on VIDEO_DEV && I2C && INPUT
select VIDEO_TUNER select VIDEO_TUNER
select VIDEO_TVEEPROM select VIDEO_TVEEPROM
select VIDEO_IR select VIDEO_IR
select VIDEOBUF_VMALLOC select VIDEOBUF_VMALLOC
select VIDEO_CX25840 select VIDEO_CX25840
select VIDEO_CX231XX_ALSA select VIDEO_CX231XX_ALSA
---help--- ---help---
This is a video4linux driver for Conexant 231xx USB based TV cards. This is a video4linux driver for Conexant 231xx USB based TV cards.
To compile this driver as a module, choose M here: the To compile this driver as a module, choose M here: the
module will be called cx231xx module will be called cx231xx
config VIDEO_CX231XX_ALSA config VIDEO_CX231XX_ALSA
tristate "Conexant Cx231xx ALSA audio module" tristate "Conexant Cx231xx ALSA audio module"
depends on VIDEO_CX231XX && SND depends on VIDEO_CX231XX && SND
select SND_PCM select SND_PCM
---help--- ---help---
This is an ALSA driver for Cx231xx USB based TV cards. This is an ALSA driver for Cx231xx USB based TV cards.
To compile this driver as a module, choose M here: the To compile this driver as a module, choose M here: the
module will be called cx231xx-alsa module will be called cx231xx-alsa
config VIDEO_CX231XX_DVB config VIDEO_CX231XX_DVB
tristate "DVB/ATSC Support for Cx231xx based TV cards" tristate "DVB/ATSC Support for Cx231xx based TV cards"
depends on VIDEO_CX231XX && DVB_CORE depends on VIDEO_CX231XX && DVB_CORE
select VIDEOBUF_DVB select VIDEOBUF_DVB
select MEDIA_TUNER_XC5000 if !DVB_FE_CUSTOMIZE select MEDIA_TUNER_XC5000 if !DVB_FE_CUSTOMISE
---help--- ---help---
This adds support for DVB cards based on the This adds support for DVB cards based on the
Conexant cx231xx chips. Conexant cx231xx chips.

7
drivers/media/video/cx231xx/Makefile
View File

@ -1,11 +1,8 @@
cx231xx-objs := cx231xx-video.o cx231xx-i2c.o cx231xx-cards.o cx231xx-core.o \ cx231xx-objs := cx231xx-video.o cx231xx-i2c.o cx231xx-cards.o cx231xx-core.o \
cx231xx-avcore.o cx231xx-pcb-config.o cx231xx-vbi.o cx231xx-avcore.o cx231xx-pcb-cfg.o cx231xx-vbi.o
cx231xx-alsa-objs := cx231xx-audio.o
obj-$(CONFIG_VIDEO_CX231XX) += cx231xx.o obj-$(CONFIG_VIDEO_CX231XX) += cx231xx.o
obj-$(CONFIG_VIDEO_CX231XX_ALSA) += cx231xx-alsa.o obj-$(CONFIG_VIDEO_CX231XX_ALSA) += cx231xx-audio.o
obj-$(CONFIG_VIDEO_CX231XX_DVB) += cx231xx-dvb.o obj-$(CONFIG_VIDEO_CX231XX_DVB) += cx231xx-dvb.o
EXTRA_CFLAGS += -Idrivers/media/video EXTRA_CFLAGS += -Idrivers/media/video

14
drivers/media/video/cx231xx/cx231xx-audio.c
View File

@ -38,16 +38,15 @@
#include <sound/control.h> #include <sound/control.h>
#include <media/v4l2-common.h> #include <media/v4l2-common.h>
#include "cx231xx.h" #include "cx231xx.h"
#include "cx231xx-pcb-config.h"
static int debug; static int debug;
module_param(debug, int, 0644); module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "activates debug info"); MODULE_PARM_DESC(debug, "activates debug info");
#define dprintk(fmt, arg...) do { \ #define dprintk(fmt, arg...) do { \
if (debug) \ if (debug) \
printk(KERN_INFO "cx231xx-audio %s: " fmt, \ printk(KERN_INFO "cx231xx-audio %s: " fmt, \
__func__, ##arg); \ __func__, ##arg); \
} while (0) } while (0)
static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
@ -262,9 +261,10 @@ static int snd_pcm_alloc_vmalloc_buffer(struct snd_pcm_substream *subs,
} }
static struct snd_pcm_hardware snd_cx231xx_hw_capture = { static struct snd_pcm_hardware snd_cx231xx_hw_capture = {
.info = SNDRV_PCM_INFO_BLOCK_TRANSFER | .info = SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID, SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_MMAP_VALID,
.formats = SNDRV_PCM_FMTBIT_S16_LE, .formats = SNDRV_PCM_FMTBIT_S16_LE,

337
drivers/media/video/cx231xx/cx231xx-avcore.c
View File

@ -41,7 +41,7 @@
/****************************************************************************** /******************************************************************************
* C O L I B R I - B L O C K C O N T R O L functions * * C O L I B R I - B L O C K C O N T R O L functions *
********************************************************************* ********/ ******************************************************************************/
int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count)
{ {
int status = 0; int status = 0;
@ -53,29 +53,44 @@ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count)
temp = (u8) (ref_count & 0xff); temp = (u8) (ref_count & 0xff);
status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
SUP_BLK_TUNE2, 2, temp, 1); SUP_BLK_TUNE2, 2, temp, 1);
if (status < 0)
return status;
status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
SUP_BLK_TUNE2, 2, SUP_BLK_TUNE2, 2,
&colibri_power_status, 1); &colibri_power_status, 1);
if (status < 0)
return status;
temp = (u8) ((ref_count & 0x300) >> 8); temp = (u8) ((ref_count & 0x300) >> 8);
temp |= 0x40; temp |= 0x40;
status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
SUP_BLK_TUNE1, 2, temp, 1); SUP_BLK_TUNE1, 2, temp, 1);
if (status < 0)
return status;
status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
SUP_BLK_PLL2, 2, 0x0f, 1); SUP_BLK_PLL2, 2, 0x0f, 1);
if (status < 0)
return status;
/* enable pll */ /* enable pll */
while (colibri_power_status != 0x18) { while (colibri_power_status != 0x18) {
status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
SUP_BLK_PWRDN, 2, 0x18, 1); SUP_BLK_PWRDN, 2, 0x18, 1);
if (status < 0) {
cx231xx_info(
": Init Super Block failed in send cmd\n");
break;
}
status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
SUP_BLK_PWRDN, 2, SUP_BLK_PWRDN, 2,
&colibri_power_status, 1); &colibri_power_status, 1);
colibri_power_status &= 0xff; colibri_power_status &= 0xff;
if (status < 0) { if (status < 0) {
cx231xx_info( cx231xx_info(
": Init Super Block failed in send/receive cmds\n"); ": Init Super Block failed in receive cmd\n");
break; break;
} }
i++; i++;
@ -93,6 +108,9 @@ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count)
/* start tuning filter */ /* start tuning filter */
status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
SUP_BLK_TUNE3, 2, 0x40, 1); SUP_BLK_TUNE3, 2, 0x40, 1);
if (status < 0)
return status;
msleep(5); msleep(5);
/* exit tuning */ /* exit tuning */
@ -188,7 +206,10 @@ int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev)
} }
/* /*
we have 3 channel The Analog Front End in Cx231xx has 3 channels. These
channels are used to share between different inputs
like tuner, s-video and composite inputs.
channel 1 ----- pin 1 to pin4(in reg is 1-4) channel 1 ----- pin 1 to pin4(in reg is 1-4)
channel 2 ----- pin 5 to pin8(in reg is 5-8) channel 2 ----- pin 5 to pin8(in reg is 5-8)
channel 3 ----- pin 9 to pin 12(in reg is 9-11) channel 3 ----- pin 9 to pin 12(in reg is 9-11)
@ -242,6 +263,11 @@ int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
{ {
int status = 0; int status = 0;
/*
* FIXME: We need to implement the AFE code for LOW IF and for HI IF.
* Currently, only baseband works.
*/
switch (mode) { switch (mode) {
case AFE_MODE_LOW_IF: case AFE_MODE_LOW_IF:
/* SetupAFEforLowIF(); */ /* SetupAFEforLowIF(); */
@ -270,8 +296,8 @@ int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
return status; return status;
} }
/* For power saving in the EVK */ int cx231xx_colibri_update_power_control(struct cx231xx *dev,
int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) enum AV_MODE avmode)
{ {
u32 colibri_power_status = 0; u32 colibri_power_status = 0;
int status = 0; int status = 0;
@ -279,14 +305,16 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
switch (dev->model) { switch (dev->model) {
case CX231XX_BOARD_CNXT_RDE_250: case CX231XX_BOARD_CNXT_RDE_250:
case CX231XX_BOARD_CNXT_RDU_250: case CX231XX_BOARD_CNXT_RDU_250:
if (avmode == POLARIS_AVMODE_ANALOGT_TV) { if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
while (colibri_power_status != 0x18) { while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS |
FLD_PWRDN_ENABLE_PLL)) {
status = cx231xx_write_i2c_data(dev, status = cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
SUP_BLK_PWRDN, 2, SUP_BLK_PWRDN, 2,
0x18, 1); FLD_PWRDN_TUNING_BIAS |
status = cx231xx_read_i2c_data(dev, FLD_PWRDN_ENABLE_PLL,
1);
status |= cx231xx_read_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
SUP_BLK_PWRDN, 2, SUP_BLK_PWRDN, 2,
&colibri_power_status, &colibri_power_status,
@ -299,11 +327,11 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH1, 2, 0x00, ADC_PWRDN_CLAMP_CH1, 2, 0x00,
1); 1);
status = cx231xx_write_i2c_data(dev, status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH2, 2, 0x00, ADC_PWRDN_CLAMP_CH2, 2, 0x00,
1); 1);
status = cx231xx_write_i2c_data(dev, status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH3, 2, 0x00, ADC_PWRDN_CLAMP_CH3, 2, 0x00,
1); 1);
@ -312,32 +340,36 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH1, 2, 0x70, ADC_PWRDN_CLAMP_CH1, 2, 0x70,
1); 1);
status = cx231xx_write_i2c_data(dev, status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH2, 2, 0x70, ADC_PWRDN_CLAMP_CH2, 2, 0x70,
1); 1);
status = cx231xx_write_i2c_data(dev, status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH3, 2, 0x70, ADC_PWRDN_CLAMP_CH3, 2, 0x70,
1); 1);
status = cx231xx_read_i2c_data(dev, status |= cx231xx_read_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
SUP_BLK_PWRDN, 2, SUP_BLK_PWRDN, 2,
&colibri_power_status, 1); &colibri_power_status, 1);
colibri_power_status |= 0x07; colibri_power_status |= FLD_PWRDN_PD_BANDGAP |
status = cx231xx_write_i2c_data(dev, FLD_PWRDN_PD_BIAS |
FLD_PWRDN_PD_TUNECK;
status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
SUP_BLK_PWRDN, 2, SUP_BLK_PWRDN, 2,
colibri_power_status, 1); colibri_power_status, 1);
} else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS |
while (colibri_power_status != 0x18) { FLD_PWRDN_ENABLE_PLL)) {
status = cx231xx_write_i2c_data(dev, status = cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
SUP_BLK_PWRDN, 2, SUP_BLK_PWRDN, 2,
0x18, 1); FLD_PWRDN_TUNING_BIAS |
status = cx231xx_read_i2c_data(dev, FLD_PWRDN_ENABLE_PLL,
1);
status |= cx231xx_read_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
SUP_BLK_PWRDN, 2, SUP_BLK_PWRDN, 2,
&colibri_power_status, &colibri_power_status,
@ -346,15 +378,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
break; break;
} }
status = cx231xx_write_i2c_data(dev, status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH1, 2, 0x00, ADC_PWRDN_CLAMP_CH1, 2, 0x00,
1); 1);
status = cx231xx_write_i2c_data(dev, status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH2, 2, 0x00, ADC_PWRDN_CLAMP_CH2, 2, 0x00,
1); 1);
status = cx231xx_write_i2c_data(dev, status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH3, 2, 0x00, ADC_PWRDN_CLAMP_CH3, 2, 0x00,
1); 1);
@ -365,12 +397,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
break; break;
default: default:
if (avmode == POLARIS_AVMODE_ANALOGT_TV) { if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
while (colibri_power_status != 0x18) { while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS |
FLD_PWRDN_ENABLE_PLL)) {
status = cx231xx_write_i2c_data(dev, status = cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
SUP_BLK_PWRDN, 2, SUP_BLK_PWRDN, 2,
0x18, 1); FLD_PWRDN_TUNING_BIAS |
status = cx231xx_read_i2c_data(dev, FLD_PWRDN_ENABLE_PLL,
1);
status |= cx231xx_read_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
SUP_BLK_PWRDN, 2, SUP_BLK_PWRDN, 2,
&colibri_power_status, &colibri_power_status,
@ -379,15 +414,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
break; break;
} }
status = cx231xx_write_i2c_data(dev, status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH1, 2, ADC_PWRDN_CLAMP_CH1, 2,
0x40, 1); 0x40, 1);
status = cx231xx_write_i2c_data(dev, status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH2, 2, ADC_PWRDN_CLAMP_CH2, 2,
0x40, 1); 0x40, 1);
status = cx231xx_write_i2c_data(dev, status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH3, 2, ADC_PWRDN_CLAMP_CH3, 2,
0x00, 1); 0x00, 1);
@ -396,33 +431,38 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH1, 2, ADC_PWRDN_CLAMP_CH1, 2,
0x70, 1); 0x70, 1);
status = cx231xx_write_i2c_data(dev, status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH2, 2, ADC_PWRDN_CLAMP_CH2, 2,
0x70, 1); 0x70, 1);
status = cx231xx_write_i2c_data(dev, status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH3, 2, ADC_PWRDN_CLAMP_CH3, 2,
0x70, 1); 0x70, 1);
status = cx231xx_read_i2c_data(dev, status |= cx231xx_read_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
SUP_BLK_PWRDN, 2, SUP_BLK_PWRDN, 2,
&colibri_power_status, &colibri_power_status,
1); 1);
colibri_power_status |= 0x07; colibri_power_status |= FLD_PWRDN_PD_BANDGAP |
status = cx231xx_write_i2c_data(dev, FLD_PWRDN_PD_BIAS |
FLD_PWRDN_PD_TUNECK;
status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
SUP_BLK_PWRDN, 2, SUP_BLK_PWRDN, 2,
colibri_power_status, colibri_power_status,
1); 1);
} else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
while (colibri_power_status != 0x18) { while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS |
FLD_PWRDN_ENABLE_PLL)) {
status = cx231xx_write_i2c_data(dev, status = cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
SUP_BLK_PWRDN, 2, SUP_BLK_PWRDN, 2,
0x18, 1); FLD_PWRDN_TUNING_BIAS |
status = cx231xx_read_i2c_data(dev, FLD_PWRDN_ENABLE_PLL,
1);
status |= cx231xx_read_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
SUP_BLK_PWRDN, 2, SUP_BLK_PWRDN, 2,
&colibri_power_status, &colibri_power_status,
@ -431,15 +471,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
break; break;
} }
status = cx231xx_write_i2c_data(dev, status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH1, 2, ADC_PWRDN_CLAMP_CH1, 2,
0x00, 1); 0x00, 1);
status = cx231xx_write_i2c_data(dev, status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH2, 2, ADC_PWRDN_CLAMP_CH2, 2,
0x00, 1); 0x00, 1);
status = cx231xx_write_i2c_data(dev, status |= cx231xx_write_i2c_data(dev,
Colibri_DEVICE_ADDRESS, Colibri_DEVICE_ADDRESS,
ADC_PWRDN_CLAMP_CH3, 2, ADC_PWRDN_CLAMP_CH3, 2,
0x40, 1); 0x40, 1);
@ -500,7 +540,7 @@ int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input)
/****************************************************************************** /******************************************************************************
* V I D E O / A U D I O D E C O D E R C O N T R O L functions * * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
******************************************++**********************************/ ******************************************************************************/
int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
{ {
int status = 0; int status = 0;
@ -839,7 +879,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
DFE_CTRL1, 2, DFE_CTRL1, 2,
value, 4); value, 4);
/* Wait 15 ms */ /* Wait until AGC locks up */
msleep(1); msleep(1);
/* Disable the auto-VGA enable AGC */ /* Disable the auto-VGA enable AGC */
@ -940,8 +980,7 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
DFE_CTRL3, 2, DFE_CTRL3, 2,
0xCD3F0280, 4); 0xCD3F0280, 4);
if (dev->norm & (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
V4L2_STD_PAL_M)) {
cx231xx_info("do_mode_ctrl_overrides NTSC\n"); cx231xx_info("do_mode_ctrl_overrides NTSC\n");
/* Move the close caption lines out of active video, /* Move the close caption lines out of active video,
@ -967,11 +1006,9 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
FLD_HBLANK_CNT, FLD_HBLANK_CNT,
cx231xx_set_field cx231xx_set_field
(FLD_HBLANK_CNT, 0x79)); (FLD_HBLANK_CNT, 0x79));
} else if (dev->norm & (V4L2_STD_PAL_B | V4L2_STD_PAL_G | } else if (dev->norm & V4L2_STD_SECAM) {
V4L2_STD_PAL_D | V4L2_STD_PAL_I | cx231xx_info("do_mode_ctrl_overrides SECAM\n");
V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { status = cx231xx_read_modify_write_i2c_dword(dev,
cx231xx_info("do_mode_ctrl_overrides PAL\n");
status = cx231xx_read_modify_write_i2c_dword(dev,
HAMMERHEAD_I2C_ADDRESS, HAMMERHEAD_I2C_ADDRESS,
VERT_TIM_CTRL, VERT_TIM_CTRL,
FLD_VBLANK_CNT, 0x24); FLD_VBLANK_CNT, 0x24);
@ -982,12 +1019,9 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
FLD_HBLANK_CNT, FLD_HBLANK_CNT,
cx231xx_set_field cx231xx_set_field
(FLD_HBLANK_CNT, 0x85)); (FLD_HBLANK_CNT, 0x85));
} else if (dev->norm & (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | } else {
V4L2_STD_SECAM_G | V4L2_STD_SECAM_K | cx231xx_info("do_mode_ctrl_overrides PAL\n");
V4L2_STD_SECAM_K1 | V4L2_STD_SECAM_L | status = cx231xx_read_modify_write_i2c_dword(dev,
V4L2_STD_SECAM_LC)) {
cx231xx_info("do_mode_ctrl_overrides SECAM\n");
status = cx231xx_read_modify_write_i2c_dword(dev,
HAMMERHEAD_I2C_ADDRESS, HAMMERHEAD_I2C_ADDRESS,
VERT_TIM_CTRL, VERT_TIM_CTRL,
FLD_VBLANK_CNT, 0x24); FLD_VBLANK_CNT, 0x24);
@ -1276,13 +1310,8 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
status = cx231xx_reg_mask_write(dev, status = cx231xx_reg_mask_write(dev,
HAMMERHEAD_I2C_ADDRESS, 32, HAMMERHEAD_I2C_ADDRESS, 32,
AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
} else { } else if (standard != DIF_USE_BASEBAND) {
switch (standard) { if (standard & V4L2_STD_MN) {
case V4L2_STD_NTSC_M: /* 75 IRE Setup */
case V4L2_STD_NTSC_M_JP:/* Japan, 0 IRE Setup */
case V4L2_STD_PAL_M:
case V4L2_STD_PAL_N:
case V4L2_STD_PAL_Nc:
/* lo if big signal */ /* lo if big signal */
status = cx231xx_reg_mask_write(dev, status = cx231xx_reg_mask_write(dev,
HAMMERHEAD_I2C_ADDRESS, 32, HAMMERHEAD_I2C_ADDRESS, 32,
@ -1304,39 +1333,8 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
status = cx231xx_reg_mask_write(dev, status = cx231xx_reg_mask_write(dev,
HAMMERHEAD_I2C_ADDRESS, 32, HAMMERHEAD_I2C_ADDRESS, 32,
AUD_IO_CTRL, 0, 31, 0x00000003); AUD_IO_CTRL, 0, 31, 0x00000003);
break; } else if ((standard == V4L2_STD_PAL_I) |
(standard & V4L2_STD_SECAM)) {
case V4L2_STD_PAL_B:
case V4L2_STD_PAL_G:
/* C2HH setup */
/* lo if big signal */
status = cx231xx_reg_mask_write(dev,
HAMMERHEAD_I2C_ADDRESS, 32,
AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
/* FUNC_MODE = DIF */
status = cx231xx_reg_mask_write(dev,
HAMMERHEAD_I2C_ADDRESS, 32,
AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
function_mode);
/* IF_MODE */
status = cx231xx_reg_mask_write(dev,
HAMMERHEAD_I2C_ADDRESS, 32,
AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
/* no inv */
status = cx231xx_reg_mask_write(dev,
HAMMERHEAD_I2C_ADDRESS, 32,
AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
break;
case V4L2_STD_PAL_D:
case V4L2_STD_PAL_I:
case V4L2_STD_SECAM_L:
case V4L2_STD_SECAM_LC:
case V4L2_STD_SECAM_B:
case V4L2_STD_SECAM_D:
case V4L2_STD_SECAM_G:
case V4L2_STD_SECAM_K:
case V4L2_STD_SECAM_K1:
/* C2HH setup */ /* C2HH setup */
/* lo if big signal */ /* lo if big signal */
status = cx231xx_reg_mask_write(dev, status = cx231xx_reg_mask_write(dev,
@ -1355,12 +1353,26 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
status = cx231xx_reg_mask_write(dev, status = cx231xx_reg_mask_write(dev,
HAMMERHEAD_I2C_ADDRESS, 32, HAMMERHEAD_I2C_ADDRESS, 32,
AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
break; } else {
/* default PAL BG */
case DIF_USE_BASEBAND: /* C2HH setup */
default: /* lo if big signal */
/* do nothing to config C2HH for baseband */ status = cx231xx_reg_mask_write(dev,
break; HAMMERHEAD_I2C_ADDRESS, 32,
AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
/* FUNC_MODE = DIF */
status = cx231xx_reg_mask_write(dev,
HAMMERHEAD_I2C_ADDRESS, 32,
AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
function_mode);
/* IF_MODE */
status = cx231xx_reg_mask_write(dev,
HAMMERHEAD_I2C_ADDRESS, 32,
AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
/* no inv */
status = cx231xx_reg_mask_write(dev,
HAMMERHEAD_I2C_ADDRESS, 32,
AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
} }
} }
@ -1406,54 +1418,6 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
DIF_MISC_CTRL, 2, DIF_MISC_CTRL, 2,
dif_misc_ctrl_value, 4); dif_misc_ctrl_value, 4);
} else if (standard & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_PLL_CTRL3, 0, 31, 0x00008800);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_AGC_IF_REF, 0, 31, 0x444C1380);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_AGC_IF_INT_CURRENT, 0, 31,
0x26001700);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_AGC_RF_CURRENT, 0, 31,
0x00002660);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_VIDEO_AGC_CTRL, 0, 31,
0x72500800);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_VID_AUD_OVERRIDE, 0, 31,
0x27000100);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_COMP_FLT_CTRL, 0, 31,
0x00A653A8);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_SRC_PHASE_INC, 0, 31,
0x1befbf06);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_SRC_GAIN_CONTROL, 0, 31,
0x000035e8);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_RPT_VARIANCE, 0, 31, 0x00000000);
/* Save the Spec Inversion value */
dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
dif_misc_ctrl_value |= 0x3a013F11;
} else if (standard & V4L2_STD_PAL_D) { } else if (standard & V4L2_STD_PAL_D) {
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_PLL_CTRL, 0, 31, 0x6503bc0c); DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
@ -1499,9 +1463,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
/* Save the Spec Inversion value */ /* Save the Spec Inversion value */
dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
dif_misc_ctrl_value |= 0x3a023F11; dif_misc_ctrl_value |= 0x3a023F11;
} else if (standard & V4L2_STD_PAL_I) { } else if (standard & V4L2_STD_PAL_I) {
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_PLL_CTRL, 0, 31, 0x6503bc0c); DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
@ -1546,7 +1508,6 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
/* Save the Spec Inversion value */ /* Save the Spec Inversion value */
dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
dif_misc_ctrl_value |= 0x3a033F11; dif_misc_ctrl_value |= 0x3a033F11;
} else if (standard & V4L2_STD_PAL_M) { } else if (standard & V4L2_STD_PAL_M) {
/* improved Low Frequency Phase Noise */ /* improved Low Frequency Phase Noise */
status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
@ -1584,13 +1545,10 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
DIF_SOFT_RST_CTRL_REVB, 2, DIF_SOFT_RST_CTRL_REVB, 2,
0x00000000, 4); 0x00000000, 4);
/* Save the Spec Inversion value */ /* Save the Spec Inversion value */
dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
dif_misc_ctrl_value |= 0x3A0A3F10; dif_misc_ctrl_value |= 0x3A0A3F10;
} else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
/* improved Low Frequency Phase Noise */ /* improved Low Frequency Phase Noise */
status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); DIF_PLL_CTRL, 2, 0xFF01FF0C, 4);
@ -1626,14 +1584,12 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
DIF_SOFT_RST_CTRL_REVB, 2, DIF_SOFT_RST_CTRL_REVB, 2,
0x00000000, 4); 0x00000000, 4);
/* Save the Spec Inversion value */ /* Save the Spec Inversion value */
dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
dif_misc_ctrl_value = 0x3A093F10; dif_misc_ctrl_value = 0x3A093F10;
} else if (standard & } else if (standard &
(V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_PLL_CTRL, 0, 31, 0x6503bc0c); DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
@ -1680,9 +1636,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
/* Save the Spec Inversion value */ /* Save the Spec Inversion value */
dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
dif_misc_ctrl_value |= 0x3a023F11; dif_misc_ctrl_value |= 0x3a023F11;
} else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
/* Is it SECAM_L1? */ /* Is it SECAM_L1? */
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_PLL_CTRL, 0, 31, 0x6503bc0c); DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
@ -1730,7 +1684,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
dif_misc_ctrl_value |= 0x3a023F11; dif_misc_ctrl_value |= 0x3a023F11;
} else { } else if (standard & V4L2_STD_NTSC_M) {
/* V4L2_STD_NTSC_M (75 IRE Setup) Or /* V4L2_STD_NTSC_M (75 IRE Setup) Or
V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */
@ -1783,7 +1737,52 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
/* Save the Spec Inversion value */ /* Save the Spec Inversion value */
dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
dif_misc_ctrl_value |= 0x3a003F10; dif_misc_ctrl_value |= 0x3a003F10;
} else {
/* default PAL BG */
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_PLL_CTRL3, 0, 31, 0x00008800);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_AGC_IF_REF, 0, 31, 0x444C1380);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_AGC_IF_INT_CURRENT, 0, 31,
0x26001700);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_AGC_RF_CURRENT, 0, 31,
0x00002660);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_VIDEO_AGC_CTRL, 0, 31,
0x72500800);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_VID_AUD_OVERRIDE, 0, 31,
0x27000100);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_COMP_FLT_CTRL, 0, 31,
0x00A653A8);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_SRC_PHASE_INC, 0, 31,
0x1befbf06);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_SRC_GAIN_CONTROL, 0, 31,
0x000035e8);
status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
DIF_RPT_VARIANCE, 0, 31, 0x00000000);
/* Save the Spec Inversion value */
dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
dif_misc_ctrl_value |= 0x3a013F11;
} }
/* The AGC values should be the same for all standards, /* The AGC values should be the same for all standards,
@ -1826,7 +1825,8 @@ int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
int status = 0; int status = 0;
u32 dwval; u32 dwval;
/* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for SECAM */ /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
* SECAM L/B/D standards */
status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
DIF_AGC_IF_REF, 2, &dwval, 4); DIF_AGC_IF_REF, 2, &dwval, 4);
dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
@ -1864,7 +1864,8 @@ int cx231xx_flatiron_initialize(struct cx231xx *dev)
return status; return status;
} }
int cx231xx_flatiron_update_power_control(struct cx231xx *dev, AV_MODE avmode) int cx231xx_flatiron_update_power_control(struct cx231xx *dev,
enum AV_MODE avmode)
{ {
int status = 0; int status = 0;
u32 value = 0; u32 value = 0;
@ -1908,7 +1909,7 @@ int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input)
/****************************************************************************** /******************************************************************************
* P O W E R C O N T R O L functions * * P O W E R C O N T R O L functions *
******************************************************************************/ ******************************************************************************/
int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
{ {
u8 value[4] = { 0, 0, 0, 0 }; u8 value[4] = { 0, 0, 0, 0 };
u32 tmp = 0; u32 tmp = 0;
@ -2211,7 +2212,7 @@ int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
if (dev->udev->speed == USB_SPEED_HIGH) { if (dev->udev->speed == USB_SPEED_HIGH) {
switch (media_type) { switch (media_type) {
case 81: /* audio */ case 81: /* audio */
cx231xx_info("%s: Audio enter HANC\n", __func__); cx231xx_info("%s: Audio enter HANC\n", __func__);
status = status =
cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
@ -2390,7 +2391,7 @@ int cx231xx_set_gpio_direction(struct cx231xx *dev,
} }
/* /*
* SetGpioPinLogicValue * cx231xx_set_gpio_value
* Sets the value of the GPIO pin to Logic high or low. The Pin under * Sets the value of the GPIO pin to Logic high or low. The Pin under
* reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
* *

244
drivers/media/video/cx231xx/cx231xx-cards.c
View File

@ -61,127 +61,108 @@ static struct cx231xx_reg_seq RDE250_XCV_TUNER[] = {
* Board definitions * Board definitions
*/ */
struct cx231xx_board cx231xx_boards[] = { struct cx231xx_board cx231xx_boards[] = {
[CX231XX_BOARD_UNKNOWN] = { [CX231XX_BOARD_UNKNOWN] = {
.name = "Unknown CX231xx video grabber", .name = "Unknown CX231xx video grabber",
.tuner_type = TUNER_ABSENT, .tuner_type = TUNER_ABSENT,
.input = {{ .input = {{
.type = CX231XX_VMUX_TELEVISION, .type = CX231XX_VMUX_TELEVISION,
.vmux = CX231XX_VIN_3_1, .vmux = CX231XX_VIN_3_1,
.amux = CX231XX_AMUX_VIDEO, .amux = CX231XX_AMUX_VIDEO,
.gpio = 0, .gpio = 0,
}, { }, {
.type = .type = CX231XX_VMUX_COMPOSITE1,
CX231XX_VMUX_COMPOSITE1, .vmux = CX231XX_VIN_2_1,
.vmux = CX231XX_VIN_2_1, .amux = CX231XX_AMUX_LINE_IN,
.amux = CX231XX_AMUX_LINE_IN, .gpio = 0,
.gpio = 0, }, {
}, { .type = CX231XX_VMUX_SVIDEO,
.type = .vmux = CX231XX_VIN_1_1 |
CX231XX_VMUX_SVIDEO, (CX231XX_VIN_1_2 << 8) |
.vmux = CX25840_SVIDEO_ON,
CX231XX_VIN_1_1 | .amux = CX231XX_AMUX_LINE_IN,
(CX231XX_VIN_1_2 << 8) | .gpio = 0,
CX25840_SVIDEO_ON, }
.amux = },
CX231XX_AMUX_LINE_IN, },
.gpio = 0,
} },
},
[CX231XX_BOARD_CNXT_RDE_250] = { [CX231XX_BOARD_CNXT_RDE_250] = {
.name = "Conexant Hybrid TV - RDE250", .name = "Conexant Hybrid TV - RDE250",
.valid = CX231XX_BOARD_VALIDATED, .tuner_type = TUNER_XC5000,
.tuner_type = TUNER_XC5000, .tuner_addr = 0x61,
.tuner_addr = 0x61, .tuner_gpio = RDE250_XCV_TUNER,
.tuner_gpio = RDE250_XCV_TUNER, .tuner_sif_gpio = 0x05,
.tuner_sif_gpio = 0x05, .tuner_scl_gpio = 0x1a,
.tuner_scl_gpio = 0x1a, .tuner_sda_gpio = 0x1b,
.tuner_sda_gpio = 0x1b, .decoder = CX231XX_AVDECODER,
.decoder = CX231XX_AVDECODER, .demod_xfer_mode = 0,
.demod_xfer_mode = 0, .ctl_pin_status_mask = 0xFFFFFFC4,
.ctl_pin_status_mask = 0xFFFFFFC4, .agc_analog_digital_select_gpio = 0x0c,
.agc_analog_digital_select_gpio = 0x0c, .gpio_pin_status_mask = 0x4001000,
.gpio_pin_status_mask = 0x4001000, .tuner_i2c_master = 1,
.tuner_i2c_master = 1, .demod_i2c_master = 2,
.demod_i2c_master = 2, .has_dvb = 1,
.has_dvb = 1, .demod_addr = 0x02,
.demod_addr = 0x02, .norm = V4L2_STD_PAL,
.norm = V4L2_STD_PAL,
.input = {{ .input = {{
.type = .type = CX231XX_VMUX_TELEVISION,
CX231XX_VMUX_TELEVISION, .vmux = CX231XX_VIN_3_1,
.vmux = CX231XX_VIN_3_1, .amux = CX231XX_AMUX_VIDEO,
.amux = CX231XX_AMUX_VIDEO, .gpio = 0,
.gpio = 0, }, {
}, { .type = CX231XX_VMUX_COMPOSITE1,
.type = .vmux = CX231XX_VIN_2_1,
CX231XX_VMUX_COMPOSITE1, .amux = CX231XX_AMUX_LINE_IN,
.vmux = CX231XX_VIN_2_1, .gpio = 0,
.amux = }, {
CX231XX_AMUX_LINE_IN, .type = CX231XX_VMUX_SVIDEO,
.gpio = 0, .vmux = CX231XX_VIN_1_1 |
}, { (CX231XX_VIN_1_2 << 8) |
.type = CX25840_SVIDEO_ON,
CX231XX_VMUX_SVIDEO, .amux = CX231XX_AMUX_LINE_IN,
.vmux = .gpio = 0,
CX231XX_VIN_1_1 | }
(CX231XX_VIN_1_2 << },
8) | },
CX25840_SVIDEO_ON,
.amux =
CX231XX_AMUX_LINE_IN,
.gpio = 0,
} },
},
[CX231XX_BOARD_CNXT_RDU_250] = { [CX231XX_BOARD_CNXT_RDU_250] = {
.name = "Conexant Hybrid TV - RDU250", .name = "Conexant Hybrid TV - RDU250",
.valid = CX231XX_BOARD_VALIDATED, .tuner_type = TUNER_XC5000,
.tuner_type = TUNER_XC5000, .tuner_addr = 0x61,
.tuner_addr = 0x61, .tuner_gpio = RDE250_XCV_TUNER,
.tuner_gpio = RDE250_XCV_TUNER, .tuner_sif_gpio = 0x05,
.tuner_sif_gpio = 0x05, .tuner_scl_gpio = 0x1a,
.tuner_scl_gpio = 0x1a, .tuner_sda_gpio = 0x1b,
.tuner_sda_gpio = 0x1b, .decoder = CX231XX_AVDECODER,
.decoder = CX231XX_AVDECODER, .demod_xfer_mode = 0,
.demod_xfer_mode = 0, .ctl_pin_status_mask = 0xFFFFFFC4,
.ctl_pin_status_mask = 0xFFFFFFC4, .agc_analog_digital_select_gpio = 0x0c,
.agc_analog_digital_select_gpio = 0x0c, .gpio_pin_status_mask = 0x4001000,
.gpio_pin_status_mask = 0x4001000, .tuner_i2c_master = 1,
.tuner_i2c_master = 1, .demod_i2c_master = 2,
.demod_i2c_master = 2, .has_dvb = 1,
.has_dvb = 1, .demod_addr = 0x32,
.demod_addr = 0x32, .norm = V4L2_STD_NTSC,
.norm = V4L2_STD_NTSC,
.input = {{ .input = {{
.type = .type = CX231XX_VMUX_TELEVISION,
CX231XX_VMUX_TELEVISION, .vmux = CX231XX_VIN_3_1,
.vmux = CX231XX_VIN_3_1, .amux = CX231XX_AMUX_VIDEO,
.amux = CX231XX_AMUX_VIDEO, .gpio = 0,
.gpio = 0, }, {
}, { .type = CX231XX_VMUX_COMPOSITE1,
.type = .vmux = CX231XX_VIN_2_1,
CX231XX_VMUX_COMPOSITE1, .amux = CX231XX_AMUX_LINE_IN,
.vmux = CX231XX_VIN_2_1, .gpio = 0,
.amux = }, {
CX231XX_AMUX_LINE_IN, .type = CX231XX_VMUX_SVIDEO,
.gpio = 0, .vmux = CX231XX_VIN_1_1 |
}, { (CX231XX_VIN_1_2 << 8) |
.type = CX25840_SVIDEO_ON,
CX231XX_VMUX_SVIDEO, .amux = CX231XX_AMUX_LINE_IN,
.vmux = .gpio = 0,
CX231XX_VIN_1_1 | }
(CX231XX_VIN_1_2 << },
8) | },
CX25840_SVIDEO_ON,
.amux =
CX231XX_AMUX_LINE_IN,
.gpio = 0,
} },
},
}; };
const unsigned int cx231xx_bcount = ARRAY_SIZE(cx231xx_boards); const unsigned int cx231xx_bcount = ARRAY_SIZE(cx231xx_boards);
@ -243,25 +224,11 @@ void cx231xx_pre_card_setup(struct cx231xx *dev)
cx231xx_info("Identified as %s (card=%d)\n", cx231xx_info("Identified as %s (card=%d)\n",
dev->board.name, dev->model); dev->board.name, dev->model);
/* Do card specific if any */ cx231xx_info("Precard: Board is %s\n", dev->board.name);
switch (dev->model) { /* set the direction for GPIO pins */
case CX231XX_BOARD_CNXT_RDE_250: cx231xx_set_gpio_direction(dev, dev->board.tuner_gpio->bit, 1);
/* do card specific GPIO settings if required */ cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit, 1);
cx231xx_info("Precard: Board is Conexnat RDE 250\n"); cx231xx_set_gpio_direction(dev, dev->board.tuner_sif_gpio, 1);
/* set the direction for GPIO pins */
cx231xx_set_gpio_direction(dev, dev->board.tuner_gpio->bit, 1);
cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit, 1);
cx231xx_set_gpio_direction(dev, dev->board.tuner_sif_gpio, 1);
break;
case CX231XX_BOARD_CNXT_RDU_250:
/* do card specific GPIO settings if required */
cx231xx_info("Precard: Board is Conexnat RDU 250\n");
/* set the direction for GPIO pins */
cx231xx_set_gpio_direction(dev, dev->board.tuner_gpio->bit, 1);
cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit, 1);
cx231xx_set_gpio_direction(dev, dev->board.tuner_sif_gpio, 1);
break;
}
/* request some modules if any required */ /* request some modules if any required */
@ -362,15 +329,6 @@ void cx231xx_card_setup(struct cx231xx *dev)
break; break;
} }
if (dev->board.valid == CX231XX_BOARD_NOT_VALIDATED) {
cx231xx_errdev("\n\n");
cx231xx_errdev("The support for this board weren't "
"valid yet.\n");
cx231xx_errdev("Please send a report of having this working\n");
cx231xx_errdev("not to V4L mailing list (and/or to other "
"addresses)\n\n");
}
/* request some modules */ /* request some modules */
if (dev->board.decoder == CX231XX_AVDECODER) { if (dev->board.decoder == CX231XX_AVDECODER) {
cx231xx_info(": Requesting cx25840 module\n"); cx231xx_info(": Requesting cx25840 module\n");

295
drivers/media/video/cx231xx/cx231xx-conf-reg.h
View File

@ -42,30 +42,30 @@
#define PWR_CTL_EN 0x74 #define PWR_CTL_EN 0x74
/* Polaris Endpoints capture mask for register EP_MODE_SET */ /* Polaris Endpoints capture mask for register EP_MODE_SET */
#define ENABLE_EP1 0x01 /* Bit[0]=1 */ #define ENABLE_EP1 0x01 /* Bit[0]=1 */
#define ENABLE_EP2 0x02 /* Bit[1]=1 */ #define ENABLE_EP2 0x02 /* Bit[1]=1 */
#define ENABLE_EP3 0x04 /* Bit[2]=1 */ #define ENABLE_EP3 0x04 /* Bit[2]=1 */
#define ENABLE_EP4 0x08 /* Bit[3]=1 */ #define ENABLE_EP4 0x08 /* Bit[3]=1 */
#define ENABLE_EP5 0x10 /* Bit[4]=1 */ #define ENABLE_EP5 0x10 /* Bit[4]=1 */
#define ENABLE_EP6 0x20 /* Bit[5]=1 */ #define ENABLE_EP6 0x20 /* Bit[5]=1 */
/* Bit definition for register PWR_CTL_EN */ /* Bit definition for register PWR_CTL_EN */
#define PWR_MODE_MASK 0x17f #define PWR_MODE_MASK 0x17f
#define PWR_AV_EN 0x08 /* bit3 */ #define PWR_AV_EN 0x08 /* bit3 */
#define PWR_ISO_EN 0x40 /* bit6 */ #define PWR_ISO_EN 0x40 /* bit6 */
#define PWR_AV_MODE 0x30 /* bit4,5 */ #define PWR_AV_MODE 0x30 /* bit4,5 */
#define PWR_TUNER_EN 0x04 /* bit2 */ #define PWR_TUNER_EN 0x04 /* bit2 */
#define PWR_DEMOD_EN 0x02 /* bit1 */ #define PWR_DEMOD_EN 0x02 /* bit1 */
#define I2C_DEMOD_EN 0x01 /* bit0 */ #define I2C_DEMOD_EN 0x01 /* bit0 */
#define PWR_RESETOUT_EN 0x100 /* bit8 */ #define PWR_RESETOUT_EN 0x100 /* bit8 */
typedef enum { enum AV_MODE{
POLARIS_AVMODE_DEFAULT = 0, POLARIS_AVMODE_DEFAULT = 0,
POLARIS_AVMODE_DIGITAL = 0x10, POLARIS_AVMODE_DIGITAL = 0x10,
POLARIS_AVMODE_ANALOGT_TV = 0x20, POLARIS_AVMODE_ANALOGT_TV = 0x20,
POLARIS_AVMODE_ENXTERNAL_AV = 0x30, POLARIS_AVMODE_ENXTERNAL_AV = 0x30,
} AV_MODE; };
/* Colibri Registers */ /* Colibri Registers */
@ -91,6 +91,13 @@ typedef enum {
#define ADC_COM_BIAS3 0x0e #define ADC_COM_BIAS3 0x0e
#define TESTBUS_CTRL 0x12 #define TESTBUS_CTRL 0x12
#define FLD_PWRDN_TUNING_BIAS 0x10
#define FLD_PWRDN_ENABLE_PLL 0x08
#define FLD_PWRDN_PD_BANDGAP 0x04
#define FLD_PWRDN_PD_BIAS 0x02
#define FLD_PWRDN_PD_TUNECK 0x01
#define ADC_STATUS_CH1 0x20 #define ADC_STATUS_CH1 0x20
#define ADC_STATUS_CH2 0x40 #define ADC_STATUS_CH2 0x40
#define ADC_STATUS_CH3 0x60 #define ADC_STATUS_CH3 0x60
@ -126,7 +133,7 @@ typedef enum {
#define ADC_INPUT_CH1 0x28 #define ADC_INPUT_CH1 0x28
#define ADC_INPUT_CH2 0x48 #define ADC_INPUT_CH2 0x48
#define ADC_INPUT_CH3 0x68 #define ADC_INPUT_CH3 0x68
#define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */ #define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */
#define ADC_NTF_PRECLMP_EN_CH1 0x29 #define ADC_NTF_PRECLMP_EN_CH1 0x29
#define ADC_NTF_PRECLMP_EN_CH2 0x49 #define ADC_NTF_PRECLMP_EN_CH2 0x49
@ -150,128 +157,128 @@ typedef enum {
#define DIRECT_IF_REVB_BASE 0x00300 #define DIRECT_IF_REVB_BASE 0x00300
/*****************************************************************************/ /*****************************************************************************/
#define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000) /* Reg Size 32 */ #define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000)
/*****************************************************************************/ /*****************************************************************************/
#define FLD_DIF_PLL_LOCK 0x80000000 #define FLD_DIF_PLL_LOCK 0x80000000
/* Reserved [30:29] */ /* Reserved [30:29] */
#define FLD_DIF_PLL_FREE_RUN 0x10000000 #define FLD_DIF_PLL_FREE_RUN 0x10000000
#define FLD_DIF_PLL_FREQ 0x0FFFFFFF #define FLD_DIF_PLL_FREQ 0x0fffffff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004) /* Reg Size 32 */ #define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004)
/*****************************************************************************/ /*****************************************************************************/
#define FLD_DIF_KD_PD 0xFF000000 #define FLD_DIF_KD_PD 0xff000000
/* Reserved [23:20] */ /* Reserved [23:20] */
#define FLD_DIF_KDS_PD 0x000F0000 #define FLD_DIF_KDS_PD 0x000f0000
#define FLD_DIF_KI_PD 0x0000FF00 #define FLD_DIF_KI_PD 0x0000ff00
/* Reserved [7:4] */ /* Reserved [7:4] */
#define FLD_DIF_KIS_PD 0x0000000F #define FLD_DIF_KIS_PD 0x0000000f
/*****************************************************************************/ /*****************************************************************************/
#define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008) /* Reg Size 32 */ #define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008)
/*****************************************************************************/ /*****************************************************************************/
#define FLD_DIF_KD_FD 0xFF000000 #define FLD_DIF_KD_FD 0xff000000
/* Reserved [23:20] */ /* Reserved [23:20] */
#define FLD_DIF_KDS_FD 0x000F0000 #define FLD_DIF_KDS_FD 0x000f0000
#define FLD_DIF_KI_FD 0x0000FF00 #define FLD_DIF_KI_FD 0x0000ff00
#define FLD_DIF_SIG_PROP_SZ 0x000000F0 #define FLD_DIF_SIG_PROP_SZ 0x000000f0
#define FLD_DIF_KIS_FD 0x0000000F #define FLD_DIF_KIS_FD 0x0000000f
/*****************************************************************************/ /*****************************************************************************/
#define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000C) /* Reg Size 32 */ #define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000c)
/*****************************************************************************/ /*****************************************************************************/
#define FLD_DIF_PLL_AGC_REF 0xFFF00000 #define FLD_DIF_PLL_AGC_REF 0xfff00000
#define FLD_DIF_PLL_AGC_KI 0x000F0000 #define FLD_DIF_PLL_AGC_KI 0x000f0000
/* Reserved [15] */ /* Reserved [15] */
#define FLD_DIF_FREQ_LIMIT 0x00007000 #define FLD_DIF_FREQ_LIMIT 0x00007000
#define FLD_DIF_K_FD 0x00000F00 #define FLD_DIF_K_FD 0x00000f00
#define FLD_DIF_DOWNSMPL_FD 0x000000FF #define FLD_DIF_DOWNSMPL_FD 0x000000ff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010) /* Reg Size 32 */ #define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:16] */ /* Reserved [31:16] */
#define FLD_DIF_PLL_AGC_EN 0x00008000 #define FLD_DIF_PLL_AGC_EN 0x00008000
/* Reserved [14:12] */ /* Reserved [14:12] */
#define FLD_DIF_PLL_MAN_GAIN 0x00000FFF #define FLD_DIF_PLL_MAN_GAIN 0x00000fff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014) /* Reg Size 32 */ #define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014)
/*****************************************************************************/ /*****************************************************************************/
#define FLD_DIF_K_AGC_RF 0xF0000000 #define FLD_DIF_K_AGC_RF 0xf0000000
#define FLD_DIF_K_AGC_IF 0x0F000000 #define FLD_DIF_K_AGC_IF 0x0f000000
#define FLD_DIF_K_AGC_INT 0x00F00000 #define FLD_DIF_K_AGC_INT 0x00f00000
/* Reserved [19:12] */ /* Reserved [19:12] */
#define FLD_DIF_IF_REF 0x00000FFF #define FLD_DIF_IF_REF 0x00000fff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018) /* Reg Size 32 */ #define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018)
/*****************************************************************************/ /*****************************************************************************/
#define FLD_DIF_IF_MAX 0xFF000000 #define FLD_DIF_IF_MAX 0xff000000
#define FLD_DIF_IF_MIN 0x00FF0000 #define FLD_DIF_IF_MIN 0x00ff0000
#define FLD_DIF_IF_AGC 0x0000FFFF #define FLD_DIF_IF_AGC 0x0000ffff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001C) /* Reg Size 32 */ #define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001c)
/*****************************************************************************/ /*****************************************************************************/
#define FLD_DIF_INT_MAX 0xFF000000 #define FLD_DIF_INT_MAX 0xff000000
#define FLD_DIF_INT_MIN 0x00FF0000 #define FLD_DIF_INT_MIN 0x00ff0000
#define FLD_DIF_INT_AGC 0x0000FFFF #define FLD_DIF_INT_AGC 0x0000ffff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020) /* Reg Size 32 */ #define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020)
/*****************************************************************************/ /*****************************************************************************/
#define FLD_DIF_RF_MAX 0xFF000000 #define FLD_DIF_RF_MAX 0xff000000
#define FLD_DIF_RF_MIN 0x00FF0000 #define FLD_DIF_RF_MIN 0x00ff0000
#define FLD_DIF_RF_AGC 0x0000FFFF #define FLD_DIF_RF_AGC 0x0000ffff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024) /* Reg Size 32 */ #define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024)
/*****************************************************************************/ /*****************************************************************************/
#define FLD_DIF_IF_AGC_IN 0xFFFF0000 #define FLD_DIF_IF_AGC_IN 0xffff0000
#define FLD_DIF_INT_AGC_IN 0x0000FFFF #define FLD_DIF_INT_AGC_IN 0x0000ffff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028) /* Reg Size 32 */ #define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:16] */ /* Reserved [31:16] */
#define FLD_DIF_RF_AGC_IN 0x0000FFFF #define FLD_DIF_RF_AGC_IN 0x0000ffff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002C) /* Reg Size 32 */ #define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002c)
/*****************************************************************************/ /*****************************************************************************/
#define FLD_DIF_AFD 0xC0000000 #define FLD_DIF_AFD 0xc0000000
#define FLD_DIF_K_VID_AGC 0x30000000 #define FLD_DIF_K_VID_AGC 0x30000000
#define FLD_DIF_LINE_LENGTH 0x0FFF0000 #define FLD_DIF_LINE_LENGTH 0x0fff0000
#define FLD_DIF_AGC_GAIN 0x0000FFFF #define FLD_DIF_AGC_GAIN 0x0000ffff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030) /* Reg Size 32 */ #define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030)
/*****************************************************************************/ /*****************************************************************************/
#define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000 #define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000
/* Reserved [30:30] */ /* Reserved [30:30] */
#define FLD_DIF_AUDIO_MAN_GAIN 0x3F000000 #define FLD_DIF_AUDIO_MAN_GAIN 0x3f000000
/* Reserved [23:17] */ /* Reserved [23:17] */
#define FLD_DIF_VID_AGC_OVERRIDE 0x00010000 #define FLD_DIF_VID_AGC_OVERRIDE 0x00010000
#define FLD_DIF_VID_MAN_GAIN 0x0000FFFF #define FLD_DIF_VID_MAN_GAIN 0x0000ffff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034) /* Reg Size 32 */ #define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034)
/*****************************************************************************/ /*****************************************************************************/
#define FLD_DIF_LPF_FREQ 0xC0000000 #define FLD_DIF_LPF_FREQ 0xc0000000
#define FLD_DIF_AV_PHASE_INC 0x3F000000 #define FLD_DIF_AV_PHASE_INC 0x3f000000
#define FLD_DIF_AUDIO_FREQ 0x00FFFFFF #define FLD_DIF_AUDIO_FREQ 0x00ffffff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038) /* Reg Size 32 */ #define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:24] */ /* Reserved [31:24] */
#define FLD_DIF_IIR23_R2 0x00FF0000 #define FLD_DIF_IIR23_R2 0x00ff0000
#define FLD_DIF_IIR23_R1 0x0000FF00 #define FLD_DIF_IIR23_R1 0x0000ff00
#define FLD_DIF_IIR1_R1 0x000000FF #define FLD_DIF_IIR1_R1 0x000000ff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003C) /* Reg Size 32 */ #define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003c)
/*****************************************************************************/ /*****************************************************************************/
#define FLD_DIF_DIF_BYPASS 0x80000000 #define FLD_DIF_DIF_BYPASS 0x80000000
#define FLD_DIF_FM_NYQ_GAIN 0x40000000 #define FLD_DIF_FM_NYQ_GAIN 0x40000000
@ -289,184 +296,184 @@ typedef enum {
/* Reserved [18] */ /* Reserved [18] */
#define FLD_DIF_IF_FREQ 0x00030000 #define FLD_DIF_IF_FREQ 0x00030000
/* Reserved [15:14] */ /* Reserved [15:14] */
#define FLD_DIF_TIP_OFFSET 0x00003F00 #define FLD_DIF_TIP_OFFSET 0x00003f00
/* Reserved [7:5] */ /* Reserved [7:5] */
#define FLD_DIF_DITHER_ENA 0x00000010 #define FLD_DIF_DITHER_ENA 0x00000010
/* Reserved [3:1] */ /* Reserved [3:1] */
#define FLD_DIF_RF_IF_LOCK 0x00000001 #define FLD_DIF_RF_IF_LOCK 0x00000001
/*****************************************************************************/ /*****************************************************************************/
#define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040) /* Reg Size 32 */ #define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:29] */ /* Reserved [31:29] */
#define FLD_DIF_PHASE_INC 0x1FFFFFFF #define FLD_DIF_PHASE_INC 0x1fffffff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044) /* Reg Size 32 */ #define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:16] */ /* Reserved [31:16] */
#define FLD_DIF_SRC_KI 0x0000FF00 #define FLD_DIF_SRC_KI 0x0000ff00
#define FLD_DIF_SRC_KD 0x000000FF #define FLD_DIF_SRC_KD 0x000000ff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048) /* Reg Size 32 */ #define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:19] */ /* Reserved [31:19] */
#define FLD_DIF_BPF_COEFF_0 0x00070000 #define FLD_DIF_BPF_COEFF_0 0x00070000
/* Reserved [15:4] */ /* Reserved [15:4] */
#define FLD_DIF_BPF_COEFF_1 0x0000000F #define FLD_DIF_BPF_COEFF_1 0x0000000f
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c) /* Reg Size 32 */ #define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:22] */ /* Reserved [31:22] */
#define FLD_DIF_BPF_COEFF_2 0x003F0000 #define FLD_DIF_BPF_COEFF_2 0x003f0000
/* Reserved [15:7] */ /* Reserved [15:7] */
#define FLD_DIF_BPF_COEFF_3 0x0000007F #define FLD_DIF_BPF_COEFF_3 0x0000007f
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050) /* Reg Size 32 */ #define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:24] */ /* Reserved [31:24] */
#define FLD_DIF_BPF_COEFF_4 0x00FF0000 #define FLD_DIF_BPF_COEFF_4 0x00ff0000
/* Reserved [15:8] */ /* Reserved [15:8] */
#define FLD_DIF_BPF_COEFF_5 0x000000FF #define FLD_DIF_BPF_COEFF_5 0x000000ff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054) /* Reg Size 32 */ #define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:25] */ /* Reserved [31:25] */
#define FLD_DIF_BPF_COEFF_6 0x01FF0000 #define FLD_DIF_BPF_COEFF_6 0x01ff0000
/* Reserved [15:9] */ /* Reserved [15:9] */
#define FLD_DIF_BPF_COEFF_7 0x000001FF #define FLD_DIF_BPF_COEFF_7 0x000001ff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058) /* Reg Size 32 */ #define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:26] */ /* Reserved [31:26] */
#define FLD_DIF_BPF_COEFF_8 0x03FF0000 #define FLD_DIF_BPF_COEFF_8 0x03ff0000
/* Reserved [15:10] */ /* Reserved [15:10] */
#define FLD_DIF_BPF_COEFF_9 0x000003FF #define FLD_DIF_BPF_COEFF_9 0x000003ff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005C) /* Reg Size 32 */ #define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005c)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:27] */ /* Reserved [31:27] */
#define FLD_DIF_BPF_COEFF_10 0x07FF0000 #define FLD_DIF_BPF_COEFF_10 0x07ff0000
/* Reserved [15:11] */ /* Reserved [15:11] */
#define FLD_DIF_BPF_COEFF_11 0x000007FF #define FLD_DIF_BPF_COEFF_11 0x000007ff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060) /* Reg Size 32 */ #define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:27] */ /* Reserved [31:27] */
#define FLD_DIF_BPF_COEFF_12 0x07FF0000 #define FLD_DIF_BPF_COEFF_12 0x07ff0000
/* Reserved [15:12] */ /* Reserved [15:12] */
#define FLD_DIF_BPF_COEFF_13 0x00000FFF #define FLD_DIF_BPF_COEFF_13 0x00000fff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064) /* Reg Size 32 */ #define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:28] */ /* Reserved [31:28] */
#define FLD_DIF_BPF_COEFF_14 0x0FFF0000 #define FLD_DIF_BPF_COEFF_14 0x0fff0000
/* Reserved [15:12] */ /* Reserved [15:12] */
#define FLD_DIF_BPF_COEFF_15 0x00000FFF #define FLD_DIF_BPF_COEFF_15 0x00000fff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068) /* Reg Size 32 */ #define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:29] */ /* Reserved [31:29] */
#define FLD_DIF_BPF_COEFF_16 0x1FFF0000 #define FLD_DIF_BPF_COEFF_16 0x1fff0000
/* Reserved [15:13] */ /* Reserved [15:13] */
#define FLD_DIF_BPF_COEFF_17 0x00001FFF #define FLD_DIF_BPF_COEFF_17 0x00001fff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006C) /* Reg Size 32 */ #define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006c)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:29] */ /* Reserved [31:29] */
#define FLD_DIF_BPF_COEFF_18 0x1FFF0000 #define FLD_DIF_BPF_COEFF_18 0x1fff0000
/* Reserved [15:13] */ /* Reserved [15:13] */
#define FLD_DIF_BPF_COEFF_19 0x00001FFF #define FLD_DIF_BPF_COEFF_19 0x00001fff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070) /* Reg Size 32 */ #define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:29] */ /* Reserved [31:29] */
#define FLD_DIF_BPF_COEFF_20 0x1FFF0000 #define FLD_DIF_BPF_COEFF_20 0x1fff0000
/* Reserved [15:14] */ /* Reserved [15:14] */
#define FLD_DIF_BPF_COEFF_21 0x00003FFF #define FLD_DIF_BPF_COEFF_21 0x00003fff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074) /* Reg Size 32 */ #define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:30] */ /* Reserved [31:30] */
#define FLD_DIF_BPF_COEFF_22 0x3FFF0000 #define FLD_DIF_BPF_COEFF_22 0x3fff0000
/* Reserved [15:14] */ /* Reserved [15:14] */
#define FLD_DIF_BPF_COEFF_23 0x00003FFF #define FLD_DIF_BPF_COEFF_23 0x00003fff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078) /* Reg Size 32 */ #define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:30] */ /* Reserved [31:30] */
#define FLD_DIF_BPF_COEFF_24 0x3FFF0000 #define FLD_DIF_BPF_COEFF_24 0x3fff0000
/* Reserved [15:14] */ /* Reserved [15:14] */
#define FLD_DIF_BPF_COEFF_25 0x00003FFF #define FLD_DIF_BPF_COEFF_25 0x00003fff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007C) /* Reg Size 32 */ #define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007c)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:30] */ /* Reserved [31:30] */
#define FLD_DIF_BPF_COEFF_26 0x3FFF0000 #define FLD_DIF_BPF_COEFF_26 0x3fff0000
/* Reserved [15:14] */ /* Reserved [15:14] */
#define FLD_DIF_BPF_COEFF_27 0x00003FFF #define FLD_DIF_BPF_COEFF_27 0x00003fff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080) /* Reg Size 32 */ #define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:30] */ /* Reserved [31:30] */
#define FLD_DIF_BPF_COEFF_28 0x3FFF0000 #define FLD_DIF_BPF_COEFF_28 0x3fff0000
/* Reserved [15:14] */ /* Reserved [15:14] */
#define FLD_DIF_BPF_COEFF_29 0x00003FFF #define FLD_DIF_BPF_COEFF_29 0x00003fff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084) /* Reg Size 32 */ #define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:30] */ /* Reserved [31:30] */
#define FLD_DIF_BPF_COEFF_30 0x3FFF0000 #define FLD_DIF_BPF_COEFF_30 0x3fff0000
/* Reserved [15:14] */ /* Reserved [15:14] */
#define FLD_DIF_BPF_COEFF_31 0x00003FFF #define FLD_DIF_BPF_COEFF_31 0x00003fff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088) /* Reg Size 32 */ #define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:30] */ /* Reserved [31:30] */
#define FLD_DIF_BPF_COEFF_32 0x3FFF0000 #define FLD_DIF_BPF_COEFF_32 0x3fff0000
/* Reserved [15:14] */ /* Reserved [15:14] */
#define FLD_DIF_BPF_COEFF_33 0x00003FFF #define FLD_DIF_BPF_COEFF_33 0x00003fff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008C) /* Reg Size 32 */ #define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008c)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:30] */ /* Reserved [31:30] */
#define FLD_DIF_BPF_COEFF_34 0x3FFF0000 #define FLD_DIF_BPF_COEFF_34 0x3fff0000
/* Reserved [15:14] */ /* Reserved [15:14] */
#define FLD_DIF_BPF_COEFF_35 0x00003FFF #define FLD_DIF_BPF_COEFF_35 0x00003fff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090) /* Reg Size 32 */ #define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:30] */ /* Reserved [31:30] */
#define FLD_DIF_BPF_COEFF_36 0x3FFF0000 #define FLD_DIF_BPF_COEFF_36 0x3fff0000
/* Reserved [15:0] */ /* Reserved [15:0] */
/*****************************************************************************/ /*****************************************************************************/
#define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094) /* Reg Size 32 */ #define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:20] */ /* Reserved [31:20] */
#define FLD_DIF_RPT_VARIANCE 0x000FFFFF #define FLD_DIF_RPT_VARIANCE 0x000fffff
/*****************************************************************************/ /*****************************************************************************/
#define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098) /* Reg Size 32 */ #define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:8] */ /* Reserved [31:8] */
#define FLD_DIF_DIF_SOFT_RST 0x00000080 #define FLD_DIF_DIF_SOFT_RST 0x00000080
@ -479,9 +486,9 @@ typedef enum {
#define FLD_DIF_PLL_RST_MSK 0x00000001 #define FLD_DIF_PLL_RST_MSK 0x00000001
/*****************************************************************************/ /*****************************************************************************/
#define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009C) /* Reg Size 32 */ #define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009c)
/*****************************************************************************/ /*****************************************************************************/
/* Reserved [31:25] */ /* Reserved [31:25] */
#define FLD_DIF_CTL_IP 0x01FFFFFF #define FLD_DIF_CTL_IP 0x01ffffff
#endif #endif

13
drivers/media/video/cx231xx/cx231xx-core.c
View File

@ -54,7 +54,6 @@ static int alt = CX231XX_PINOUT;
module_param(alt, int, 0644); module_param(alt, int, 0644);
MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint"); MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
/* FIXME */
#define cx231xx_isocdbg(fmt, arg...) do {\ #define cx231xx_isocdbg(fmt, arg...) do {\
if (core_debug) \ if (core_debug) \
printk(KERN_INFO "%s %s :"fmt, \ printk(KERN_INFO "%s %s :"fmt, \
@ -308,7 +307,7 @@ int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg,
reg & 0xff, reg >> 8, len & 0xff, len >> 8); reg & 0xff, reg >> 8, len & 0xff, len >> 8);
} }
/* mutex_lock(&dev->ctrl_urb_lock); */ mutex_lock(&dev->ctrl_urb_lock);
ret = usb_control_msg(dev->udev, pipe, req, ret = usb_control_msg(dev->udev, pipe, req,
USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
val, reg, dev->urb_buf, len, HZ); val, reg, dev->urb_buf, len, HZ);
@ -321,7 +320,7 @@ int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg,
if (len) if (len)
memcpy(buf, dev->urb_buf, len); memcpy(buf, dev->urb_buf, len);
/* mutex_unlock(&dev->ctrl_urb_lock); */ mutex_unlock(&dev->ctrl_urb_lock);
if (reg_debug) { if (reg_debug) {
int byte; int byte;
@ -369,13 +368,13 @@ int cx231xx_send_vendor_cmd(struct cx231xx *dev,
cx231xx_isocdbg("\n"); cx231xx_isocdbg("\n");
} }
/* mutex_lock(&dev->ctrl_urb_lock); */ mutex_lock(&dev->ctrl_urb_lock);
ret = usb_control_msg(dev->udev, pipe, ven_req->bRequest, ret = usb_control_msg(dev->udev, pipe, ven_req->bRequest,
ven_req-> ven_req->
direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE, direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
ven_req->wValue, ven_req->wIndex, ven_req->pBuff, ven_req->wValue, ven_req->wIndex, ven_req->pBuff,
ven_req->wLength, HZ); ven_req->wLength, HZ);
/* mutex_unlock(&dev->ctrl_urb_lock); */ mutex_unlock(&dev->ctrl_urb_lock);
return ret; return ret;
} }
@ -432,12 +431,12 @@ int cx231xx_write_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg, char *buf,
cx231xx_isocdbg("\n"); cx231xx_isocdbg("\n");
} }
/* mutex_lock(&dev->ctrl_urb_lock); */ mutex_lock(&dev->ctrl_urb_lock);
memcpy(dev->urb_buf, buf, len); memcpy(dev->urb_buf, buf, len);
ret = usb_control_msg(dev->udev, pipe, req, ret = usb_control_msg(dev->udev, pipe, req,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
val, reg, dev->urb_buf, len, HZ); val, reg, dev->urb_buf, len, HZ);
/* mutex_unlock(&dev->ctrl_urb_lock); */ mutex_unlock(&dev->ctrl_urb_lock);
return ret; return ret;
} }

12
drivers/media/video/cx231xx/cx231xx-i2c.c
View File

@ -42,8 +42,8 @@ MODULE_PARM_DESC(i2c_debug, "enable debug messages [i2c]");
#define dprintk1(lvl, fmt, args...) \ #define dprintk1(lvl, fmt, args...) \
do { \ do { \
if (i2c_debug >= lvl) { \ if (i2c_debug >= lvl) { \
printk(fmt, ##args); \ printk(fmt, ##args); \
} \ } \
} while (0) } while (0)
#define dprintk2(lvl, fmt, args...) \ #define dprintk2(lvl, fmt, args...) \
@ -77,13 +77,10 @@ int cx231xx_i2c_send_bytes(struct i2c_adapter *i2c_adap,
size = msg->len; size = msg->len;
if (size == 2) { /* register write sub addr */ if (size == 2) { /* register write sub addr */
/* Just writing sub address will cause problem
/* Just writing sub address will cause problem to XC5000 * to XC5000. So ignore the request */
So ignore the request */
return 0; return 0;
} else if (size == 4) { /* register write with sub addr */ } else if (size == 4) { /* register write with sub addr */
if (msg->len >= 2) if (msg->len >= 2)
saddr = msg->buf[0] << 8 | msg->buf[1]; saddr = msg->buf[0] << 8 | msg->buf[1];
else if (msg->len == 1) else if (msg->len == 1)
@ -117,7 +114,6 @@ int cx231xx_i2c_send_bytes(struct i2c_adapter *i2c_adap,
msg->buf, msg->buf,
msg->len); msg->len);
} }
} }
/* special case for Xc5000 tuner case */ /* special case for Xc5000 tuner case */

793
drivers/media/video/cx231xx/cx231xx-pcb-cfg.c Normal file
View File

@ -0,0 +1,793 @@
/*
cx231xx-pcb-config.c - driver for Conexant
Cx23100/101/102 USB video capture devices
Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include "cx231xx.h"
#include "cx231xx-conf-reg.h"
/******************************************************************************/
struct pcb_config cx231xx_Scenario[] = {
{
INDEX_SELFPOWER_DIGITAL_ONLY, /* index */
USB_SELF_POWER, /* power_type */
0, /* speed , not decide yet */
MOD_DIGITAL, /* mode */
SOURCE_TS_BDA, /* ts1_source, digital tv only */
NOT_SUPPORTED, /* ts2_source */
NOT_SUPPORTED, /* analog source */
0, /* digital_index */
0, /* analog index */
0, /* dif_index */
0, /* external_index */
1, /* only one configuration */
{
{
0, /* config index */
{
0, /* interrupt ep index */
1, /* ts1 index */
NOT_SUPPORTED, /* TS2 index */
NOT_SUPPORTED, /* AUDIO */
NOT_SUPPORTED, /* VIDEO */
NOT_SUPPORTED, /* VANC */
NOT_SUPPORTED, /* HANC */
NOT_SUPPORTED /* ir_index */
}
,
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
,
/* full-speed config */
{
{
0, /* config index */
{
0, /* interrupt ep index */
1, /* ts1 index */
NOT_SUPPORTED, /* TS2 index */
NOT_SUPPORTED, /* AUDIO */
NOT_SUPPORTED, /* VIDEO */
NOT_SUPPORTED, /* VANC */
NOT_SUPPORTED, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
}
,
{
INDEX_SELFPOWER_DUAL_DIGITAL, /* index */
USB_SELF_POWER, /* power_type */
0, /* speed , not decide yet */
MOD_DIGITAL, /* mode */
SOURCE_TS_BDA, /* ts1_source, digital tv only */
0, /* ts2_source,need update from register */
NOT_SUPPORTED, /* analog source */
0, /* digital_index */
0, /* analog index */
0, /* dif_index */
0, /* external_index */
1, /* only one configuration */
{
{
0, /* config index */
{
0, /* interrupt ep index */
1, /* ts1 index */
2, /* TS2 index */
NOT_SUPPORTED, /* AUDIO */
NOT_SUPPORTED, /* VIDEO */
NOT_SUPPORTED, /* VANC */
NOT_SUPPORTED, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
,
/* full-speed */
{
{
0, /* config index */
{
0, /* interrupt ep index */
1, /* ts1 index */
2, /* TS2 index */
NOT_SUPPORTED, /* AUDIO */
NOT_SUPPORTED, /* VIDEO */
NOT_SUPPORTED, /* VANC */
NOT_SUPPORTED, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
}
,
{
INDEX_SELFPOWER_ANALOG_ONLY, /* index */
USB_SELF_POWER, /* power_type */
0, /* speed , not decide yet */
MOD_ANALOG | MOD_DIF | MOD_EXTERNAL, /* mode ,analog tv only */
NOT_SUPPORTED, /* ts1_source, NOT SUPPORT */
NOT_SUPPORTED, /* ts2_source,NOT SUPPORT */
0, /* analog source, need update */
0, /* digital_index */
0, /* analog index */
0, /* dif_index */
0, /* external_index */
1, /* only one configuration */
{
{
0, /* config index */
{
0, /* interrupt ep index */
NOT_SUPPORTED, /* ts1 index */
NOT_SUPPORTED, /* TS2 index */
1, /* AUDIO */
2, /* VIDEO */
3, /* VANC */
4, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
,
/* full-speed */
{
{
0, /* config index */
{
0, /* interrupt ep index */
NOT_SUPPORTED, /* ts1 index */
NOT_SUPPORTED, /* TS2 index */
1, /* AUDIO */
2, /* VIDEO */
NOT_SUPPORTED, /* VANC */
NOT_SUPPORTED, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
}
,
{
INDEX_SELFPOWER_DUAL, /* index */
USB_SELF_POWER, /* power_type */
0, /* speed , not decide yet */
/* mode ,analog tv and digital path */
MOD_ANALOG | MOD_DIF | MOD_DIGITAL | MOD_EXTERNAL,
0, /* ts1_source,will update in register */
NOT_SUPPORTED, /* ts2_source,NOT SUPPORT */
0, /* analog source need update */
0, /* digital_index */
0, /* analog index */
0, /* dif_index */
0, /* external_index */
1, /* only one configuration */
{
{
0, /* config index */
{
0, /* interrupt ep index */
1, /* ts1 index */
NOT_SUPPORTED, /* TS2 index */
2, /* AUDIO */
3, /* VIDEO */
4, /* VANC */
5, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
,
/* full-speed */
{
{
0, /* config index */
{
0, /* interrupt ep index */
1, /* ts1 index */
NOT_SUPPORTED, /* TS2 index */
2, /* AUDIO */
3, /* VIDEO */
NOT_SUPPORTED, /* VANC */
NOT_SUPPORTED, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
}
,
{
INDEX_SELFPOWER_TRIPLE, /* index */
USB_SELF_POWER, /* power_type */
0, /* speed , not decide yet */
/* mode ,analog tv and digital path */
MOD_ANALOG | MOD_DIF | MOD_DIGITAL | MOD_EXTERNAL,
0, /* ts1_source, update in register */
0, /* ts2_source,update in register */
0, /* analog source, need update */
0, /* digital_index */
0, /* analog index */
0, /* dif_index */
0, /* external_index */
1, /* only one configuration */
{
{
0, /* config index */
{
0, /* interrupt ep index */
1, /* ts1 index */
2, /* TS2 index */
3, /* AUDIO */
4, /* VIDEO */
5, /* VANC */
6, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
,
/* full-speed */
{
{
0, /* config index */
{
0, /* interrupt ep index */
1, /* ts1 index */
2, /* TS2 index */
3, /* AUDIO */
4, /* VIDEO */
NOT_SUPPORTED, /* VANC */
NOT_SUPPORTED, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
}
,
{
INDEX_SELFPOWER_COMPRESSOR, /* index */
USB_SELF_POWER, /* power_type */
0, /* speed , not decide yet */
/* mode ,analog tv AND DIGITAL path */
MOD_ANALOG | MOD_DIF | MOD_DIGITAL | MOD_EXTERNAL,
NOT_SUPPORTED, /* ts1_source, disable */
SOURCE_TS_BDA, /* ts2_source */
0, /* analog source,need update */
0, /* digital_index */
0, /* analog index */
0, /* dif_index */
0, /* external_index */
1, /* only one configuration */
{
{
0, /* config index */
{
0, /* interrupt ep index */
NOT_SUPPORTED, /* ts1 index */
1, /* TS2 index */
2, /* AUDIO */
3, /* VIDEO */
4, /* VANC */
5, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
,
/* full-speed */
{
{
0, /* config index */
{
0, /* interrupt ep index */
NOT_SUPPORTED, /* ts1 index */
1, /* TS2 index */
2, /* AUDIO */
3, /* VIDEO */
NOT_SUPPORTED, /* VANC */
NOT_SUPPORTED, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
}
,
{
INDEX_BUSPOWER_DIGITAL_ONLY, /* index */
USB_BUS_POWER, /* power_type */
0, /* speed , not decide yet */
MOD_DIGITAL, /* mode ,analog tv AND DIGITAL path */
SOURCE_TS_BDA, /* ts1_source, disable */
NOT_SUPPORTED, /* ts2_source */
NOT_SUPPORTED, /* analog source */
0, /* digital_index */
0, /* analog index */
0, /* dif_index */
0, /* external_index */
1, /* only one configuration */
{
{
0, /* config index */
{
0, /* interrupt ep index = 2 */
1, /* ts1 index */
NOT_SUPPORTED, /* TS2 index */
NOT_SUPPORTED, /* AUDIO */
NOT_SUPPORTED, /* VIDEO */
NOT_SUPPORTED, /* VANC */
NOT_SUPPORTED, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
,
/* full-speed */
{
{
0, /* config index */
{
0, /* interrupt ep index = 2 */
1, /* ts1 index */
NOT_SUPPORTED, /* TS2 index */
NOT_SUPPORTED, /* AUDIO */
NOT_SUPPORTED, /* VIDEO */
NOT_SUPPORTED, /* VANC */
NOT_SUPPORTED, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
}
,
{
INDEX_BUSPOWER_ANALOG_ONLY, /* index */
USB_BUS_POWER, /* power_type */
0, /* speed , not decide yet */
MOD_ANALOG, /* mode ,analog tv AND DIGITAL path */
NOT_SUPPORTED, /* ts1_source, disable */
NOT_SUPPORTED, /* ts2_source */
SOURCE_ANALOG, /* analog source--analog */
0, /* digital_index */
0, /* analog index */
0, /* dif_index */
0, /* external_index */
1, /* only one configuration */
{
{
0, /* config index */
{
0, /* interrupt ep index */
NOT_SUPPORTED, /* ts1 index */
NOT_SUPPORTED, /* TS2 index */
1, /* AUDIO */
2, /* VIDEO */
3, /* VANC */
4, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
,
{ /* full-speed */
{
0, /* config index */
{
0, /* interrupt ep index */
NOT_SUPPORTED, /* ts1 index */
NOT_SUPPORTED, /* TS2 index */
1, /* AUDIO */
2, /* VIDEO */
NOT_SUPPORTED, /* VANC */
NOT_SUPPORTED, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
}
,
{
INDEX_BUSPOWER_DIF_ONLY, /* index */
USB_BUS_POWER, /* power_type */
0, /* speed , not decide yet */
/* mode ,analog tv AND DIGITAL path */
MOD_DIF | MOD_ANALOG | MOD_DIGITAL | MOD_EXTERNAL,
SOURCE_TS_BDA, /* ts1_source, disable */
NOT_SUPPORTED, /* ts2_source */
SOURCE_DIF | SOURCE_ANALOG | SOURCE_EXTERNAL, /* analog source, dif */
0, /* digital_index */
0, /* analog index */
0, /* dif_index */
0, /* external_index */
1, /* only one configuration */
{
{
0, /* config index */
{
0, /* interrupt ep index */
1, /* ts1 index */
NOT_SUPPORTED, /* TS2 index */
2, /* AUDIO */
3, /* VIDEO */
4, /* VANC */
5, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
,
{ /* full speed */
{
0, /* config index */
{
0, /* interrupt ep index */
1, /* ts1 index */
NOT_SUPPORTED, /* TS2 index */
2, /* AUDIO */
3, /* VIDEO */
NOT_SUPPORTED, /* VANC */
NOT_SUPPORTED, /* HANC */
NOT_SUPPORTED /* ir_index */
}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
,
{NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
NOT_SUPPORTED}
}
}
}
,
};
/*****************************************************************/
u32 initialize_cx231xx(struct cx231xx *dev)
{
u32 config_info = 0;
struct pcb_config *p_pcb_info;
u8 usb_speed = 1; /* from register,1--HS, 0--FS */
u8 data[4] = { 0, 0, 0, 0 };
u32 ts1_source = 0;
u32 ts2_source = 0;
u32 analog_source = 0;
u8 tmp = 0;
u8 _current_scenario_idx = 0xff;
cx231xx_info("PcbConfig::initialize \n");
ts1_source = SOURCE_TS_BDA;
ts2_source = SOURCE_TS_BDA;
/* read board config register to find out which
pcb config it is related to */
cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, data, 4);
config_info = *((u32 *) data);
cx231xx_info("SC(0x00) register = 0x%x\n", config_info);
usb_speed = (u8) (config_info & 0x1);
/* Verify this device belongs to Bus power or Self power device */
if (config_info & BUS_POWER) { /* bus-power */
switch (config_info & BUSPOWER_MASK) {
case TS1_PORT | BUS_POWER:
cx231xx_Scenario[INDEX_BUSPOWER_DIGITAL_ONLY].speed =
usb_speed;
p_pcb_info =
&cx231xx_Scenario[INDEX_BUSPOWER_DIGITAL_ONLY];
_current_scenario_idx = INDEX_BUSPOWER_DIGITAL_ONLY;
break;
case AVDEC_ENABLE | BUS_POWER:
cx231xx_Scenario[INDEX_BUSPOWER_ANALOG_ONLY].speed =
usb_speed;
p_pcb_info =
&cx231xx_Scenario[INDEX_BUSPOWER_ANALOG_ONLY];
_current_scenario_idx = INDEX_BUSPOWER_ANALOG_ONLY;
break;
case AVDEC_ENABLE | BUS_POWER | TS1_PORT:
cx231xx_Scenario[INDEX_BUSPOWER_DIF_ONLY].speed =
usb_speed;
p_pcb_info = &cx231xx_Scenario[INDEX_BUSPOWER_DIF_ONLY];
_current_scenario_idx = INDEX_BUSPOWER_DIF_ONLY;
break;
default:
cx231xx_info("bad config in buspower!!!!\n");
cx231xx_info("config_info=%x\n",
(config_info & BUSPOWER_MASK));
return 1;
}
} else { /* self-power */
switch (config_info & SELFPOWER_MASK) {
case TS1_PORT | SELF_POWER:
cx231xx_Scenario[INDEX_SELFPOWER_DIGITAL_ONLY].speed =
usb_speed;
p_pcb_info =
&cx231xx_Scenario[INDEX_SELFPOWER_DIGITAL_ONLY];
_current_scenario_idx = INDEX_SELFPOWER_DIGITAL_ONLY;
break;
case TS1_TS2_PORT | SELF_POWER:
cx231xx_Scenario[INDEX_SELFPOWER_DUAL_DIGITAL].speed =
usb_speed;
cx231xx_Scenario[INDEX_SELFPOWER_DUAL_DIGITAL].
ts2_source = ts2_source;
p_pcb_info =
&cx231xx_Scenario[INDEX_SELFPOWER_DUAL_DIGITAL];
_current_scenario_idx = INDEX_SELFPOWER_DUAL_DIGITAL;
break;
case AVDEC_ENABLE | SELF_POWER:
cx231xx_Scenario[INDEX_SELFPOWER_ANALOG_ONLY].speed =
usb_speed;
cx231xx_Scenario[INDEX_SELFPOWER_ANALOG_ONLY].
analog_source = analog_source;
p_pcb_info =
&cx231xx_Scenario[INDEX_SELFPOWER_ANALOG_ONLY];
_current_scenario_idx = INDEX_SELFPOWER_ANALOG_ONLY;
break;
case AVDEC_ENABLE | TS1_PORT | SELF_POWER:
cx231xx_Scenario[INDEX_SELFPOWER_DUAL].speed =
usb_speed;
cx231xx_Scenario[INDEX_SELFPOWER_DUAL].ts1_source =
ts1_source;
cx231xx_Scenario[INDEX_SELFPOWER_DUAL].analog_source =
analog_source;
p_pcb_info = &cx231xx_Scenario[INDEX_SELFPOWER_DUAL];
_current_scenario_idx = INDEX_SELFPOWER_DUAL;
break;
case AVDEC_ENABLE | TS1_TS2_PORT | SELF_POWER:
cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].speed =
usb_speed;
cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].ts1_source =
ts1_source;
cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].ts2_source =
ts2_source;
cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].analog_source =
analog_source;
p_pcb_info = &cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE];
_current_scenario_idx = INDEX_SELFPOWER_TRIPLE;
break;
case AVDEC_ENABLE | TS1VIP_TS2_PORT | SELF_POWER:
cx231xx_Scenario[INDEX_SELFPOWER_COMPRESSOR].speed =
usb_speed;
cx231xx_Scenario[INDEX_SELFPOWER_COMPRESSOR].
analog_source = analog_source;
p_pcb_info =
&cx231xx_Scenario[INDEX_SELFPOWER_COMPRESSOR];
_current_scenario_idx = INDEX_SELFPOWER_COMPRESSOR;
break;
default:
cx231xx_info("bad senario!!!!!\n");
cx231xx_info("config_info=%x\n",
(config_info & SELFPOWER_MASK));
return 1;
}
}
dev->current_scenario_idx = _current_scenario_idx;
memcpy(&dev->current_pcb_config, p_pcb_info,
sizeof(struct pcb_config));
/*******************************************************************/
tmp = (dev->current_pcb_config.index) + 1;
cx231xx_info("scenario %d\n", tmp);
cx231xx_info("type=%x\n", dev->current_pcb_config.type);
cx231xx_info("mode=%x\n", dev->current_pcb_config.mode);
cx231xx_info("speed=%x\n", dev->current_pcb_config.speed);
cx231xx_info("ts1_source=%x\n", dev->current_pcb_config.ts1_source);
cx231xx_info("ts2_source=%x\n", dev->current_pcb_config.ts2_source);
cx231xx_info("analog_source=%x\n",
dev->current_pcb_config.analog_source);
/*******************************************************************/
return 0;
}

235
drivers/media/video/cx231xx/cx231xx-pcb-cfg.h Normal file
View File

@ -0,0 +1,235 @@
/*
cx231xx-pcb-cfg.h - driver for Conexant
Cx23100/101/102 USB video capture devices
Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _PCB_CONFIG_H_
#define _PCB_CONFIG_H_
#include <linux/init.h>
#include <linux/module.h>
/***************************************************************************
* Class Information *
***************************************************************************/
#define CLASS_DEFAULT 0xFF
enum VENDOR_REQUEST_TYPE {
/* Set/Get I2C */
VRT_SET_I2C0 = 0x0,
VRT_SET_I2C1 = 0x1,
VRT_SET_I2C2 = 0x2,
VRT_GET_I2C0 = 0x4,
VRT_GET_I2C1 = 0x5,
VRT_GET_I2C2 = 0x6,
/* Set/Get GPIO */
VRT_SET_GPIO = 0x8,
VRT_GET_GPIO = 0x9,
/* Set/Get GPIE */
VRT_SET_GPIE = 0xA,
VRT_GET_GPIE = 0xB,
/* Set/Get Register Control/Status */
VRT_SET_REGISTER = 0xC,
VRT_GET_REGISTER = 0xD,
/* Get Extended Compat ID Descriptor */
VRT_GET_EXTCID_DESC = 0xFF,
};
enum BYTE_ENABLE_MASK {
ENABLE_ONE_BYTE = 0x1,
ENABLE_TWE_BYTE = 0x3,
ENABLE_THREE_BYTE = 0x7,
ENABLE_FOUR_BYTE = 0xF,
};
#define SPEED_MASK 0x1
enum USB_SPEED{
FULL_SPEED = 0x0, /* 0: full speed */
HIGH_SPEED = 0x1 /* 1: high speed */
};
enum _true_false{
FALSE = 0,
TRUE = 1
};
#define TS_MASK 0x6
enum TS_PORT{
NO_TS_PORT = 0x0, /* 2'b00: Neither port used. PCB not a Hybrid,
only offers Analog TV or Video */
TS1_PORT = 0x4, /* 2'b10: TS1 Input (Hybrid mode :
Digital or External Analog/Compressed source) */
TS1_TS2_PORT = 0x6, /* 2'b11: TS1 & TS2 Inputs
(Dual inputs from Digital and/or
External Analog/Compressed sources) */
TS1_EXT_CLOCK = 0x6, /* 2'b11: TS1 & TS2 as selector
to external clock */
TS1VIP_TS2_PORT = 0x2 /* 2'b01: TS1 used as 656/VIP Output,
TS2 Input (from Compressor) */
};
#define EAVP_MASK 0x8
enum EAV_PRESENT{
NO_EXTERNAL_AV = 0x0, /* 0: No External A/V inputs
(no need for Flatiron),
Analog Tuner must be present */
EXTERNAL_AV = 0x8 /* 1: External A/V inputs
present (requires Flatiron) */
};
#define ATM_MASK 0x30
enum AT_MODE{
DIF_TUNER = 0x30, /* 2'b11: IF Tuner (requires use of DIF) */
BASEBAND_SOUND = 0x20, /* 2'b10: Baseband Composite &
Sound-IF Signals present */
NO_TUNER = 0x10 /* 2'b0x: No Analog Tuner present */
};
#define PWR_SEL_MASK 0x40
enum POWE_TYPE{
SELF_POWER = 0x0, /* 0: self power */
BUS_POWER = 0x40 /* 1: bus power */
};
enum USB_POWE_TYPE{
USB_SELF_POWER = 0,
USB_BUS_POWER
};
#define BO_0_MASK 0x80
enum AVDEC_STATUS{
AVDEC_DISABLE = 0x0, /* 0: A/V Decoder Disabled */
AVDEC_ENABLE = 0x80 /* 1: A/V Decoder Enabled */
};
#define BO_1_MASK 0x100
enum HAMMERHEAD__STATUS{
HAMMERHEAD_ONLY = 0x0, /* 0:Hammerhead Only */
HAMMERHEAD_SC = 0x100 /* 1:Hammerhead and SC */
};
#define BUSPOWER_MASK 0xC4 /* for Polaris spec 0.8 */
#define SELFPOWER_MASK 0x86
/***************************************************************************/
#define NOT_DECIDE_YET 0xFE
#define NOT_SUPPORTED 0xFF
/***************************************************************************
* for mod field use *
***************************************************************************/
#define MOD_DIGITAL 0x1
#define MOD_ANALOG 0x2
#define MOD_DIF 0x4
#define MOD_EXTERNAL 0x8
#define CAP_ALL_MOD 0x0f
/***************************************************************************
* source define *
***************************************************************************/
#define SOURCE_DIGITAL 0x1
#define SOURCE_ANALOG 0x2
#define SOURCE_DIF 0x4
#define SOURCE_EXTERNAL 0x8
#define SOURCE_TS_BDA 0x10
#define SOURCE_TS_ENCODE 0x20
#define SOURCE_TS_EXTERNAL 0x40
/***************************************************************************
* interface information define *
***************************************************************************/
struct INTERFACE_INFO {
u8 interrupt_index;
u8 ts1_index;
u8 ts2_index;
u8 audio_index;
u8 video_index;
u8 vanc_index; /* VBI */
u8 hanc_index; /* Sliced CC */
u8 ir_index;
};
enum INDEX_INTERFACE_INFO{
INDEX_INTERRUPT = 0x0,
INDEX_TS1,
INDEX_TS2,
INDEX_AUDIO,
INDEX_VIDEO,
INDEX_VANC,
INDEX_HANC,
INDEX_IR,
};
/***************************************************************************
* configuration information define *
***************************************************************************/
struct CONFIG_INFO {
u8 config_index;
struct INTERFACE_INFO interface_info;
};
struct pcb_config {
u8 index;
u8 type; /* bus power or self power,
self power--0, bus_power--1 */
u8 speed; /* usb speed, 2.0--1, 1.1--0 */
u8 mode; /* digital , anlog, dif or external A/V */
u32 ts1_source; /* three source -- BDA,External,encode */
u32 ts2_source;
u32 analog_source;
u8 digital_index; /* bus-power used */
u8 analog_index; /* bus-power used */
u8 dif_index; /* bus-power used */
u8 external_index; /* bus-power used */
u8 config_num; /* current config num, 0,1,2,
for self-power, always 0 */
struct CONFIG_INFO hs_config_info[3];
struct CONFIG_INFO fs_config_info[3];
};
enum INDEX_PCB_CONFIG{
INDEX_SELFPOWER_DIGITAL_ONLY = 0x0,
INDEX_SELFPOWER_DUAL_DIGITAL,
INDEX_SELFPOWER_ANALOG_ONLY,
INDEX_SELFPOWER_DUAL,
INDEX_SELFPOWER_TRIPLE,
INDEX_SELFPOWER_COMPRESSOR,
INDEX_BUSPOWER_DIGITAL_ONLY,
INDEX_BUSPOWER_ANALOG_ONLY,
INDEX_BUSPOWER_DIF_ONLY,
INDEX_BUSPOWER_EXTERNAL_ONLY,
INDEX_BUSPOWER_EXTERNAL_ANALOG,
INDEX_BUSPOWER_EXTERNAL_DIF,
INDEX_BUSPOWER_EXTERNAL_DIGITAL,
INDEX_BUSPOWER_DIGITAL_ANALOG,
INDEX_BUSPOWER_DIGITAL_DIF,
INDEX_BUSPOWER_DIGITAL_ANALOG_EXTERNAL,
INDEX_BUSPOWER_DIGITAL_DIF_EXTERNAL,
};
/***************************************************************************/
struct cx231xx;
u32 initialize_cx231xx(struct cx231xx *p_dev);
#endif

930
drivers/media/video/cx231xx/cx231xx-reg.h
View File

File diff suppressed because it is too large Load Diff

8
drivers/media/video/cx231xx/cx231xx-video.c
View File

@ -1655,10 +1655,12 @@ static int vidioc_querycap(struct file *file, void *priv,
cap->capabilities = V4L2_CAP_VBI_CAPTURE | cap->capabilities = V4L2_CAP_VBI_CAPTURE |
#if 0 #if 0
V4L2_CAP_SLICED_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_CAPTURE |
#endif #endif
V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_CAPTURE |
V4L2_CAP_AUDIO | V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; V4L2_CAP_AUDIO |
V4L2_CAP_READWRITE |
V4L2_CAP_STREAMING;
if (dev->tuner_type != TUNER_ABSENT) if (dev->tuner_type != TUNER_ABSENT)
cap->capabilities |= V4L2_CAP_TUNER; cap->capabilities |= V4L2_CAP_TUNER;

14
drivers/media/video/cx231xx/cx231xx.h
View File

@ -35,7 +35,7 @@
#endif #endif
#include "cx231xx-reg.h" #include "cx231xx-reg.h"
#include "cx231xx-pcb-config.h" #include "cx231xx-pcb-cfg.h"
#include "cx231xx-conf-reg.h" #include "cx231xx-conf-reg.h"
#define DRIVER_NAME "cx231xx" #define DRIVER_NAME "cx231xx"
@ -389,7 +389,7 @@ struct cx231xx_i2c_xfer_data {
u8 *p_buffer; /* pointer to the buffer */ u8 *p_buffer; /* pointer to the buffer */
}; };
struct VENDOR_REQUEST_IN{ struct VENDOR_REQUEST_IN {
u8 bRequest; u8 bRequest;
u16 wValue; u16 wValue;
u16 wIndex; u16 wIndex;
@ -407,7 +407,7 @@ struct cx231xx_ctrl {
u32 shift; u32 shift;
}; };
enum TRANSFER_TYPE{ enum TRANSFER_TYPE {
Raw_Video = 0, Raw_Video = 0,
Audio, Audio,
Vbi, /* VANC */ Vbi, /* VANC */
@ -581,12 +581,14 @@ int cx231xx_colibri_init_channels(struct cx231xx *dev);
int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev); int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev);
int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux); int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux);
int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode); int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode);
int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode); int cx231xx_colibri_update_power_control(struct cx231xx *dev,
enum AV_MODE avmode);
int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input); int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input);
/* flatiron related functions */ /* flatiron related functions */
int cx231xx_flatiron_initialize(struct cx231xx *dev); int cx231xx_flatiron_initialize(struct cx231xx *dev);
int cx231xx_flatiron_update_power_control(struct cx231xx *dev, AV_MODE avmode); int cx231xx_flatiron_update_power_control(struct cx231xx *dev,
enum AV_MODE avmode);
int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input); int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input);
/* DIF related functions */ /* DIF related functions */
@ -692,7 +694,7 @@ int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask);
int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type); int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type);
/* Power control functions */ /* Power control functions */
int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode); int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode);
int cx231xx_power_suspend(struct cx231xx *dev); int cx231xx_power_suspend(struct cx231xx *dev);
/* chip specific control functions */ /* chip specific control functions */