forked from luck/tmp_suning_uos_patched
ibm_newemac: Fix EMAC soft reset on 460EX/GT
This patch fixes EMAC soft reset on 460EX/GT when no external clock is available. Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -68,6 +68,10 @@
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#define SDR0_UART3 0x0123
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#define SDR0_CUST0 0x4000
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/* SDRs (460EX/460GT) */
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#define SDR0_ETH_CFG 0x4103
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#define SDR0_ETH_CFG_ECS 0x00000100 /* EMAC int clk source */
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/*
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* All those DCR register addresses are offsets from the base address
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* for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is
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@ -130,6 +130,7 @@ static inline void emac_report_timeout_error(struct emac_instance *dev,
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const char *error)
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{
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if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX |
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EMAC_FTR_460EX_PHY_CLK_FIX |
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EMAC_FTR_440EP_PHY_CLK_FIX))
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DBG(dev, "%s" NL, error);
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else if (net_ratelimit())
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@ -351,10 +352,24 @@ static int emac_reset(struct emac_instance *dev)
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emac_tx_disable(dev);
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}
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#ifdef CONFIG_PPC_DCR_NATIVE
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/* Enable internal clock source */
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if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
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dcri_clrset(SDR0, SDR0_ETH_CFG,
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0, SDR0_ETH_CFG_ECS << dev->cell_index);
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#endif
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out_be32(&p->mr0, EMAC_MR0_SRST);
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while ((in_be32(&p->mr0) & EMAC_MR0_SRST) && n)
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--n;
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#ifdef CONFIG_PPC_DCR_NATIVE
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/* Enable external clock source */
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if (emac_has_feature(dev, EMAC_FTR_460EX_PHY_CLK_FIX))
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dcri_clrset(SDR0, SDR0_ETH_CFG,
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SDR0_ETH_CFG_ECS << dev->cell_index, 0);
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#endif
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if (n) {
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dev->reset_failed = 0;
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return 0;
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@ -2559,6 +2574,9 @@ static int __devinit emac_init_config(struct emac_instance *dev)
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/* Check EMAC version */
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if (of_device_is_compatible(np, "ibm,emac4sync")) {
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dev->features |= (EMAC_FTR_EMAC4 | EMAC_FTR_EMAC4SYNC);
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if (of_device_is_compatible(np, "ibm,emac-460ex") ||
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of_device_is_compatible(np, "ibm,emac-460gt"))
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dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX;
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} else if (of_device_is_compatible(np, "ibm,emac4")) {
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dev->features |= EMAC_FTR_EMAC4;
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if (of_device_is_compatible(np, "ibm,emac-440gx"))
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@ -317,6 +317,10 @@ struct emac_instance {
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* The 405EX and 460EX contain the EMAC4SYNC core
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*/
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#define EMAC_FTR_EMAC4SYNC 0x00000200
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/*
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* Set if we need phy clock workaround for 460ex or 460gt
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*/
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#define EMAC_FTR_460EX_PHY_CLK_FIX 0x00000400
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/* Right now, we don't quite handle the always/possible masks on the
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@ -341,6 +345,7 @@ enum {
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#ifdef CONFIG_IBM_NEW_EMAC_RGMII
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EMAC_FTR_HAS_RGMII |
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#endif
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EMAC_FTR_460EX_PHY_CLK_FIX |
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EMAC_FTR_440EP_PHY_CLK_FIX,
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};
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