forked from luck/tmp_suning_uos_patched
arm64: tegra: Fix Tegra194 HDA {clock,reset}-names ordering
[ Upstream commit 48f6e195039486bc303118948f49a9873acc888f ] As per the HDA binding doc reorder {clock,reset}-names entries for Tegra194. This also serves as a preparation for converting existing binding doc to json-schema. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -782,13 +782,13 @@ hda@3510000 {
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reg = <0x3510000 0x10000>;
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_HDA>,
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<&bpmp TEGRA194_CLK_HDA2CODEC_2X>,
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<&bpmp TEGRA194_CLK_HDA2HDMICODEC>;
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clock-names = "hda", "hda2codec_2x", "hda2hdmi";
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<&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
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<&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
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clock-names = "hda", "hda2hdmi", "hda2codec_2x";
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resets = <&bpmp TEGRA194_RESET_HDA>,
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<&bpmp TEGRA194_RESET_HDA2CODEC_2X>,
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<&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
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reset-names = "hda", "hda2codec_2x", "hda2hdmi";
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<&bpmp TEGRA194_RESET_HDA2HDMICODEC>,
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<&bpmp TEGRA194_RESET_HDA2CODEC_2X>;
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reset-names = "hda", "hda2hdmi", "hda2codec_2x";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
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interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
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<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
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