forked from luck/tmp_suning_uos_patched
irqchip/exiu: Add support for Socionext Synquacer EXIU controller
The Socionext Synquacer SoC has an external interrupt unit (EXIU) that forwards a block of 32 configurable input lines to 32 adjacent level-high type GICv3 SPIs. The EXIU has per-interrupt level/edge and polarity controls, and mask bits that keep the outgoing lines de-asserted, even though the controller may still latch interrupt conditions that occur while the line is masked. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Ard Biesheuvel
Marc Zyngier
parent
0ea04c7322
commit
706cffc1b9
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@ -161,6 +161,9 @@ config ARCH_SEATTLE
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config ARCH_SHMOBILE
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bool
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config ARCH_SYNQUACER
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bool "Socionext SynQuacer SoC Family"
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config ARCH_RENESAS
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bool "Renesas SoC Platforms"
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select ARCH_SHMOBILE
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@ -79,4 +79,5 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
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obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
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obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
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obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o
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obj-$(CONFIG_ARCH_SYNQUACER) += irq-sni-exiu.o
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obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o
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227
drivers/irqchip/irq-sni-exiu.c
Normal file
227
drivers/irqchip/irq-sni-exiu.c
Normal file
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@ -0,0 +1,227 @@
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/*
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* Driver for Socionext External Interrupt Unit (EXIU)
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*
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* Copyright (c) 2017 Linaro, Ltd. <ard.biesheuvel@linaro.org>
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*
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* Based on irq-tegra.c:
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* Copyright (C) 2011 Google, Inc.
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* Copyright (C) 2010,2013, NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define NUM_IRQS 32
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#define EIMASK 0x00
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#define EISRCSEL 0x04
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#define EIREQSTA 0x08
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#define EIRAWREQSTA 0x0C
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#define EIREQCLR 0x10
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#define EILVL 0x14
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#define EIEDG 0x18
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#define EISIR 0x1C
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struct exiu_irq_data {
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void __iomem *base;
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u32 spi_base;
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};
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static void exiu_irq_eoi(struct irq_data *d)
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{
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struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
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writel(BIT(d->hwirq), data->base + EIREQCLR);
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irq_chip_eoi_parent(d);
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}
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static void exiu_irq_mask(struct irq_data *d)
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{
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struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
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u32 val;
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val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq);
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writel_relaxed(val, data->base + EIMASK);
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irq_chip_mask_parent(d);
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}
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static void exiu_irq_unmask(struct irq_data *d)
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{
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struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
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u32 val;
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val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq);
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writel_relaxed(val, data->base + EIMASK);
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irq_chip_unmask_parent(d);
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}
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static void exiu_irq_enable(struct irq_data *d)
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{
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struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
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u32 val;
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/* clear interrupts that were latched while disabled */
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writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
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val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq);
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writel_relaxed(val, data->base + EIMASK);
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irq_chip_enable_parent(d);
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}
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static int exiu_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
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u32 val;
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val = readl_relaxed(data->base + EILVL);
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if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
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val |= BIT(d->hwirq);
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else
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val &= ~BIT(d->hwirq);
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writel_relaxed(val, data->base + EILVL);
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val = readl_relaxed(data->base + EIEDG);
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if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
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val &= ~BIT(d->hwirq);
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else
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val |= BIT(d->hwirq);
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writel_relaxed(val, data->base + EIEDG);
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writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
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return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
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}
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static struct irq_chip exiu_irq_chip = {
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.name = "EXIU",
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.irq_eoi = exiu_irq_eoi,
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.irq_enable = exiu_irq_enable,
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.irq_mask = exiu_irq_mask,
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.irq_unmask = exiu_irq_unmask,
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.irq_set_type = exiu_irq_set_type,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.flags = IRQCHIP_SET_TYPE_MASKED |
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IRQCHIP_SKIP_SET_WAKE |
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IRQCHIP_EOI_THREADED |
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IRQCHIP_MASK_ON_SUSPEND,
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};
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static int exiu_domain_translate(struct irq_domain *domain,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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struct exiu_irq_data *info = domain->host_data;
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 3)
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return -EINVAL;
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if (fwspec->param[0] != GIC_SPI)
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return -EINVAL; /* No PPI should point to this domain */
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*hwirq = fwspec->param[1] - info->spi_base;
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*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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return -EINVAL;
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}
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static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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struct exiu_irq_data *info = dom->host_data;
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irq_hw_number_t hwirq;
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if (fwspec->param_count != 3)
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return -EINVAL; /* Not GIC compliant */
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if (fwspec->param[0] != GIC_SPI)
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return -EINVAL; /* No PPI should point to this domain */
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WARN_ON(nr_irqs != 1);
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hwirq = fwspec->param[1] - info->spi_base;
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irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info);
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parent_fwspec = *fwspec;
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parent_fwspec.fwnode = dom->parent->fwnode;
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return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec);
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}
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static const struct irq_domain_ops exiu_domain_ops = {
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.translate = exiu_domain_translate,
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.alloc = exiu_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int __init exiu_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *parent_domain, *domain;
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struct exiu_irq_data *data;
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int err;
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if (!parent) {
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pr_err("%pOF: no parent, giving up\n", node);
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return -ENODEV;
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}
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("%pOF: unable to obtain parent domain\n", node);
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return -ENXIO;
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}
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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if (of_property_read_u32(node, "socionext,spi-base", &data->spi_base)) {
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pr_err("%pOF: failed to parse 'spi-base' property\n", node);
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err = -ENODEV;
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goto out_free;
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}
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data->base = of_iomap(node, 0);
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if (IS_ERR(data->base)) {
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err = PTR_ERR(data->base);
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goto out_free;
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}
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/* clear and mask all interrupts */
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writel_relaxed(0xFFFFFFFF, data->base + EIREQCLR);
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writel_relaxed(0xFFFFFFFF, data->base + EIMASK);
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domain = irq_domain_add_hierarchy(parent_domain, 0, NUM_IRQS, node,
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&exiu_domain_ops, data);
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if (!domain) {
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pr_err("%pOF: failed to allocate domain\n", node);
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err = -ENOMEM;
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goto out_unmap;
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}
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pr_info("%pOF: %d interrupts forwarded to %pOF\n", node, NUM_IRQS,
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parent);
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return 0;
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out_unmap:
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iounmap(data->base);
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out_free:
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kfree(data);
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return err;
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}
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IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_init);
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