forked from luck/tmp_suning_uos_patched
ARMv7: Add SMP initialisation to proc-v7.S
This patch adds the SMP/nAMP mode setting to __v7_setup and also sets TTBR to shared page table walks if SMP is enabled. The PTWs are also marked inner cacheable for both SMP and UP modes (setting this is fine even if the CPU doesn't support the feature). Signed-off-by: Jon Callan <Jon.Callan@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -20,9 +20,17 @@
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#define TTB_C (1 << 0)
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#define TTB_S (1 << 1)
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#define TTB_RGN_NC (0 << 3)
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#define TTB_RGN_OC_WBWA (1 << 3)
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#define TTB_RGN_OC_WT (2 << 3)
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#define TTB_RGN_OC_WB (3 << 3)
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#ifndef CONFIG_SMP
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#define TTB_FLAGS TTB_C|TTB_RGN_OC_WB @ mark PTWs cacheable, outer WB
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#else
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#define TTB_FLAGS TTB_C|TTB_S|TTB_RGN_OC_WBWA @ mark PTWs cacheable and shared, outer WBWA
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#endif
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ENTRY(cpu_v7_proc_init)
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mov pc, lr
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ENDPROC(cpu_v7_proc_init)
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@ -85,7 +93,7 @@ ENTRY(cpu_v7_switch_mm)
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#ifdef CONFIG_MMU
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mov r2, #0
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ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
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orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
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orr r0, r0, #TTB_FLAGS
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mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
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isb
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1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
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@ -162,6 +170,11 @@ cpu_v7_name:
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* - cache type register is implemented
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*/
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__v7_setup:
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#ifdef CONFIG_SMP
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mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
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orr r0, r0, #(0x1 << 6)
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mcr p15, 0, r0, c1, c0, 1
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#endif
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adr r12, __v7_setup_stack @ the local stack
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stmia r12, {r0-r5, r7, r9, r11, lr}
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bl v7_flush_dcache_all
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@ -174,7 +187,7 @@ __v7_setup:
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#ifdef CONFIG_MMU
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mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
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mcr p15, 0, r10, c2, c0, 2 @ TTB control register
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orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
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orr r4, r4, #TTB_FLAGS
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mcr p15, 0, r4, c2, c0, 1 @ load TTB1
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mov r10, #0x1f @ domains 0, 1 = manager
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mcr p15, 0, r10, c3, c0, 0 @ load domain access register
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