forked from luck/tmp_suning_uos_patched
ath10k: create a chip revision whitelist
This will make it easier to extend and maintain list of supported hardware. Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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5aabff05df
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@ -1136,34 +1136,6 @@ static int ath10k_core_probe_fw(struct ath10k *ar)
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return 0;
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}
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static int ath10k_core_check_chip_id(struct ath10k *ar)
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{
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u32 hw_revision = MS(ar->chip_id, SOC_CHIP_ID_REV);
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ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip_id 0x%08x hw_revision 0x%x\n",
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ar->chip_id, hw_revision);
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/* Check that we are not using hw1.0 (some of them have same pci id
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* as hw2.0) before doing anything else as ath10k crashes horribly
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* due to missing hw1.0 workarounds. */
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switch (hw_revision) {
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case QCA988X_HW_1_0_CHIP_ID_REV:
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ath10k_err(ar, "ERROR: qca988x hw1.0 is not supported\n");
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return -EOPNOTSUPP;
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case QCA988X_HW_2_0_CHIP_ID_REV:
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/* known hardware revision, continue normally */
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return 0;
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default:
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ath10k_warn(ar, "Warning: hardware revision unknown (0x%x), expect problems\n",
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ar->chip_id);
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return 0;
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}
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return 0;
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}
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static void ath10k_core_register_work(struct work_struct *work)
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{
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struct ath10k *ar = container_of(work, struct ath10k, register_work);
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@ -1211,16 +1183,7 @@ static void ath10k_core_register_work(struct work_struct *work)
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int ath10k_core_register(struct ath10k *ar, u32 chip_id)
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{
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int status;
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ar->chip_id = chip_id;
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status = ath10k_core_check_chip_id(ar);
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if (status) {
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ath10k_err(ar, "Unsupported chip id 0x%08x\n", ar->chip_id);
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return status;
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}
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queue_work(ar->workqueue, &ar->register_work);
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return 0;
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@ -64,6 +64,14 @@ static const struct pci_device_id ath10k_pci_id_table[] = {
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{0}
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};
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static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
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/* QCA988X pre 2.0 chips are not supported because they need some nasty
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* hacks. ath10k doesn't have them and these devices crash horribly
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* because of that.
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*/
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{ QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
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};
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static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
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static int ath10k_pci_cold_reset(struct ath10k *ar);
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static int ath10k_pci_warm_reset(struct ath10k *ar);
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@ -2476,6 +2484,23 @@ static void ath10k_pci_release(struct ath10k *ar)
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pci_disable_device(pdev);
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}
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static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
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{
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const struct ath10k_pci_supp_chip *supp_chip;
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int i;
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u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV);
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for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) {
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supp_chip = &ath10k_pci_supp_chips[i];
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if (supp_chip->dev_id == dev_id &&
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supp_chip->rev_id == rev_id)
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return true;
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}
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return false;
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}
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static int ath10k_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *pci_dev)
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{
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@ -2521,6 +2546,12 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
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goto err_sleep;
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}
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if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) {
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ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
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pdev->device, chip_id);
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goto err_sleep;
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}
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ret = ath10k_pci_alloc_pipes(ar);
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if (ret) {
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ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
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@ -152,6 +152,11 @@ struct ath10k_pci_pipe {
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struct tasklet_struct intr;
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};
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struct ath10k_pci_supp_chip {
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u32 dev_id;
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u32 rev_id;
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};
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struct ath10k_pci {
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struct pci_dev *pdev;
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struct device *dev;
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