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[MIPS] Fix pipeline hazard.

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In the the sequence:
        ei
        ..
        mfc0    $x, $status

the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the
kernel code because we knew this was a safe thing to do on all R2 silicon
so far but new silicon is changing this.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2007-03-20 13:56:50 +00:00
parent 83598f1cb0
commit 7605b39061
1 changed files with 1 additions and 0 deletions
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include/asm-mips/hazards.h
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@ -52,6 +52,7 @@ ASMMACRO(tlb_probe_hazard,
_ehb
)
ASMMACRO(irq_enable_hazard,
_ehb
)
ASMMACRO(irq_disable_hazard,
_ehb