forked from luck/tmp_suning_uos_patched
PCI: Use dev->has_secondary_link to find downstream PCIe links
Previously we assumed that PCIe Root Ports and Downstream Ports had Links on their secondary side. That is true in most systems, but it is possible to connect a switch with either an Upstream or a Downstream Port leading downstream. Instead of relying on the component type to identify devices that have links leading downstream, use the "dev->has_secondary_link" field. [bhelgaas: changelog] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -425,8 +425,7 @@ static pci_ers_result_t reset_link(struct pci_dev *dev)
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if (driver && driver->reset_link) {
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status = driver->reset_link(udev);
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} else if (pci_pcie_type(udev) == PCI_EXP_TYPE_DOWNSTREAM ||
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pci_pcie_type(udev) == PCI_EXP_TYPE_ROOT_PORT) {
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} else if (udev->has_secondary_link) {
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status = default_reset_link(udev);
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} else {
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dev_printk(KERN_DEBUG, &dev->dev,
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@ -1629,7 +1629,7 @@ static int only_one_child(struct pci_bus *bus)
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return 0;
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if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
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return 1;
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if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM &&
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if (parent->has_secondary_link &&
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!pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
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return 1;
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return 0;
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@ -108,8 +108,7 @@ static void pci_vc_enable(struct pci_dev *dev, int pos, int res)
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struct pci_dev *link = NULL;
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/* Enable VCs from the downstream device */
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
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pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM)
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if (!dev->has_secondary_link)
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return;
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ctrl_pos = pos + PCI_VC_RES_CTRL + (res * PCI_CAP_VC_PER_VC_SIZEOF);
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