forked from luck/tmp_suning_uos_patched
docs: sh: convert register-banks.txt to ReST
- Add a SPDX header; - Adjust document title to follow ReST style; - Add blank lines to make ReST markup happy - Add it to sh/index.rst. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/adf117cf1edd7f43cb839ff2800f4315dfbcce13.1592203650.git.mchehab+huawei@kernel.org Signed-off-by: Jonathan Corbet <corbet@lwn.net>
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@ -8,6 +8,7 @@ SuperH Interfaces Guide
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:maxdepth: 1
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new-machine
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register-banks
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Memory Management
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=================
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@ -1,5 +1,8 @@
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Notes on register bank usage in the kernel
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==========================================
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.. SPDX-License-Identifier: GPL-2.0
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==========================================
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Notes on register bank usage in the kernel
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==========================================
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Introduction
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------------
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@ -23,11 +26,15 @@ Presently the kernel uses several of these registers.
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- r0_bank, r1_bank (referenced as k0 and k1, used for scratch
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registers when doing exception handling).
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- r2_bank (used to track the EXPEVT/INTEVT code)
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- Used by do_IRQ() and friends for doing irq mapping based off
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of the interrupt exception vector jump table offset
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- r6_bank (global interrupt mask)
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- The SR.IMASK interrupt handler makes use of this to set the
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interrupt priority level (used by local_irq_enable())
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- r7_bank (current)
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- r7_bank (current)
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@ -85,7 +85,7 @@ config CPU_HAS_SR_RB
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that are lacking this bit must have another method in place for
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accomplishing what is taken care of by the banked registers.
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See <file:Documentation/sh/register-banks.txt> for further
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See <file:Documentation/sh/register-banks.rst> for further
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information on SR.RB and register banking in the kernel in general.
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config CPU_HAS_PTEAEX
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