forked from luck/tmp_suning_uos_patched
[AVR32] Make sure all genclocks have a parent
Initialize the parent field of each generic clock by looking at the PM registers. This means that the genclock operations can always assume that the parent field is non-null, so they don't have to check. Also remove a few unnecessary BUG_ON()s. Extracted from a patch by David Brownell. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
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160f34531a
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7a5fe23879
@ -310,8 +310,6 @@ static void genclk_mode(struct clk *clk, int enabled)
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{
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u32 control;
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BUG_ON(clk->index > 7);
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control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
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if (enabled)
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control |= SM_BIT(CEN);
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@ -325,11 +323,6 @@ static unsigned long genclk_get_rate(struct clk *clk)
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u32 control;
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unsigned long div = 1;
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BUG_ON(clk->index > 7);
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if (!clk->parent)
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return 0;
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control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
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if (control & SM_BIT(DIVEN))
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div = 2 * (SM_BFEXT(DIV, control) + 1);
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@ -342,11 +335,6 @@ static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
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u32 control;
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unsigned long parent_rate, actual_rate, div;
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BUG_ON(clk->index > 7);
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if (!clk->parent)
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return 0;
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parent_rate = clk->parent->get_rate(clk->parent);
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control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
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@ -373,11 +361,8 @@ int genclk_set_parent(struct clk *clk, struct clk *parent)
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{
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u32 control;
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BUG_ON(clk->index > 7);
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printk("clk %s: new parent %s (was %s)\n",
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clk->name, parent->name,
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clk->parent ? clk->parent->name : "(null)");
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clk->name, parent->name, clk->parent->name);
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control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
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@ -399,6 +384,22 @@ int genclk_set_parent(struct clk *clk, struct clk *parent)
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return 0;
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}
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static void __init genclk_init_parent(struct clk *clk)
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{
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u32 control;
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struct clk *parent;
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BUG_ON(clk->index > 7);
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control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
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if (control & SM_BIT(OSCSEL))
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parent = (control & SM_BIT(PLLSEL)) ? &pll1 : &osc1;
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else
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parent = (control & SM_BIT(PLLSEL)) ? &pll0 : &osc0;
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clk->parent = parent;
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}
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/* --------------------------------------------------------------------
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* System peripherals
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* -------------------------------------------------------------------- */
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@ -872,6 +873,50 @@ at32_add_device_lcdc(unsigned int id, struct lcdc_platform_data *data)
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return pdev;
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}
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/* --------------------------------------------------------------------
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* GCLK
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* -------------------------------------------------------------------- */
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static struct clk gclk0 = {
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.name = "gclk0",
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.mode = genclk_mode,
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.get_rate = genclk_get_rate,
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.set_rate = genclk_set_rate,
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.set_parent = genclk_set_parent,
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.index = 0,
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};
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static struct clk gclk1 = {
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.name = "gclk1",
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.mode = genclk_mode,
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.get_rate = genclk_get_rate,
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.set_rate = genclk_set_rate,
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.set_parent = genclk_set_parent,
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.index = 1,
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};
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static struct clk gclk2 = {
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.name = "gclk2",
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.mode = genclk_mode,
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.get_rate = genclk_get_rate,
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.set_rate = genclk_set_rate,
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.set_parent = genclk_set_parent,
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.index = 2,
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};
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static struct clk gclk3 = {
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.name = "gclk3",
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.mode = genclk_mode,
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.get_rate = genclk_get_rate,
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.set_rate = genclk_set_rate,
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.set_parent = genclk_set_parent,
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.index = 3,
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};
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static struct clk gclk4 = {
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.name = "gclk4",
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.mode = genclk_mode,
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.get_rate = genclk_get_rate,
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.set_rate = genclk_set_rate,
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.set_parent = genclk_set_parent,
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.index = 4,
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};
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struct clk *at32_clock_list[] = {
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&osc32k,
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&osc0,
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@ -908,6 +953,11 @@ struct clk *at32_clock_list[] = {
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&atmel_spi1_spi_clk,
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&lcdc0_hclk,
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&lcdc0_pixclk,
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&gclk0,
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&gclk1,
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&gclk2,
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&gclk3,
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&gclk4,
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};
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unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
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@ -936,6 +986,13 @@ void __init at32_clock_init(void)
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if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC))
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pll1.parent = &osc1;
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genclk_init_parent(&gclk0);
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genclk_init_parent(&gclk1);
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genclk_init_parent(&gclk2);
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genclk_init_parent(&gclk3);
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genclk_init_parent(&gclk4);
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genclk_init_parent(&lcdc0_pixclk);
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/*
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* Turn on all clocks that have at least one user already, and
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* turn off everything else. We only do this for module
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