forked from luck/tmp_suning_uos_patched
ARM: mxs: select STMP_DEVICE and use it for timer code
Select STMP_DEVICE and in timer code replace mxs_reset_block() with stmp_reset_block(), use STMP_OFFSET_REG_SET/CLR to replace __mxs_setl/clrl. As the result, <mach/mxs.h> and <mach/common.h> includsion can be removed from timer.c now. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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220d2f269a
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@ -480,6 +480,7 @@ config ARCH_MXS
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select MULTI_IRQ_HANDLER
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select PINCTRL
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select SPARSE_IRQ
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select STMP_DEVICE
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select USE_OF
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help
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Support for Freescale MXS-based family of processors
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@ -28,11 +28,10 @@
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/stmp_device.h>
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#include <asm/mach/time.h>
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#include <asm/sched_clock.h>
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#include <mach/mxs.h>
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#include <mach/common.h>
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/*
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* There are 2 versions of the timrot on Freescale MXS-based SoCs.
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@ -85,20 +84,20 @@ static u32 timrot_major_version;
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static inline void timrot_irq_disable(void)
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{
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__mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
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mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
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__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
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HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
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}
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static inline void timrot_irq_enable(void)
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{
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__mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
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mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
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__raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
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HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET);
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}
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static void timrot_irq_acknowledge(void)
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{
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__mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
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mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
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__raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base +
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HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
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}
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static cycle_t timrotv1_get_cycles(struct clocksource *cs)
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@ -262,7 +261,7 @@ static void __init mxs_timer_init(struct device_node *np)
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/*
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* Initialize timers to a known state
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*/
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mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
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stmp_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
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/* get timrot version */
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timrot_major_version = __raw_readl(mxs_timrot_base +
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