forked from luck/tmp_suning_uos_patched
ARM: S5PV310: Update CMU registers for CPUFREQ
This patch adds CMU(Clock Management Unit) registers for S5PV310/S5PC210 CPUFREQ driver and modifies some register names according to datasheet. Signed-off-by: Sunyoung Kang <sy0816.kang@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Sunyoung Kang
Kukjin Kim
parent
90a8a73c06
commit
7af36b9787
@ -244,7 +244,7 @@ static struct clksrc_clk clk_mout_corebus = {
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.id = -1,
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},
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.sources = &clkset_mout_corebus,
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.reg_src = { .reg = S5P_CLKSRC_CORE, .shift = 4, .size = 1 },
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.reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
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};
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static struct clksrc_clk clk_sclk_dmc = {
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@ -253,7 +253,7 @@ static struct clksrc_clk clk_sclk_dmc = {
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.id = -1,
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.parent = &clk_mout_corebus.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
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};
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static struct clksrc_clk clk_aclk_cored = {
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@ -262,7 +262,7 @@ static struct clksrc_clk clk_aclk_cored = {
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.id = -1,
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.parent = &clk_sclk_dmc.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
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};
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static struct clksrc_clk clk_aclk_corep = {
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@ -271,7 +271,7 @@ static struct clksrc_clk clk_aclk_corep = {
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.id = -1,
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.parent = &clk_aclk_cored.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
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};
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static struct clksrc_clk clk_aclk_acp = {
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@ -280,7 +280,7 @@ static struct clksrc_clk clk_aclk_acp = {
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.id = -1,
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.parent = &clk_mout_corebus.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
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};
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static struct clksrc_clk clk_pclk_acp = {
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@ -289,7 +289,7 @@ static struct clksrc_clk clk_pclk_acp = {
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.id = -1,
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.parent = &clk_aclk_acp.clk,
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},
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.reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 },
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.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
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};
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/* Core list of CMU_TOP side */
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@ -19,6 +19,12 @@
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#define S5P_INFORM0 S5P_CLKREG(0x800)
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#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500)
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#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600)
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#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500)
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#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
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#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
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#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
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#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
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@ -58,6 +64,8 @@
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#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
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#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
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#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
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#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
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#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
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#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
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@ -66,8 +74,9 @@
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#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
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#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
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#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)
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#define S5P_CLKDIV_CORE0 S5P_CLKREG(0x10500)
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#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200)
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#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500)
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#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600)
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#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
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#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
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@ -84,6 +93,70 @@
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#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
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/* APLL_LOCK */
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#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */
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/* APLL_CON0 */
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#define S5P_APLLCON0_ENABLE_SHIFT (31)
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#define S5P_APLLCON0_LOCKED_SHIFT (29)
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#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
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/* CLK_SRC_CPU */
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#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
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#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
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/* CLKDIV_CPU0 */
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#define S5P_CLKDIV_CPU0_CORE_SHIFT (0)
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#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
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#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4)
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#define S5P_CLKDIV_CPU0_COREM0_MASK (0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)
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#define S5P_CLKDIV_CPU0_COREM1_SHIFT (8)
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#define S5P_CLKDIV_CPU0_COREM1_MASK (0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)
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#define S5P_CLKDIV_CPU0_PERIPH_SHIFT (12)
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#define S5P_CLKDIV_CPU0_PERIPH_MASK (0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)
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#define S5P_CLKDIV_CPU0_ATB_SHIFT (16)
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#define S5P_CLKDIV_CPU0_ATB_MASK (0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)
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#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
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#define S5P_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)
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#define S5P_CLKDIV_CPU0_APLL_SHIFT (24)
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#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
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/* CLKDIV_DMC0 */
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#define S5P_CLKDIV_DMC0_ACP_SHIFT (0)
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#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
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#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
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#define S5P_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)
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#define S5P_CLKDIV_DMC0_DPHY_SHIFT (8)
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#define S5P_CLKDIV_DMC0_DPHY_MASK (0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)
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#define S5P_CLKDIV_DMC0_DMC_SHIFT (12)
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#define S5P_CLKDIV_DMC0_DMC_MASK (0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)
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#define S5P_CLKDIV_DMC0_DMCD_SHIFT (16)
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#define S5P_CLKDIV_DMC0_DMCD_MASK (0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)
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#define S5P_CLKDIV_DMC0_DMCP_SHIFT (20)
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#define S5P_CLKDIV_DMC0_DMCP_MASK (0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)
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#define S5P_CLKDIV_DMC0_COPY2_SHIFT (24)
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#define S5P_CLKDIV_DMC0_COPY2_MASK (0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)
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#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28)
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#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
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/* CLKDIV_TOP */
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#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0)
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#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
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#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4)
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#define S5P_CLKDIV_TOP_ACLK100_MASK (0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)
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#define S5P_CLKDIV_TOP_ACLK160_SHIFT (8)
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#define S5P_CLKDIV_TOP_ACLK160_MASK (0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)
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#define S5P_CLKDIV_TOP_ACLK133_SHIFT (12)
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#define S5P_CLKDIV_TOP_ACLK133_MASK (0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)
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#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16)
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#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
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/* CLKDIV_LEFTBUS / CLKDIV_RIGHTBUS*/
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#define S5P_CLKDIV_BUS_GDLR_SHIFT (0)
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#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
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#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
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#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
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/* Compatibility defines */
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#define S5P_EPLL_CON S5P_EPLL_CON0
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