forked from luck/tmp_suning_uos_patched
drm/radeon: Add probing of clocks from device-tree
When we find no ROM we understand and a device-tree is present, see if we can retreive clock info from there. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -91,6 +91,85 @@ uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
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return mclk;
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}
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#ifdef CONFIG_OF
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/*
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* Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
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* tree. Hopefully, ATI OF driver is kind enough to fill these
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*/
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static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
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{
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struct radeon_device *rdev = dev->dev_private;
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struct device_node *dp = rdev->pdev->dev.of_node;
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const u32 *val;
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struct radeon_pll *p1pll = &rdev->clock.p1pll;
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struct radeon_pll *p2pll = &rdev->clock.p2pll;
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struct radeon_pll *spll = &rdev->clock.spll;
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struct radeon_pll *mpll = &rdev->clock.mpll;
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if (dp == NULL)
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return false;
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val = of_get_property(dp, "ATY,RefCLK", NULL);
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if (!val || !*val) {
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printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
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return false;
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}
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p1pll->reference_freq = p2pll->reference_freq = (*val) / 10;
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p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
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if (p1pll->reference_div < 2)
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p1pll->reference_div = 12;
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p2pll->reference_div = p1pll->reference_div;
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/* These aren't in the device-tree */
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if (rdev->family >= CHIP_R420) {
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p1pll->pll_in_min = 100;
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p1pll->pll_in_max = 1350;
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p1pll->pll_out_min = 20000;
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p1pll->pll_out_max = 50000;
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p2pll->pll_in_min = 100;
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p2pll->pll_in_max = 1350;
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p2pll->pll_out_min = 20000;
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p2pll->pll_out_max = 50000;
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} else {
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p1pll->pll_in_min = 40;
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p1pll->pll_in_max = 500;
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p1pll->pll_out_min = 12500;
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p1pll->pll_out_max = 35000;
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p2pll->pll_in_min = 40;
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p2pll->pll_in_max = 500;
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p2pll->pll_out_min = 12500;
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p2pll->pll_out_max = 35000;
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}
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spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
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spll->reference_div = mpll->reference_div =
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RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
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RADEON_M_SPLL_REF_DIV_MASK;
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val = of_get_property(dp, "ATY,SCLK", NULL);
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if (val && *val)
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rdev->clock.default_sclk = (*val) / 10;
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else
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rdev->clock.default_sclk =
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radeon_legacy_get_engine_clock(rdev);
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val = of_get_property(dp, "ATY,MCLK", NULL);
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if (val && *val)
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rdev->clock.default_mclk = (*val) / 10;
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else
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rdev->clock.default_mclk =
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radeon_legacy_get_memory_clock(rdev);
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DRM_INFO("Using device-tree clock info\n");
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return true;
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}
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#else
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static bool __devinit radeon_read_clocks_OF(struct drm_device *dev)
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{
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return false;
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}
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#endif /* CONFIG_OF */
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void radeon_get_clock_info(struct drm_device *dev)
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{
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struct radeon_device *rdev = dev->dev_private;
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@ -105,6 +184,8 @@ void radeon_get_clock_info(struct drm_device *dev)
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ret = radeon_atom_get_clock_info(dev);
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else
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ret = radeon_combios_get_clock_info(dev);
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if (!ret)
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ret = radeon_read_clocks_OF(dev);
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if (ret) {
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if (p1pll->reference_div < 2) {
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