forked from luck/tmp_suning_uos_patched
DMAENGINE: DMA40 U8500 platform configuration
This completes the DMA40 support with the platform-specific configuration for U8500/DB8500. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Acked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Reviewed-by: Alessandro Rubini <rubini@unipv.it> Cc: STEricsson_nomadik_linux@list.st.com Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> [fixed up dma40_{tx|rx}_map declaration/initialization] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Linus Walleij
Dan Williams
parent
b3040e4067
commit
7b8ddb06e5
@ -411,7 +411,7 @@ static struct clk_lookup u8500_common_clks[] = {
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CLK(apetraceclk, "apetrace", NULL),
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CLK(mcdeclk, "mcde", NULL),
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CLK(ipi2clk, "ipi2", NULL),
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CLK(dmaclk, "dma40", NULL),
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CLK(dmaclk, "dma40.0", NULL),
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CLK(b2r2clk, "b2r2", NULL),
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CLK(tvclk, "tv", NULL),
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};
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@ -32,6 +32,7 @@ static struct platform_device *platform_devs[] __initdata = {
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&u8500_gpio_devs[6],
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&u8500_gpio_devs[7],
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&u8500_gpio_devs[8],
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&u8500_dma40_device,
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};
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/* minimum static i/o mapping required to boot U8500 platforms */
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@ -71,6 +72,9 @@ void __init u8500_init_devices(void)
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{
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ux500_init_devices();
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if (cpu_is_u8500ed())
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dma40_u8500ed_fixup();
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/* Register the platform devices */
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platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
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@ -12,9 +12,13 @@
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#include <linux/gpio.h>
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#include <linux/amba/bus.h>
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#include <plat/ste_dma40.h>
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#include <mach/hardware.h>
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#include <mach/setup.h>
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#include "ste-dma40-db8500.h"
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static struct nmk_gpio_platform_data u8500_gpio_data[] = {
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GPIO_DATA("GPIO-0-31", 0),
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GPIO_DATA("GPIO-32-63", 32), /* 37..63 not routed to pin */
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@ -105,3 +109,108 @@ struct platform_device u8500_i2c4_device = {
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.resource = u8500_i2c4_resources,
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.num_resources = ARRAY_SIZE(u8500_i2c4_resources),
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};
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static struct resource dma40_resources[] = {
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[0] = {
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.start = U8500_DMA_BASE,
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.end = U8500_DMA_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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.name = "base",
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},
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[1] = {
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.start = U8500_DMA_LCPA_BASE,
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.end = U8500_DMA_LCPA_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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.name = "lcpa",
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},
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[2] = {
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.start = U8500_DMA_LCLA_BASE,
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.end = U8500_DMA_LCLA_BASE + 16 * 1024 - 1,
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.flags = IORESOURCE_MEM,
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.name = "lcla",
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},
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[3] = {
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.start = IRQ_DMA,
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.end = IRQ_DMA,
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.flags = IORESOURCE_IRQ}
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};
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/* Default configuration for physcial memcpy */
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struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
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.channel_type = (STEDMA40_CHANNEL_IN_PHY_MODE |
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STEDMA40_LOW_PRIORITY_CHANNEL |
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STEDMA40_PCHAN_BASIC_MODE),
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.dir = STEDMA40_MEM_TO_MEM,
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.src_info.endianess = STEDMA40_LITTLE_ENDIAN,
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.src_info.data_width = STEDMA40_BYTE_WIDTH,
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.src_info.psize = STEDMA40_PSIZE_PHY_1,
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.dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
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.dst_info.data_width = STEDMA40_BYTE_WIDTH,
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.dst_info.psize = STEDMA40_PSIZE_PHY_1,
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};
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/* Default configuration for logical memcpy */
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struct stedma40_chan_cfg dma40_memcpy_conf_log = {
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.channel_type = (STEDMA40_CHANNEL_IN_LOG_MODE |
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STEDMA40_LOW_PRIORITY_CHANNEL |
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STEDMA40_LCHAN_SRC_LOG_DST_LOG |
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STEDMA40_NO_TIM_FOR_LINK),
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.dir = STEDMA40_MEM_TO_MEM,
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.src_info.endianess = STEDMA40_LITTLE_ENDIAN,
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.src_info.data_width = STEDMA40_BYTE_WIDTH,
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.src_info.psize = STEDMA40_PSIZE_LOG_1,
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.dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
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.dst_info.data_width = STEDMA40_BYTE_WIDTH,
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.dst_info.psize = STEDMA40_PSIZE_LOG_1,
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};
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/*
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* Mapping between destination event lines and physical device address.
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* The event line is tied to a device and therefor the address is constant.
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*/
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static const dma_addr_t dma40_tx_map[STEDMA40_NR_DEV];
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/* Mapping between source event lines and physical device address */
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static const dma_addr_t dma40_rx_map[STEDMA40_NR_DEV];
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/* Reserved event lines for memcpy only */
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static int dma40_memcpy_event[] = {
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STEDMA40_MEMCPY_TX_1,
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STEDMA40_MEMCPY_TX_2,
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STEDMA40_MEMCPY_TX_3,
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STEDMA40_MEMCPY_TX_4,
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};
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static struct stedma40_platform_data dma40_plat_data = {
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.dev_len = STEDMA40_NR_DEV,
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.dev_rx = dma40_rx_map,
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.dev_tx = dma40_tx_map,
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.memcpy = dma40_memcpy_event,
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.memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
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.memcpy_conf_phy = &dma40_memcpy_conf_phy,
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.memcpy_conf_log = &dma40_memcpy_conf_log,
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.llis_per_log = 8,
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};
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struct platform_device u8500_dma40_device = {
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.dev = {
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.platform_data = &dma40_plat_data,
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},
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.name = "dma40",
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.id = 0,
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.num_resources = ARRAY_SIZE(dma40_resources),
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.resource = dma40_resources
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};
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void dma40_u8500ed_fixup(void)
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{
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dma40_plat_data.memcpy = NULL;
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dma40_plat_data.memcpy_len = 0;
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dma40_resources[0].start = U8500_DMA_BASE_ED;
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dma40_resources[0].end = U8500_DMA_BASE_ED + SZ_4K - 1;
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}
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@ -7,6 +7,18 @@
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#ifndef __MACH_DB8500_REGS_H
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#define __MACH_DB8500_REGS_H
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/* Base address and bank offsets for ESRAM */
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#define U8500_ESRAM_BASE 0x40000000
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#define U8500_ESRAM_BANK_SIZE 0x00020000
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#define U8500_ESRAM_BANK0 U8500_ESRAM_BASE
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#define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE)
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#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
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#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
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#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
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/* Use bank 4 for DMA LCLA and LCPA */
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#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4
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#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK4 + 0x4000)
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#define U8500_PER3_BASE 0x80000000
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#define U8500_STM_BASE 0x80100000
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#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
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@ -25,5 +25,8 @@ extern struct platform_device ux500_i2c3_device;
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extern struct platform_device u8500_i2c0_device;
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extern struct platform_device u8500_i2c4_device;
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extern struct platform_device u8500_dma40_device;
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void dma40_u8500ed_fixup(void);
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#endif
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154
arch/arm/mach-ux500/ste-dma40-db8500.h
Normal file
154
arch/arm/mach-ux500/ste-dma40-db8500.h
Normal file
@ -0,0 +1,154 @@
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/*
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* arch/arm/mach-ux500/ste_dma40_db8500.h
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* DB8500-SoC-specific configuration for DMA40
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*
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* Copyright (C) ST-Ericsson 2007-2010
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* License terms: GNU General Public License (GPL) version 2
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* Author: Per Friden <per.friden@stericsson.com>
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* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
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*/
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#ifndef STE_DMA40_DB8500_H
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#define STE_DMA40_DB8500_H
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#define STEDMA40_NR_DEV 64
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enum dma_src_dev_type {
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STEDMA40_DEV_SPI0_RX = 0,
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STEDMA40_DEV_SD_MMC0_RX = 1,
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STEDMA40_DEV_SD_MMC1_RX = 2,
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STEDMA40_DEV_SD_MMC2_RX = 3,
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STEDMA40_DEV_I2C1_RX = 4,
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STEDMA40_DEV_I2C3_RX = 5,
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STEDMA40_DEV_I2C2_RX = 6,
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STEDMA40_DEV_I2C4_RX = 7, /* Only on V1 */
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STEDMA40_DEV_SSP0_RX = 8,
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STEDMA40_DEV_SSP1_RX = 9,
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STEDMA40_DEV_MCDE_RX = 10,
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STEDMA40_DEV_UART2_RX = 11,
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STEDMA40_DEV_UART1_RX = 12,
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STEDMA40_DEV_UART0_RX = 13,
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STEDMA40_DEV_MSP2_RX = 14,
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STEDMA40_DEV_I2C0_RX = 15,
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STEDMA40_DEV_USB_OTG_IEP_8 = 16,
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STEDMA40_DEV_USB_OTG_IEP_1_9 = 17,
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STEDMA40_DEV_USB_OTG_IEP_2_10 = 18,
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STEDMA40_DEV_USB_OTG_IEP_3_11 = 19,
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STEDMA40_DEV_SLIM0_CH0_RX_HSI_RX_CH0 = 20,
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STEDMA40_DEV_SLIM0_CH1_RX_HSI_RX_CH1 = 21,
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STEDMA40_DEV_SLIM0_CH2_RX_HSI_RX_CH2 = 22,
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STEDMA40_DEV_SLIM0_CH3_RX_HSI_RX_CH3 = 23,
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STEDMA40_DEV_SRC_SXA0_RX_TX = 24,
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STEDMA40_DEV_SRC_SXA1_RX_TX = 25,
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STEDMA40_DEV_SRC_SXA2_RX_TX = 26,
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STEDMA40_DEV_SRC_SXA3_RX_TX = 27,
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STEDMA40_DEV_SD_MM2_RX = 28,
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STEDMA40_DEV_SD_MM0_RX = 29,
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STEDMA40_DEV_MSP1_RX = 30,
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/*
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* This channel is either SlimBus or MSP,
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* never both at the same time.
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*/
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STEDMA40_SLIM0_CH0_RX = 31,
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STEDMA40_DEV_MSP0_RX = 31,
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STEDMA40_DEV_SD_MM1_RX = 32,
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STEDMA40_DEV_SPI2_RX = 33,
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STEDMA40_DEV_I2C3_RX2 = 34,
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STEDMA40_DEV_SPI1_RX = 35,
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STEDMA40_DEV_USB_OTG_IEP_4_12 = 36,
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STEDMA40_DEV_USB_OTG_IEP_5_13 = 37,
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STEDMA40_DEV_USB_OTG_IEP_6_14 = 38,
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STEDMA40_DEV_USB_OTG_IEP_7_15 = 39,
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STEDMA40_DEV_SPI3_RX = 40,
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STEDMA40_DEV_SD_MM3_RX = 41,
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STEDMA40_DEV_SD_MM4_RX = 42,
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STEDMA40_DEV_SD_MM5_RX = 43,
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STEDMA40_DEV_SRC_SXA4_RX_TX = 44,
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STEDMA40_DEV_SRC_SXA5_RX_TX = 45,
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STEDMA40_DEV_SRC_SXA6_RX_TX = 46,
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STEDMA40_DEV_SRC_SXA7_RX_TX = 47,
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STEDMA40_DEV_CAC1_RX = 48,
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/* RX channels 49 and 50 are unused */
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STEDMA40_DEV_MSHC_RX = 51,
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STEDMA40_DEV_SLIM1_CH0_RX_HSI_RX_CH4 = 52,
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STEDMA40_DEV_SLIM1_CH1_RX_HSI_RX_CH5 = 53,
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STEDMA40_DEV_SLIM1_CH2_RX_HSI_RX_CH6 = 54,
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STEDMA40_DEV_SLIM1_CH3_RX_HSI_RX_CH7 = 55,
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/* RX channels 56 thru 60 are unused */
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STEDMA40_DEV_CAC0_RX = 61,
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/* RX channels 62 and 63 are unused */
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};
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enum dma_dest_dev_type {
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STEDMA40_DEV_SPI0_TX = 0,
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STEDMA40_DEV_SD_MMC0_TX = 1,
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STEDMA40_DEV_SD_MMC1_TX = 2,
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STEDMA40_DEV_SD_MMC2_TX = 3,
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STEDMA40_DEV_I2C1_TX = 4,
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STEDMA40_DEV_I2C3_TX = 5,
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STEDMA40_DEV_I2C2_TX = 6,
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STEDMA50_DEV_I2C4_TX = 7, /* Only on V1 */
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STEDMA40_DEV_SSP0_TX = 8,
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STEDMA40_DEV_SSP1_TX = 9,
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/* TX channel 10 is unused */
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STEDMA40_DEV_UART2_TX = 11,
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STEDMA40_DEV_UART1_TX = 12,
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STEDMA40_DEV_UART0_TX= 13,
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STEDMA40_DEV_MSP2_TX = 14,
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STEDMA40_DEV_I2C0_TX = 15,
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STEDMA40_DEV_USB_OTG_OEP_8 = 16,
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STEDMA40_DEV_USB_OTG_OEP_1_9 = 17,
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STEDMA40_DEV_USB_OTG_OEP_2_10= 18,
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STEDMA40_DEV_USB_OTG_OEP_3_11 = 19,
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STEDMA40_DEV_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
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STEDMA40_DEV_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
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STEDMA40_DEV_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
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STEDMA40_DEV_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
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STEDMA40_DEV_DST_SXA0_RX_TX = 24,
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STEDMA40_DEV_DST_SXA1_RX_TX = 25,
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STEDMA40_DEV_DST_SXA2_RX_TX = 26,
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STEDMA40_DEV_DST_SXA3_RX_TX = 27,
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STEDMA40_DEV_SD_MM2_TX = 28,
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STEDMA40_DEV_SD_MM0_TX = 29,
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STEDMA40_DEV_MSP1_TX = 30,
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/*
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* This channel is either SlimBus or MSP,
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* never both at the same time.
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*/
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STEDMA40_SLIM0_CH0_TX = 31,
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STEDMA40_DEV_MSP0_TX = 31,
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STEDMA40_DEV_SD_MM1_TX = 32,
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STEDMA40_DEV_SPI2_TX = 33,
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/* Secondary I2C3 channel */
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STEDMA40_DEV_I2C3_TX2 = 34,
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STEDMA40_DEV_SPI1_TX = 35,
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STEDMA40_DEV_USB_OTG_OEP_4_12 = 36,
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STEDMA40_DEV_USB_OTG_OEP_5_13 = 37,
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STEDMA40_DEV_USB_OTG_OEP_6_14 = 38,
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STEDMA40_DEV_USB_OTG_OEP_7_15 = 39,
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STEDMA40_DEV_SPI3_TX = 40,
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STEDMA40_DEV_SD_MM3_TX = 41,
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STEDMA40_DEV_SD_MM4_TX = 42,
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STEDMA40_DEV_SD_MM5_TX = 43,
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STEDMA40_DEV_DST_SXA4_RX_TX = 44,
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STEDMA40_DEV_DST_SXA5_RX_TX = 45,
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STEDMA40_DEV_DST_SXA6_RX_TX = 46,
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STEDMA40_DEV_DST_SXA7_RX_TX = 47,
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STEDMA40_DEV_CAC1_TX = 48,
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STEDMA40_DEV_CAC1_TX_HAC1_TX = 49,
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STEDMA40_DEV_HAC1_TX = 50,
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STEDMA40_MEMXCPY_TX_0 = 51,
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STEDMA40_DEV_SLIM1_CH0_TX_HSI_TX_CH4 = 52,
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STEDMA40_DEV_SLIM1_CH1_TX_HSI_TX_CH5 = 53,
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STEDMA40_DEV_SLIM1_CH2_TX_HSI_TX_CH6 = 54,
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STEDMA40_DEV_SLIM1_CH3_TX_HSI_TX_CH7 = 55,
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STEDMA40_MEMCPY_TX_1 = 56,
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STEDMA40_MEMCPY_TX_2 = 57,
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STEDMA40_MEMCPY_TX_3 = 58,
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STEDMA40_MEMCPY_TX_4 = 59,
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STEDMA40_MEMCPY_TX_5 = 60,
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STEDMA40_DEV_CAC0_TX = 61,
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STEDMA40_DEV_CAC0_TX_HAC0_TX = 62,
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STEDMA40_DEV_HAC0_TX = 63,
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};
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#endif
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