forked from luck/tmp_suning_uos_patched
sh: new sh_mobile mstpcr clocks base code
Add base code to handle new mstpcr clocks. Make sure clock rates propagate. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -516,16 +516,19 @@ static struct clk_ops sh7722_video_clk_ops = {
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static struct clk sh7722_umem_clock = {
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.name = "umem_clk",
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.ops = &sh7722_frqcr_clk_ops,
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.flags = CLK_RATE_PROPAGATES,
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};
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static struct clk sh7722_sh_clock = {
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.name = "sh_clk",
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.ops = &sh7722_frqcr_clk_ops,
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.flags = CLK_RATE_PROPAGATES,
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};
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static struct clk sh7722_peripheral_clock = {
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.name = "peripheral_clk",
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.ops = &sh7722_frqcr_clk_ops,
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.flags = CLK_RATE_PROPAGATES,
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};
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static struct clk sh7722_sdram_clock = {
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@ -533,6 +536,11 @@ static struct clk sh7722_sdram_clock = {
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.ops = &sh7722_frqcr_clk_ops,
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};
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static struct clk sh7722_r_clock = {
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.name = "r_clk",
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.rate = 32768,
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.flags = CLK_RATE_PROPAGATES,
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};
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#ifndef CONFIG_CPU_SUBTYPE_SH7343
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@ -612,9 +620,16 @@ static void sh7722_mstpcr_disable(struct clk *clk)
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sh7722_mstpcr_start_stop(clk, 0);
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}
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static void sh7722_mstpcr_recalc(struct clk *clk)
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{
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if (clk->parent)
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clk->rate = clk->parent->rate;
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}
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static struct clk_ops sh7722_mstpcr_clk_ops = {
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.enable = sh7722_mstpcr_enable,
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.disable = sh7722_mstpcr_disable,
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.recalc = sh7722_mstpcr_recalc,
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};
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#define DECLARE_MSTPCRN(regnr, bitnr, bitstr) \
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@ -664,6 +679,16 @@ static struct clk sh7722_mstpcr[] = {
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DECLARE_MSTPCR(2),
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};
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#define MSTPCR(_name, _parent, regnr, bitnr) \
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{ \
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.name = _name, \
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.arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr), \
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.ops = (void *)_parent, \
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}
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static struct clk sh7722_mstpcr_clocks[] = {
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};
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static struct clk *sh7722_clocks[] = {
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&sh7722_umem_clock,
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&sh7722_sh_clock,
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@ -698,16 +723,28 @@ arch_init_clk_ops(struct clk_ops **ops, int type)
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int __init arch_clk_init(void)
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{
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struct clk *master;
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struct clk *clk;
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int i;
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master = clk_get(NULL, "master_clk");
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clk = clk_get(NULL, "master_clk");
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for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) {
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pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name);
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sh7722_clocks[i]->parent = master;
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sh7722_clocks[i]->parent = clk;
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clk_register(sh7722_clocks[i]);
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}
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clk_put(master);
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clk_put(clk);
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clk_register(&sh7722_r_clock);
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for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr_clocks); i++) {
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pr_debug( "Registering mstpcr clock '%s'\n",
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sh7722_mstpcr_clocks[i].name);
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clk = clk_get(NULL, (void *) sh7722_mstpcr_clocks[i].ops);
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sh7722_mstpcr_clocks[i].parent = clk;
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sh7722_mstpcr_clocks[i].ops = &sh7722_mstpcr_clk_ops;
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clk_register(&sh7722_mstpcr_clocks[i]);
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clk_put(clk);
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}
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for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr); i++) {
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pr_debug( "Registering mstpcr '%s'\n", sh7722_mstpcr[i].name);
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