forked from luck/tmp_suning_uos_patched
amd64_edac: Adjust channel counting to F15h
The only difference is that F10h used to sport ganged DCTs and F15h doesn't so adjust the F10h routine and reuse it. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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@ -1082,15 +1082,13 @@ static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, int cs_mode)
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* Pass back:
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* contents of the DCL0_LOW register
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*/
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static int f10_early_channel_count(struct amd64_pvt *pvt)
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static int f1x_early_channel_count(struct amd64_pvt *pvt)
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{
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int i, j, channels = 0;
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/* If we are in 128 bit mode, then we are using 2 channels */
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if (pvt->dclr0 & F10_WIDTH_128) {
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channels = 2;
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return channels;
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}
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/* On F10h, if we are in 128 bit mode, then we are using 2 channels */
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if (boot_cpu_data.x86 == 0x10 && (pvt->dclr0 & F10_WIDTH_128))
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return 2;
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/*
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* Need to check if in unganged mode: In such, there are 2 channels,
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@ -1540,7 +1538,7 @@ static struct amd64_family_type amd64_family_types[] = {
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.f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP,
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.f3_id = PCI_DEVICE_ID_AMD_10H_NB_MISC,
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.ops = {
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.early_channel_count = f10_early_channel_count,
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.early_channel_count = f1x_early_channel_count,
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.get_error_address = f10_get_error_address,
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.read_dram_ctl_register = f10_read_dram_ctl_register,
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.map_sysaddr_to_csrow = f10_map_sysaddr_to_csrow,
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@ -1551,6 +1549,7 @@ static struct amd64_family_type amd64_family_types[] = {
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[F15_CPUS] = {
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.ctl_name = "F15h",
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.ops = {
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.early_channel_count = f1x_early_channel_count,
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.read_dct_pci_cfg = f15_read_dct_pci_cfg,
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}
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},
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