AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

[PATCH] Fix up TLB flush filter disabling

Browse Source 
I checked with AMD and they requested to only disable it for family 15.
Also disable it for i386 too. And some style fixes.

Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Andi Kleen 2005-09-29 22:05:55 +02:00 committed by Linus Torvalds
parent 5acbc5cb50
commit 7d318d7747
3 changed files with 29 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
arch/i386/kernel/cpu/amd.c
View File

@ -28,6 +28,22 @@ static void __init init_amd(struct cpuinfo_x86 *c)
int mbytes = num_physpages >> (20-PAGE_SHIFT);
int r;
#ifdef CONFIG_SMP
unsigned long value;
/* Disable TLB flush filter by setting HWCR.FFDIS on K8
* bit 6 of msr C001_0015
*
* Errata 63 for SH-B3 steppings
* Errata 122 for all steppings (F+ have it disabled by default)
*/
if (c->x86 == 15) {
rdmsrl(MSR_K7_HWCR, value);
value |= 1 << 6;
wrmsrl(MSR_K7_HWCR, value);
}
#endif
/*
* FIXME: We should handle the K5 here. Set up the write
* range and also turn on MSR 83 bits 4 and 31 (write alloc,

22
arch/x86_64/kernel/setup.c
View File

@ -831,8 +831,6 @@ static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
#endif
}
#define HWCR 0xc0010015
static int __init init_amd(struct cpuinfo_x86 *c)
{
int r;
@ -841,14 +839,18 @@ static int __init init_amd(struct cpuinfo_x86 *c)
#ifdef CONFIG_SMP
unsigned long value;
// Disable TLB flush filter by setting HWCR.FFDIS:
// bit 6 of msr C001_0015
//
// Errata 63 for SH-B3 steppings
// Errata 122 for all(?) steppings
rdmsrl(HWCR, value);
value |= 1 << 6;
wrmsrl(HWCR, value);
/*
* Disable TLB flush filter by setting HWCR.FFDIS on K8
* bit 6 of msr C001_0015
*
* Errata 63 for SH-B3 steppings
* Errata 122 for all steppings (F+ have it disabled by default)
*/
if (c->x86 == 15) {
rdmsrl(MSR_K8_HWCR, value);
value |= 1 << 6;
wrmsrl(MSR_K8_HWCR, value);
}
#endif
/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;

1
include/asm-x86_64/msr.h
View File

@ -234,6 +234,7 @@ static inline unsigned int cpuid_edx(unsigned int op)
#define MSR_K8_TOP_MEM1 0xC001001A
#define MSR_K8_TOP_MEM2 0xC001001D
#define MSR_K8_SYSCFG 0xC0010010
#define MSR_K8_HWCR 0xC0010015
/* K6 MSRs */
#define MSR_K6_EFER 0xC0000080