forked from luck/tmp_suning_uos_patched
clk: at91: allow 24 Mhz clock as input for PLL
The PLL input range needs to be able to allow 24 Mhz crystal as input Update the range accordingly in plla characteristics struct Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lkml.kernel.org/r/1568183622-7858-1-git-send-email-eugen.hristev@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Fixes: c561e41ce4d2 ("clk: at91: add sama5d2 PMC driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -21,7 +21,7 @@ static const struct clk_range plla_outputs[] = {
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};
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static const struct clk_pll_characteristics plla_characteristics = {
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.input = { .min = 12000000, .max = 12000000 },
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.input = { .min = 12000000, .max = 24000000 },
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.num_output = ARRAY_SIZE(plla_outputs),
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.output = plla_outputs,
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.icpll = plla_icpll,
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