forked from luck/tmp_suning_uos_patched
KVM: arm64: enable KVM_CAP_SET_GUEST_DEBUG
Finally advertise the KVM capability for SET_GUEST_DEBUG. Once arm support is added this check can be moved to the common kvm_vm_ioctl_check_extension() code. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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5540546bc9
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834bf88726
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@ -2694,7 +2694,7 @@ The top 16 bits of the control field are architecture specific control
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flags which can include the following:
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- KVM_GUESTDBG_USE_SW_BP: using software breakpoints [x86, arm64]
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- KVM_GUESTDBG_USE_HW_BP: using hardware breakpoints [x86, s390]
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- KVM_GUESTDBG_USE_HW_BP: using hardware breakpoints [x86, s390, arm64]
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- KVM_GUESTDBG_INJECT_DB: inject DB type exception [x86]
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- KVM_GUESTDBG_INJECT_BP: inject BP type exception [x86]
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- KVM_GUESTDBG_EXIT_PENDING: trigger an immediate guest exit [s390]
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@ -2709,6 +2709,11 @@ updated to the correct (supplied) values.
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The second part of the structure is architecture specific and
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typically contains a set of debug registers.
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For arm64 the number of debug registers is implementation defined and
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can be determined by querying the KVM_CAP_GUEST_DEBUG_HW_BPS and
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KVM_CAP_GUEST_DEBUG_HW_WPS capabilities which return a positive number
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indicating the number of supported registers.
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When debug events exit the main run loop with the reason
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KVM_EXIT_DEBUG with the kvm_debug_exit_arch part of the kvm_run
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structure containing architecture specific debug information.
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@ -16,6 +16,8 @@
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#ifndef __ASM_HW_BREAKPOINT_H
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#define __ASM_HW_BREAKPOINT_H
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#include <asm/cputype.h>
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#ifdef __KERNEL__
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struct arch_hw_breakpoint_ctrl {
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@ -132,5 +134,17 @@ static inline void ptrace_hw_copy_thread(struct task_struct *task)
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extern struct pmu perf_ops_bp;
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/* Determine number of BRP registers available. */
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static inline int get_num_brps(void)
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{
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return ((read_cpuid(ID_AA64DFR0_EL1) >> 12) & 0xf) + 1;
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}
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/* Determine number of WRP registers available. */
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static inline int get_num_wrps(void)
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{
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return ((read_cpuid(ID_AA64DFR0_EL1) >> 20) & 0xf) + 1;
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}
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#endif /* __KERNEL__ */
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#endif /* __ASM_BREAKPOINT_H */
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@ -116,13 +116,17 @@ struct kvm_vcpu_arch {
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* debugging the guest from the host and to maintain separate host and
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* guest state during world switches. vcpu_debug_state are the debug
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* registers of the vcpu as the guest sees them. host_debug_state are
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* the host registers which are saved and restored during world switches.
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* the host registers which are saved and restored during
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* world switches. external_debug_state contains the debug
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* values we want to debug the guest. This is set via the
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* KVM_SET_GUEST_DEBUG ioctl.
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*
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* debug_ptr points to the set of debug registers that should be loaded
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* onto the hardware when running the guest.
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*/
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struct kvm_guest_debug_arch *debug_ptr;
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struct kvm_guest_debug_arch vcpu_debug_state;
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struct kvm_guest_debug_arch external_debug_state;
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/* Pointer to host CPU context */
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kvm_cpu_context_t *host_cpu_context;
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@ -48,18 +48,6 @@ static DEFINE_PER_CPU(int, stepping_kernel_bp);
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static int core_num_brps;
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static int core_num_wrps;
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/* Determine number of BRP registers available. */
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static int get_num_brps(void)
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{
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return ((read_cpuid(ID_AA64DFR0_EL1) >> 12) & 0xf) + 1;
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}
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/* Determine number of WRP registers available. */
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static int get_num_wrps(void)
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{
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return ((read_cpuid(ID_AA64DFR0_EL1) >> 20) & 0xf) + 1;
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}
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int hw_breakpoint_slots(int type)
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{
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/*
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@ -105,10 +105,6 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu)
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MDCR_EL2_TDRA |
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MDCR_EL2_TDOSA);
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/* Trap on access to debug registers? */
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if (trap_debug)
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vcpu->arch.mdcr_el2 |= MDCR_EL2_TDA;
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/* Is Guest debugging in effect? */
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if (vcpu->guest_debug) {
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/* Route all software debug exceptions to EL2 */
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@ -143,11 +139,45 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu)
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} else {
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vcpu_sys_reg(vcpu, MDSCR_EL1) &= ~DBG_MDSCR_SS;
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}
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/*
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* HW Breakpoints and watchpoints
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*
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* We simply switch the debug_ptr to point to our new
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* external_debug_state which has been populated by the
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* debug ioctl. The existing KVM_ARM64_DEBUG_DIRTY
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* mechanism ensures the registers are updated on the
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* world switch.
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*/
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if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW) {
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/* Enable breakpoints/watchpoints */
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vcpu_sys_reg(vcpu, MDSCR_EL1) |= DBG_MDSCR_MDE;
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vcpu->arch.debug_ptr = &vcpu->arch.external_debug_state;
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vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
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trap_debug = true;
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}
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}
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BUG_ON(!vcpu->guest_debug &&
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vcpu->arch.debug_ptr != &vcpu->arch.vcpu_debug_state);
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/* Trap debug register access */
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if (trap_debug)
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vcpu->arch.mdcr_el2 |= MDCR_EL2_TDA;
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}
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void kvm_arm_clear_debug(struct kvm_vcpu *vcpu)
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{
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if (vcpu->guest_debug)
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if (vcpu->guest_debug) {
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restore_guest_debug_regs(vcpu);
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/*
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* If we were using HW debug we need to restore the
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* debug_ptr to the guest debug state.
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*/
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if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW)
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kvm_arm_reset_debug_ptr(vcpu);
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}
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}
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@ -334,6 +334,7 @@ int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
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#define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
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KVM_GUESTDBG_USE_SW_BP | \
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KVM_GUESTDBG_USE_HW | \
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KVM_GUESTDBG_SINGLESTEP)
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/**
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@ -354,6 +355,12 @@ int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
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if (dbg->control & KVM_GUESTDBG_ENABLE) {
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vcpu->guest_debug = dbg->control;
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/* Hardware assisted Break and Watch points */
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if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW) {
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vcpu->arch.external_debug_state = dbg->arch;
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}
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} else {
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/* If not enabled clear all flags */
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vcpu->guest_debug = 0;
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@ -103,7 +103,11 @@ static int kvm_handle_guest_debug(struct kvm_vcpu *vcpu, struct kvm_run *run)
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run->debug.arch.hsr = hsr;
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switch (hsr >> ESR_ELx_EC_SHIFT) {
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case ESR_ELx_EC_WATCHPT_LOW:
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run->debug.arch.far = vcpu->arch.fault.far_el2;
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/* fall through */
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case ESR_ELx_EC_SOFTSTP_LOW:
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case ESR_ELx_EC_BREAKPT_LOW:
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case ESR_ELx_EC_BKPT32:
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case ESR_ELx_EC_BRK64:
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break;
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@ -132,6 +136,8 @@ static exit_handle_fn arm_exit_handlers[] = {
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[ESR_ELx_EC_IABT_LOW] = kvm_handle_guest_abort,
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[ESR_ELx_EC_DABT_LOW] = kvm_handle_guest_abort,
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[ESR_ELx_EC_SOFTSTP_LOW]= kvm_handle_guest_debug,
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[ESR_ELx_EC_WATCHPT_LOW]= kvm_handle_guest_debug,
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[ESR_ELx_EC_BREAKPT_LOW]= kvm_handle_guest_debug,
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[ESR_ELx_EC_BKPT32] = kvm_handle_guest_debug,
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[ESR_ELx_EC_BRK64] = kvm_handle_guest_debug,
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};
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@ -22,6 +22,7 @@
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#include <linux/errno.h>
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#include <linux/kvm_host.h>
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#include <linux/kvm.h>
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#include <linux/hw_breakpoint.h>
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#include <kvm/arm_arch_timer.h>
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@ -56,6 +57,12 @@ static bool cpu_has_32bit_el1(void)
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return !!(pfr0 & 0x20);
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}
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/**
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* kvm_arch_dev_ioctl_check_extension
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*
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* We currently assume that the number of HW registers is uniform
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* across all CPUs (see cpuinfo_sanity_check).
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*/
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int kvm_arch_dev_ioctl_check_extension(long ext)
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{
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int r;
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case KVM_CAP_ARM_EL1_32BIT:
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r = cpu_has_32bit_el1();
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break;
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case KVM_CAP_GUEST_DEBUG_HW_BPS:
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r = get_num_brps();
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break;
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case KVM_CAP_GUEST_DEBUG_HW_WPS:
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r = get_num_wrps();
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break;
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case KVM_CAP_SET_GUEST_DEBUG:
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r = 1;
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break;
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default:
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r = 0;
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}
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