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Merge branch 'msm-8960' into msm-core

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* msm-8960:
  msm: Support for the MSM8960 RUMI3 target
  msm: Support for the MSM8960 Simulator target
  msm: Makefile cleanup
  msm: timer: Timer support for MSM8960
  msm: Add MSM 8960 cpu_is check
  msm: irqs-8960: Interrupt map for MSM8960
  msm: Physical offset for MSM8960
  msm: io: I/O register definitions for MSM8960
  msm: Generalize QGIC registers
  msm: Generalize timer register mappings
  msm: Add CPU queries
This commit is contained in:
David Brown 2011-01-26 13:29:22 -08:00
commit 851492c658
16 changed files with 582 additions and 90 deletions
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22
arch/arm/mach-msm/Kconfig
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@ -48,6 +48,16 @@ config ARCH_MSM8X60
select IOMMU_API
select MSM_SCM if SMP
config ARCH_MSM8960
bool "MSM8960"
select ARCH_MSM_SCORPIONMP
select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3)
select ARM_GIC
select CPU_V7
select MSM_V2_TLMM
select MSM_GPIOMUX
select MSM_SCM if SMP
endchoice
config MSM_SOC_REV_A
@ -125,6 +135,18 @@ config MACH_MSM8X60_FFA
help
Support for the Qualcomm MSM8x60 FFA eval board.
config MACH_MSM8960_SIM
depends on ARCH_MSM8960
bool "MSM8960 Simulator"
help
Support for the Qualcomm MSM8960 simulator.
config MACH_MSM8960_RUMI3
depends on ARCH_MSM8960
bool "MSM8960 RUMI3"
help
Support for the Qualcomm MSM8960 RUMI3 emulator.
endmenu
config IOMMU_PGTABLES_L2

23
arch/arm/mach-msm/Makefile
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@ -1,21 +1,16 @@
obj-y += io.o idle.o timer.o
ifndef CONFIG_ARCH_MSM8X60
obj-y += acpuclock-arm11.o
obj-y += dma.o
endif
ifdef CONFIG_MSM_VIC
obj-y += irq-vic.o
else
ifndef CONFIG_ARCH_MSM8X60
obj-y += irq.o
endif
endif
obj-$(CONFIG_MSM_VIC) += irq-vic.o
obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
obj-$(CONFIG_ARCH_MSM7X30) += dma.o
obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o
obj-$(CONFIG_ARCH_MSM8960) += clock-dummy.o
obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
obj-$(CONFIG_MSM_PROC_COMM) += clock.o
obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
obj-$(CONFIG_MSM_SMD) += last_radio_log.o
obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
@ -29,12 +24,16 @@ obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o
obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o
obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
ifdef CONFIG_MSM_V2_TLMM
ifndef CONFIG_ARCH_MSM8960
# TODO: TLMM Mapping issues need to be resolved
obj-y += gpio-v2.o
endif
else
obj-y += gpio.o
endif

68
arch/arm/mach-msm/board-msm8960.c Normal file
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@ -0,0 +1,68 @@
/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>
static void __init msm8960_map_io(void)
{
msm_map_msm8960_io();
}
static void __init msm8960_init_irq(void)
{
unsigned int i;
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
if (machine_is_msm8960_rumi3())
writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
* as they are configured as level, which does not play nice with
* handle_percpu_irq.
*/
for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
set_irq_handler(i, handle_percpu_irq);
}
}
MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
.map_io = msm8960_map_io,
.init_irq = msm8960_init_irq,
.timer = &msm_timer,
MACHINE_END
MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
.map_io = msm8960_map_io,
.init_irq = msm8960_init_irq,
.timer = &msm_timer,
MACHINE_END

54
arch/arm/mach-msm/include/mach/cpu.h Normal file
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@ -0,0 +1,54 @@
/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#ifndef __ARCH_ARM_MACH_MSM_CPU_H__
#define __ARCH_ARM_MACH_MSM_CPU_H__
/* TODO: For now, only one CPU can be compiled at a time. */
#define cpu_is_msm7x01() 0
#define cpu_is_msm7x30() 0
#define cpu_is_qsd8x50() 0
#define cpu_is_msm8x60() 0
#define cpu_is_msm8960() 0
#ifdef CONFIG_ARCH_MSM7X00A
# undef cpu_is_msm7x01
# define cpu_is_msm7x01() 1
#endif
#ifdef CONFIG_ARCH_MSM7X30
# undef cpu_is_msm7x30
# define cpu_is_msm7x30() 1
#endif
#ifdef CONFIG_ARCH_QSD8X50
# undef cpu_is_qsd8x50
# define cpu_is_qsd8x50() 1
#endif
#ifdef CONFIG_ARCH_MSM8X60
# undef cpu_is_msm8x60
# define cpu_is_msm8x60() 1
#endif
#ifdef CONFIG_ARCH_MSM8960
# undef cpu_is_msm8960
# define cpu_is_msm8960() 1
#endif
#endif

1
arch/arm/mach-msm/include/mach/io.h
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@ -29,6 +29,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m
void msm_map_qsd8x50_io(void);
void msm_map_msm7x30_io(void);
void msm_map_msm8x60_io(void);
void msm_map_msm8960_io(void);
extern unsigned int msm_shared_ram_phys;

293
arch/arm/mach-msm/include/mach/irqs-8960.h Normal file
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@ -0,0 +1,293 @@
/* Copyright (c) 2011 Code Aurora Forum. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Code Aurora nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __ASM_ARCH_MSM_IRQS_8960_H
#define __ASM_ARCH_MSM_IRQS_8960_H
/* MSM ACPU Interrupt Numbers */
/* 0-15: STI/SGI (software triggered/generated interrupts)
16-31: PPI (private peripheral interrupts)
32+: SPI (shared peripheral interrupts) */
#define GIC_PPI_START 16
#define GIC_SPI_START 32
#define INT_VGIC (GIC_PPI_START + 0)
#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
#define INT_GP_TIMER_EXP (GIC_PPI_START + 2)
#define INT_GP_TIMER2_EXP (GIC_PPI_START + 3)
#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4)
#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5)
#define AVS_SVICINT (GIC_PPI_START + 6)
#define AVS_SVICINTSWDONE (GIC_PPI_START + 7)
#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8)
#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9)
#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 10)
#define SC_AVSCPUXDOWN (GIC_PPI_START + 11)
#define SC_AVSCPUXUP (GIC_PPI_START + 12)
#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13)
#define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14)
/* PPI 15 is unused */
#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0)
#define SC_SICL2IRPTREQ (GIC_SPI_START + 1)
#define SC_SICL2PERFMONIRPTREQ (GIC_SPI_START + 2)
#define SC_SICAGCIRPTREQ (GIC_SPI_START + 3)
#define TLMM_APCC_DIR_CONN_IRQ_0 (GIC_SPI_START + 4)
#define TLMM_APCC_DIR_CONN_IRQ_1 (GIC_SPI_START + 5)
#define TLMM_APCC_DIR_CONN_IRQ_2 (GIC_SPI_START + 6)
#define TLMM_APCC_DIR_CONN_IRQ_3 (GIC_SPI_START + 7)
#define TLMM_APCC_DIR_CONN_IRQ_4 (GIC_SPI_START + 8)
#define TLMM_APCC_DIR_CONN_IRQ_5 (GIC_SPI_START + 9)
#define TLMM_APCC_DIR_CONN_IRQ_6 (GIC_SPI_START + 10)
#define TLMM_APCC_DIR_CONN_IRQ_7 (GIC_SPI_START + 11)
#define TLMM_APCC_DIR_CONN_IRQ_8 (GIC_SPI_START + 12)
#define TLMM_APCC_DIR_CONN_IRQ_9 (GIC_SPI_START + 13)
#define PM8921_SEC_IRQ_103 (GIC_SPI_START + 14)
#define PM8018_SEC_IRQ_106 (GIC_SPI_START + 15)
#define TLMM_APCC_SUMMARY_IRQ (GIC_SPI_START + 16)
#define SPDM_RT_1_IRQ (GIC_SPI_START + 17)
#define SPDM_DIAG_IRQ (GIC_SPI_START + 18)
#define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19)
#define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20)
#define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21)
#define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22)
#define RPM_APCC_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23)
#define RPM_APCC_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24)
#define RPM_APCC_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25)
#define RPM_APCC_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26)
#define SSBI2_2_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 27)
#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 28)
#define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29)
#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30)
#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31)
#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32)
#define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33)
#define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34)
#define Q6FW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 35)
#define Q6SW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 36)
#define MSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37)
#define MSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38)
#define MSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39)
#define MSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40)
#define MSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41)
#define MSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42)
#define MSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43)
#define MSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44)
#define MSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45)
#define MSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46)
#define VPE_IRQ (GIC_SPI_START + 47)
#define VFE_IRQ (GIC_SPI_START + 48)
#define VCODEC_IRQ (GIC_SPI_START + 49)
#define TV_ENC_IRQ (GIC_SPI_START + 50)
#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51)
#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52)
#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53)
#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54)
#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55)
#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56)
#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57)
#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58)
#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59)
#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60)
#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61)
#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62)
#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63)
#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64)
#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65)
#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66)
#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67)
#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68)
#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69)
#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70)
#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71)
#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72)
#define ROT_IRQ (GIC_SPI_START + 73)
#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74)
#define MDP_IRQ (GIC_SPI_START + 75)
#define JPEGD_IRQ (GIC_SPI_START + 76)
#define JPEG_IRQ (GIC_SPI_START + 77)
#define MMSS_IMEM_IRQ (GIC_SPI_START + 78)
#define HDMI_IRQ (GIC_SPI_START + 79)
#define GFX3D_IRQ (GIC_SPI_START + 80)
#define GFX2D0_IRQ (GIC_SPI_START + 81)
#define DSI1_IRQ (GIC_SPI_START + 82)
#define CSI_1_IRQ (GIC_SPI_START + 83)
#define CSI_0_IRQ (GIC_SPI_START + 84)
#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85)
#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86)
#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87)
#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88)
#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89)
#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90)
#define TOP_IMEM_IRQ (GIC_SPI_START + 91)
#define FABRIC_SYS_IRQ (GIC_SPI_START + 92)
#define FABRIC_APPS_IRQ (GIC_SPI_START + 93)
#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
#define SDC4_BAM_IRQ (GIC_SPI_START + 95)
#define SDC3_BAM_IRQ (GIC_SPI_START + 96)
#define SDC2_BAM_IRQ (GIC_SPI_START + 97)
#define SDC1_BAM_IRQ (GIC_SPI_START + 98)
#define FABRIC_SPS_IRQ (GIC_SPI_START + 99)
#define USB1_HS_IRQ (GIC_SPI_START + 100)
#define SDC4_IRQ_0 (GIC_SPI_START + 101)
#define SDC3_IRQ_0 (GIC_SPI_START + 102)
#define SDC2_IRQ_0 (GIC_SPI_START + 103)
#define SDC1_IRQ_0 (GIC_SPI_START + 104)
#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106)
#define SPS_MTI_0 (GIC_SPI_START + 107)
#define SPS_MTI_1 (GIC_SPI_START + 108)
#define SPS_MTI_2 (GIC_SPI_START + 109)
#define SPS_MTI_3 (GIC_SPI_START + 110)
#define SPS_MTI_4 (GIC_SPI_START + 111)
#define SPS_MTI_5 (GIC_SPI_START + 112)
#define SPS_MTI_6 (GIC_SPI_START + 113)
#define SPS_MTI_7 (GIC_SPI_START + 114)
#define SPS_MTI_8 (GIC_SPI_START + 115)
#define SPS_MTI_9 (GIC_SPI_START + 116)
#define SPS_MTI_10 (GIC_SPI_START + 117)
#define SPS_MTI_11 (GIC_SPI_START + 118)
#define SPS_MTI_12 (GIC_SPI_START + 119)
#define SPS_MTI_13 (GIC_SPI_START + 120)
#define SPS_MTI_14 (GIC_SPI_START + 121)
#define SPS_MTI_15 (GIC_SPI_START + 122)
#define SPS_MTI_16 (GIC_SPI_START + 123)
#define SPS_MTI_17 (GIC_SPI_START + 124)
#define SPS_MTI_18 (GIC_SPI_START + 125)
#define SPS_MTI_19 (GIC_SPI_START + 126)
#define SPS_MTI_20 (GIC_SPI_START + 127)
#define SPS_MTI_21 (GIC_SPI_START + 128)
#define SPS_MTI_22 (GIC_SPI_START + 129)
#define SPS_MTI_23 (GIC_SPI_START + 130)
#define SPS_MTI_24 (GIC_SPI_START + 131)
#define SPS_MTI_25 (GIC_SPI_START + 132)
#define SPS_MTI_26 (GIC_SPI_START + 133)
#define SPS_MTI_27 (GIC_SPI_START + 134)
#define SPS_MTI_28 (GIC_SPI_START + 135)
#define SPS_MTI_29 (GIC_SPI_START + 136)
#define SPS_MTI_30 (GIC_SPI_START + 137)
#define SPS_MTI_31 (GIC_SPI_START + 138)
#define CSIPHY_4LN_IRQ (GIC_SPI_START + 139)
#define CSIPHY_2LN_IRQ (GIC_SPI_START + 140)
#define USB2_IRQ (GIC_SPI_START + 141)
#define USB1_IRQ (GIC_SPI_START + 142)
#define TSSC_SSBI_IRQ (GIC_SPI_START + 143)
#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144)
#define TSSC_PENUP_IRQ (GIC_SPI_START + 145)
#define GSBI1_UARTDM_IRQ (GIC_SPI_START + 146)
#define GSBI1_QUP_IRQ (GIC_SPI_START + 147)
#define GSBI2_UARTDM_IRQ (GIC_SPI_START + 148)
#define GSBI2_QUP_IRQ (GIC_SPI_START + 149)
#define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150)
#define GSBI3_QUP_IRQ (GIC_SPI_START + 151)
#define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152)
#define GSBI4_QUP_IRQ (GIC_SPI_START + 153)
#define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154)
#define GSBI5_QUP_IRQ (GIC_SPI_START + 155)
#define GSBI6_UARTDM_IRQ (GIC_SPI_START + 156)
#define GSBI6_QUP_IRQ (GIC_SPI_START + 157)
#define GSBI7_UARTDM_IRQ (GIC_SPI_START + 158)
#define GSBI7_QUP_IRQ (GIC_SPI_START + 159)
#define GSBI8_UARTDM_IRQ (GIC_SPI_START + 160)
#define GSBI8_QUP_IRQ (GIC_SPI_START + 161)
#define TSIF_TSPP_IRQ (GIC_SPI_START + 162)
#define TSIF_BAM_IRQ (GIC_SPI_START + 163)
#define TSIF2_IRQ (GIC_SPI_START + 164)
#define TSIF1_IRQ (GIC_SPI_START + 165)
#define DSI2_IRQ (GIC_SPI_START + 166)
#define ISPIF_IRQ (GIC_SPI_START + 167)
#define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168)
#define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169)
#define INT_ADM0_SCSS_0_IRQ (GIC_SPI_START + 170)
#define INT_ADM0_SCSS_1_IRQ (GIC_SPI_START + 171)
#define INT_ADM0_SCSS_2_IRQ (GIC_SPI_START + 172)
#define INT_ADM0_SCSS_3_IRQ (GIC_SPI_START + 173)
#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174)
#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175)
#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176)
#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177)
#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178)
#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179)
#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180)
#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181)
#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182)
#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183)
#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184)
#define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185)
#define HSDDRX_EBI1CH1_IRQ (GIC_SPI_START + 186)
#define SDC5_BAM_IRQ (GIC_SPI_START + 187)
#define SDC5_IRQ_0 (GIC_SPI_START + 188)
#define GSBI9_UARTDM_IRQ (GIC_SPI_START + 189)
#define GSBI9_QUP_IRQ (GIC_SPI_START + 190)
#define GSBI10_UARTDM_IRQ (GIC_SPI_START + 191)
#define GSBI10_QUP_IRQ (GIC_SPI_START + 192)
#define GSBI11_UARTDM_IRQ (GIC_SPI_START + 193)
#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
#define GSBI12_UARTDM_IRQ (GIC_SPI_START + 195)
#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
#define RIVA_APSS_LTECOEX_IRQ (GIC_SPI_START + 197)
#define RIVA_APSS_SPARE_IRQ (GIC_SPI_START + 198)
#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ (GIC_SPI_START + 199)
#define RIVA_ASS_RESET_DONE_IRQ (GIC_SPI_START + 200)
#define RIVA_APSS_ASIC_IRQ (GIC_SPI_START + 201)
#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ (GIC_SPI_START + 202)
#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ (GIC_SPI_START + 203)
#define RIVA_APPS_WLAM_SMSM_IRQ (GIC_SPI_START + 204)
#define RIVA_APPS_LOG_CTRL_IRQ (GIC_SPI_START + 205)
#define RIVA_APPS_FM_CTRL_IRQ (GIC_SPI_START + 206)
#define RIVA_APPS_HCI_IRQ (GIC_SPI_START + 207)
#define RIVA_APPS_WLAN_CTRL_IRQ (GIC_SPI_START + 208)
#define A2_BAM_IRQ (GIC_SPI_START + 209)
#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210)
#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211)
#define GFX2D1_IRQ (GIC_SPI_START + 212)
#define PPSS_WDOG_TIMER_IRQ (GIC_SPI_START + 213)
#define SPS_SLIMBUS_CORE_EE0_IRQ (GIC_SPI_START + 214)
#define SPS_SLIMBUS_BAM_EE0_IRQ (GIC_SPI_START + 215)
#define QDSS_ETB_IRQ (GIC_SPI_START + 216)
#define QDSS_CTI2KPSS_CPU1_IRQ (GIC_SPI_START + 217)
#define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218)
#define TLMM_APCC_DIR_CONN_IRQ_16 (GIC_SPI_START + 219)
#define TLMM_APCC_DIR_CONN_IRQ_17 (GIC_SPI_START + 220)
#define TLMM_APCC_DIR_CONN_IRQ_18 (GIC_SPI_START + 221)
#define TLMM_APCC_DIR_CONN_IRQ_19 (GIC_SPI_START + 222)
#define TLMM_APCC_DIR_CONN_IRQ_20 (GIC_SPI_START + 223)
#define TLMM_APCC_DIR_CONN_IRQ_21 (GIC_SPI_START + 224)
#define PM8921_SEC_IRQ_104 (GIC_SPI_START + 225)
#define PM8018_SEC_IRQ_107 (GIC_SPI_START + 226)
/* For now, use the maximum number of interrupts until a pending GIC issue
* is sorted out */
#define NR_MSM_IRQS 1020
#define NR_BOARD_IRQS 0
#define NR_GPIO_IRQS 0
#endif

3
arch/arm/mach-msm/include/mach/irqs.h
View File

@ -26,6 +26,9 @@
#include "sirc.h"
#elif defined(CONFIG_ARCH_MSM8X60)
#include "irqs-8x60.h"
#elif defined(CONFIG_ARCH_MSM8960)
/* TODO: Make these not generic. */
#include "irqs-8960.h"
#elif defined(CONFIG_ARCH_MSM_ARM11)
#include "irqs-7x00.h"
#else

2
arch/arm/mach-msm/include/mach/memory.h
View File

@ -25,6 +25,8 @@
#define PHYS_OFFSET UL(0x00200000)
#elif defined(CONFIG_ARCH_MSM8X60)
#define PHYS_OFFSET UL(0x40200000)
#elif defined(CONFIG_ARCH_MSM8960)
#define PHYS_OFFSET UL(0x40200000)
#else
#define PHYS_OFFSET UL(0x10000000)
#endif

10
arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
View File

@ -1,6 +1,7 @@
/* arch/arm/mach-msm/include/mach/msm_iomap.h
*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
@ -47,13 +48,8 @@
#define MSM_VIC_PHYS 0xC0000000
#define MSM_VIC_SIZE SZ_4K
#define MSM_CSR_BASE IOMEM(0xE0001000)
#define MSM_CSR_PHYS 0xC0100000
#define MSM_CSR_SIZE SZ_4K
#define MSM_GPT_PHYS MSM_CSR_PHYS
#define MSM_GPT_BASE MSM_CSR_BASE
#define MSM_GPT_SIZE SZ_4K
#define MSM7X00_CSR_PHYS 0xC0100000
#define MSM7X00_CSR_SIZE SZ_4K
#define MSM_DMOV_BASE IOMEM(0xE0002000)
#define MSM_DMOV_PHYS 0xA9700000

14
arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
* Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
@ -39,16 +39,8 @@
#define MSM_VIC_PHYS 0xC0080000
#define MSM_VIC_SIZE SZ_4K
#define MSM_CSR_BASE IOMEM(0xE0001000)
#define MSM_CSR_PHYS 0xC0100000
#define MSM_CSR_SIZE SZ_4K
#define MSM_TMR_PHYS MSM_CSR_PHYS
#define MSM_TMR_BASE MSM_CSR_BASE
#define MSM_TMR_SIZE SZ_4K
#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4)
#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
#define MSM7X30_CSR_PHYS 0xC0100000
#define MSM7X30_CSR_SIZE SZ_4K
#define MSM_DMOV_BASE IOMEM(0xE0002000)
#define MSM_DMOV_PHYS 0xAC400000

48
arch/arm/mach-msm/include/mach/msm_iomap-8960.h Normal file
View File

@ -0,0 +1,48 @@
/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* The MSM peripherals are spread all over across 768MB of physical
* space, which makes just having a simple IO_ADDRESS macro to slide
* them into the right virtual location rough. Instead, we will
* provide a master phys->virt mapping for peripherals here.
*
*/
#ifndef __ASM_ARCH_MSM_IOMAP_8960_H
#define __ASM_ARCH_MSM_IOMAP_8960_H
/* Physical base address and size of peripherals.
* Ordered by the virtual base addresses they will be mapped at.
*
* If you add or remove entries here, you'll want to edit the
* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
* changes.
*
*/
#define MSM8960_QGIC_DIST_PHYS 0x02000000
#define MSM8960_QGIC_DIST_SIZE SZ_4K
#define MSM8960_QGIC_CPU_PHYS 0x02002000
#define MSM8960_QGIC_CPU_SIZE SZ_4K
#define MSM8960_TMR_PHYS 0x0200A000
#define MSM8960_TMR_SIZE SZ_4K
#define MSM8960_TMR0_PHYS 0x0208A000
#define MSM8960_TMR0_SIZE SZ_4K
#endif

14
arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
* Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
@ -39,16 +39,8 @@
#define MSM_VIC_PHYS 0xAC000000
#define MSM_VIC_SIZE SZ_4K
#define MSM_CSR_BASE IOMEM(0xE0001000)
#define MSM_CSR_PHYS 0xAC100000
#define MSM_CSR_SIZE SZ_4K
#define MSM_TMR_PHYS MSM_CSR_PHYS
#define MSM_TMR_BASE MSM_CSR_BASE
#define MSM_TMR_SIZE SZ_4K
#define MSM_GPT_BASE MSM_TMR_BASE
#define MSM_DGT_BASE (MSM_TMR_BASE + 0x10)
#define QSD8X50_CSR_PHYS 0xAC100000
#define QSD8X50_CSR_SIZE SZ_4K
#define MSM_DMOV_BASE IOMEM(0xE0002000)
#define MSM_DMOV_PHYS 0xA9700000

25
arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
@ -35,13 +35,11 @@
*
*/
#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000)
#define MSM_QGIC_DIST_PHYS 0x02080000
#define MSM_QGIC_DIST_SIZE SZ_4K
#define MSM8X60_QGIC_DIST_PHYS 0x02080000
#define MSM8X60_QGIC_DIST_SIZE SZ_4K
#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000)
#define MSM_QGIC_CPU_PHYS 0x02081000
#define MSM_QGIC_CPU_SIZE SZ_4K
#define MSM8X60_QGIC_CPU_PHYS 0x02081000
#define MSM8X60_QGIC_CPU_SIZE SZ_4K
#define MSM_ACC_BASE IOMEM(0xF0002000)
#define MSM_ACC_PHYS 0x02001000
@ -58,16 +56,11 @@
#define MSM_SHARED_RAM_BASE IOMEM(0xF0100000)
#define MSM_SHARED_RAM_SIZE SZ_1M
#define MSM_TMR_BASE IOMEM(0xF0200000)
#define MSM_TMR_PHYS 0x02000000
#define MSM_TMR_SIZE SZ_4K
#define MSM8X60_TMR_PHYS 0x02000000
#define MSM8X60_TMR_SIZE SZ_4K
#define MSM_TMR0_BASE IOMEM(0xF0201000)
#define MSM_TMR0_PHYS 0x02040000
#define MSM_TMR0_SIZE SZ_4K
#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4)
#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
#define MSM8X60_TMR0_PHYS 0x02040000
#define MSM8X60_TMR0_SIZE SZ_4K
#define MSM_IOMMU_JPEGD_PHYS 0x07300000
#define MSM_IOMMU_JPEGD_SIZE SZ_1M

9
arch/arm/mach-msm/include/mach/msm_iomap.h
View File

@ -1,6 +1,6 @@
/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
@ -53,6 +53,13 @@
#include "msm_iomap-7x00.h"
#endif
#include "msm_iomap-8960.h"
/* Virtual addressses shared across all MSM targets. */
#define MSM_CSR_BASE IOMEM(0xE0001000)
#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000)
#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000)
#define MSM_TMR_BASE IOMEM(0xF0200000)
#define MSM_TMR0_BASE IOMEM(0xF0201000)
#endif

40
arch/arm/mach-msm/io.c
View File

@ -3,7 +3,7 @@
* MSM7K, QSD io support
*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
@ -28,18 +28,20 @@
#include <mach/board.h>
#define MSM_DEVICE(name) { \
#define MSM_CHIP_DEVICE(name, chip) { \
.virtual = (unsigned long) MSM_##name##_BASE, \
.pfn = __phys_to_pfn(MSM_##name##_PHYS), \
.length = MSM_##name##_SIZE, \
.pfn = __phys_to_pfn(chip##_##name##_PHYS), \
.length = chip##_##name##_SIZE, \
.type = MT_DEVICE_NONSHARED, \
}
#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
|| defined(CONFIG_ARCH_MSM7X25)
static struct map_desc msm_io_desc[] __initdata = {
MSM_DEVICE(VIC),
MSM_DEVICE(CSR),
MSM_CHIP_DEVICE(CSR, MSM7X00),
MSM_DEVICE(GPT),
MSM_DEVICE(DMOV),
MSM_DEVICE(GPIO1),
@ -73,8 +75,7 @@ void __init msm_map_common_io(void)
#ifdef CONFIG_ARCH_QSD8X50
static struct map_desc qsd8x50_io_desc[] __initdata = {
MSM_DEVICE(VIC),
MSM_DEVICE(CSR),
MSM_DEVICE(TMR),
MSM_CHIP_DEVICE(CSR, QSD8X50),
MSM_DEVICE(DMOV),
MSM_DEVICE(GPIO1),
MSM_DEVICE(GPIO2),
@ -102,10 +103,10 @@ void __init msm_map_qsd8x50_io(void)
#ifdef CONFIG_ARCH_MSM8X60
static struct map_desc msm8x60_io_desc[] __initdata = {
MSM_DEVICE(QGIC_DIST),
MSM_DEVICE(QGIC_CPU),
MSM_DEVICE(TMR),
MSM_DEVICE(TMR0),
MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60),
MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60),
MSM_CHIP_DEVICE(TMR, MSM8X60),
MSM_CHIP_DEVICE(TMR0, MSM8X60),
MSM_DEVICE(ACC),
MSM_DEVICE(GCC),
};
@ -116,11 +117,24 @@ void __init msm_map_msm8x60_io(void)
}
#endif /* CONFIG_ARCH_MSM8X60 */
#ifdef CONFIG_ARCH_MSM8960
static struct map_desc msm8960_io_desc[] __initdata = {
MSM_CHIP_DEVICE(QGIC_DIST, MSM8960),
MSM_CHIP_DEVICE(QGIC_CPU, MSM8960),
MSM_CHIP_DEVICE(TMR, MSM8960),
MSM_CHIP_DEVICE(TMR0, MSM8960),
};
void __init msm_map_msm8960_io(void)
{
iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc));
}
#endif /* CONFIG_ARCH_MSM8960 */
#ifdef CONFIG_ARCH_MSM7X30
static struct map_desc msm7x30_io_desc[] __initdata = {
MSM_DEVICE(VIC),
MSM_DEVICE(CSR),
MSM_DEVICE(TMR),
MSM_CHIP_DEVICE(CSR, MSM7X30),
MSM_DEVICE(DMOV),
MSM_DEVICE(GPIO1),
MSM_DEVICE(GPIO2),

46
arch/arm/mach-msm/timer.c
View File

@ -24,10 +24,7 @@
#include <asm/mach/time.h>
#include <mach/msm_iomap.h>
#ifndef MSM_DGT_BASE
#define MSM_DGT_BASE (MSM_GPT_BASE + 0x10)
#endif
#include <mach/cpu.h>
#define TIMER_MATCH_VAL 0x0000
#define TIMER_COUNT_VAL 0x0004
@ -52,18 +49,14 @@ enum timer_location {
GLOBAL_TIMER = 1,
};
#ifdef MSM_TMR0_BASE
#define MSM_TMR_GLOBAL (MSM_TMR0_BASE - MSM_TMR_BASE)
#else
#define MSM_TMR_GLOBAL 0
#endif
#define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
/* TODO: Remove these ifdefs */
#if defined(CONFIG_ARCH_QSD8X50)
#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
#define MSM_DGT_SHIFT (0)
#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60)
#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \
defined(CONFIG_ARCH_MSM8960)
#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
#define MSM_DGT_SHIFT (0)
#else
@ -177,11 +170,7 @@ static struct msm_clock msm_clocks[] = {
.dev_id = &msm_clocks[0].clockevent,
.irq = INT_GP_TIMER_EXP
},
.regbase = MSM_GPT_BASE,
.freq = GPT_HZ,
.local_counter = MSM_GPT_BASE + TIMER_COUNT_VAL,
.global_counter = MSM_GPT_BASE + TIMER_COUNT_VAL +
MSM_TMR_GLOBAL,
},
[MSM_CLOCK_DGT] = {
.clockevent = {
@ -206,12 +195,8 @@ static struct msm_clock msm_clocks[] = {
.dev_id = &msm_clocks[1].clockevent,
.irq = INT_DEBUG_TIMER_EXP
},
.regbase = MSM_DGT_BASE,
.freq = DGT_HZ >> MSM_DGT_SHIFT,
.shift = MSM_DGT_SHIFT,
.local_counter = MSM_DGT_BASE + TIMER_COUNT_VAL,
.global_counter = MSM_DGT_BASE + TIMER_COUNT_VAL +
MSM_TMR_GLOBAL,
}
};
@ -219,6 +204,25 @@ static void __init msm_timer_init(void)
{
int i;
int res;
int global_offset = 0;
if (cpu_is_msm7x01()) {
msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
} else if (cpu_is_msm7x30()) {
msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
} else if (cpu_is_qsd8x50()) {
msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
} else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
/* Use CPU0's timer as the global timer. */
global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
} else
BUG();
#ifdef CONFIG_ARCH_MSM_SCORPIONMP
writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
@ -228,6 +232,10 @@ static void __init msm_timer_init(void)
struct msm_clock *clock = &msm_clocks[i];
struct clock_event_device *ce = &clock->clockevent;
struct clocksource *cs = &clock->clocksource;
clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
clock->global_counter = clock->local_counter + global_offset;
writel(0, clock->regbase + TIMER_ENABLE);
writel(0, clock->regbase + TIMER_CLEAR);
writel(~0, clock->regbase + TIMER_MATCH_VAL);