forked from luck/tmp_suning_uos_patched
ASoC: optimize init sequence of Freescale MPC8610 sound drivers
In the Freescale MPC8610 sound drivers, relocate all code from the _prepare functions into the corresponding _hw_params functions. These drivers assumed that the sample size is known in the _prepare function and not in the _hw_params function, but this is not true. Move the code in fsl_dma_prepare() into fsl_dma_hw_param(). Create fsl_ssi_hw_params() and move the code from fsl_ssi_prepare() into it. Turn off snooping for DMA operations to/from I/O registers, since that's not necessary. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Timur Tabi
Mark Brown
parent
8836c273e4
commit
85ef2375ef
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@ -464,11 +464,7 @@ static int fsl_dma_open(struct snd_pcm_substream *substream)
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sizeof(struct fsl_dma_link_descriptor);
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for (i = 0; i < NUM_DMA_LINKS; i++) {
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struct fsl_dma_link_descriptor *link = &dma_private->link[i];
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link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
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link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
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link->next = cpu_to_be64(temp_link);
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dma_private->link[i].next = cpu_to_be64(temp_link);
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temp_link += sizeof(struct fsl_dma_link_descriptor);
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}
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@ -525,79 +521,9 @@ static int fsl_dma_open(struct snd_pcm_substream *substream)
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* This function obtains hardware parameters about the opened stream and
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* programs the DMA controller accordingly.
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*
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* Note that due to a quirk of the SSI's STX register, the target address
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* for the DMA operations depends on the sample size. So we don't program
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* the dest_addr (for playback -- source_addr for capture) fields in the
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* link descriptors here. We do that in fsl_dma_prepare()
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*/
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static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *hw_params)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct fsl_dma_private *dma_private = runtime->private_data;
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dma_addr_t temp_addr; /* Pointer to next period */
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unsigned int i;
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/* Get all the parameters we need */
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size_t buffer_size = params_buffer_bytes(hw_params);
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size_t period_size = params_period_bytes(hw_params);
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/* Initialize our DMA tracking variables */
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dma_private->period_size = period_size;
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dma_private->num_periods = params_periods(hw_params);
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dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
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dma_private->dma_buf_next = dma_private->dma_buf_phys +
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(NUM_DMA_LINKS * period_size);
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if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
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dma_private->dma_buf_next = dma_private->dma_buf_phys;
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/*
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* The actual address in STX0 (destination for playback, source for
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* capture) is based on the sample size, but we don't know the sample
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* size in this function, so we'll have to adjust that later. See
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* comments in fsl_dma_prepare().
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*
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* The DMA controller does not have a cache, so the CPU does not
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* need to tell it to flush its cache. However, the DMA
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* controller does need to tell the CPU to flush its cache.
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* That's what the SNOOP bit does.
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*
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* Also, even though the DMA controller supports 36-bit addressing, for
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* simplicity we currently support only 32-bit addresses for the audio
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* buffer itself.
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*/
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temp_addr = substream->dma_buffer.addr;
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for (i = 0; i < NUM_DMA_LINKS; i++) {
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struct fsl_dma_link_descriptor *link = &dma_private->link[i];
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link->count = cpu_to_be32(period_size);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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link->source_addr = cpu_to_be32(temp_addr);
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else
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link->dest_addr = cpu_to_be32(temp_addr);
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temp_addr += period_size;
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}
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return 0;
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}
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/**
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* fsl_dma_prepare - prepare the DMA registers for playback.
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*
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* This function is called after the specifics of the audio data are known,
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* i.e. snd_pcm_runtime is initialized.
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*
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* In this function, we finish programming the registers of the DMA
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* controller that are dependent on the sample size.
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*
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* One of the drawbacks with big-endian is that when copying integers of
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* different sizes to a fixed-sized register, the address to which the
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* integer must be copied is dependent on the size of the integer.
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* One drawback of big-endian is that when copying integers of different
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* sizes to a fixed-sized register, the address to which the integer must be
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* copied is dependent on the size of the integer.
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*
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* For example, if P is the address of a 32-bit register, and X is a 32-bit
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* integer, then X should be copied to address P. However, if X is a 16-bit
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@ -613,22 +539,58 @@ static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
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* and 8 bytes at a time). So we do not support packed 24-bit samples.
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* 24-bit data must be padded to 32 bits.
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*/
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static int fsl_dma_prepare(struct snd_pcm_substream *substream)
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static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *hw_params)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct fsl_dma_private *dma_private = runtime->private_data;
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struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
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u32 mr;
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unsigned int i;
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dma_addr_t ssi_sxx_phys; /* Bus address of SSI STX register */
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unsigned int frame_size; /* Number of bytes per frame */
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ssi_sxx_phys = dma_private->ssi_sxx_phys;
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/* Number of bits per sample */
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unsigned int sample_size =
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snd_pcm_format_physical_width(params_format(hw_params));
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/* Number of bytes per frame */
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unsigned int frame_size = 2 * (sample_size / 8);
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/* Bus address of SSI STX register */
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dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys;
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/* Size of the DMA buffer, in bytes */
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size_t buffer_size = params_buffer_bytes(hw_params);
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/* Number of bytes per period */
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size_t period_size = params_period_bytes(hw_params);
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/* Pointer to next period */
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dma_addr_t temp_addr = substream->dma_buffer.addr;
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/* Pointer to DMA controller */
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struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
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u32 mr; /* DMA Mode Register */
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unsigned int i;
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/* Initialize our DMA tracking variables */
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dma_private->period_size = period_size;
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dma_private->num_periods = params_periods(hw_params);
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dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
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dma_private->dma_buf_next = dma_private->dma_buf_phys +
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(NUM_DMA_LINKS * period_size);
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if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
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/* This happens if the number of periods == NUM_DMA_LINKS */
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dma_private->dma_buf_next = dma_private->dma_buf_phys;
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mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK |
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CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK);
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switch (runtime->sample_bits) {
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/* Due to a quirk of the SSI's STX register, the target address
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* for the DMA operations depends on the sample size. So we calculate
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* that offset here. While we're at it, also tell the DMA controller
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* how much data to transfer per sample.
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*/
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switch (sample_size) {
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case 8:
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mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1;
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ssi_sxx_phys += 3;
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@ -641,12 +603,12 @@ static int fsl_dma_prepare(struct snd_pcm_substream *substream)
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mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4;
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break;
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default:
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/* We should never get here */
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dev_err(substream->pcm->card->dev,
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"unsupported sample size %u\n", runtime->sample_bits);
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"unsupported sample size %u\n", sample_size);
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return -EINVAL;
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}
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frame_size = runtime->frame_bits / 8;
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/*
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* BWC should always be a multiple of the frame size. BWC determines
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* how many bytes are sent/received before the DMA controller checks the
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@ -655,7 +617,6 @@ static int fsl_dma_prepare(struct snd_pcm_substream *substream)
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* capture, the receive FIFO is triggered when it contains one frame, so
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* we want to receive one frame at a time.
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*/
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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mr |= CCSR_DMA_MR_BWC(2 * frame_size);
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else
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@ -663,16 +624,48 @@ static int fsl_dma_prepare(struct snd_pcm_substream *substream)
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out_be32(&dma_channel->mr, mr);
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/*
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* Program the address of the DMA transfer to/from the SSI.
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*/
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for (i = 0; i < NUM_DMA_LINKS; i++) {
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struct fsl_dma_link_descriptor *link = &dma_private->link[i];
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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link->count = cpu_to_be32(period_size);
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/* Even though the DMA controller supports 36-bit addressing,
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* for simplicity we allow only 32-bit addresses for the audio
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* buffer itself. This was enforced in fsl_dma_new() with the
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* DMA mask.
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*
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* The snoop bit tells the DMA controller whether it should tell
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* the ECM to snoop during a read or write to an address. For
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* audio, we use DMA to transfer data between memory and an I/O
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* device (the SSI's STX0 or SRX0 register). Snooping is only
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* needed if there is a cache, so we need to snoop memory
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* addresses only. For playback, that means we snoop the source
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* but not the destination. For capture, we snoop the
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* destination but not the source.
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*
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* Note that failing to snoop properly is unlikely to cause
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* cache incoherency if the period size is larger than the
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* size of L1 cache. This is because filling in one period will
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* flush out the data for the previous period. So if you
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* increased period_bytes_min to a large enough size, you might
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* get more performance by not snooping, and you'll still be
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* okay.
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*/
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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link->source_addr = cpu_to_be32(temp_addr);
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link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
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link->dest_addr = cpu_to_be32(ssi_sxx_phys);
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else
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link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP);
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} else {
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link->source_addr = cpu_to_be32(ssi_sxx_phys);
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link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP);
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link->dest_addr = cpu_to_be32(temp_addr);
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link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
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}
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temp_addr += period_size;
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}
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return 0;
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@ -808,7 +801,6 @@ static struct snd_pcm_ops fsl_dma_ops = {
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.ioctl = snd_pcm_lib_ioctl,
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.hw_params = fsl_dma_hw_params,
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.hw_free = fsl_dma_hw_free,
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.prepare = fsl_dma_prepare,
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.pointer = fsl_dma_pointer,
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};
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@ -400,7 +400,7 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
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}
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/**
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* fsl_ssi_prepare: prepare the SSI.
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* fsl_ssi_hw_params - program the sample size
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*
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* Most of the SSI registers have been programmed in the startup function,
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* but the word length must be programmed here. Unfortunately, programming
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@ -412,20 +412,19 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
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* Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
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* clock master.
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*/
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static int fsl_ssi_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct fsl_ssi_private *ssi_private = rtd->dai->cpu_dai->private_data;
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struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
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struct fsl_ssi_private *ssi_private = cpu_dai->private_data;
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if (substream == ssi_private->first_stream) {
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struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
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unsigned int sample_size =
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snd_pcm_format_width(params_format(hw_params));
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u32 wl;
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/* The SSI should always be disabled at this points (SSIEN=0) */
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wl = CCSR_SSI_SxCCR_WL(snd_pcm_format_width(runtime->format));
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wl = CCSR_SSI_SxCCR_WL(sample_size);
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/* In synchronous mode, the SSI uses STCCR for capture */
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clrsetbits_be32(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
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@ -579,7 +578,7 @@ static struct snd_soc_dai fsl_ssi_dai_template = {
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},
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.ops = {
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.startup = fsl_ssi_startup,
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.prepare = fsl_ssi_prepare,
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.hw_params = fsl_ssi_hw_params,
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.shutdown = fsl_ssi_shutdown,
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.trigger = fsl_ssi_trigger,
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.set_sysclk = fsl_ssi_set_sysclk,
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