forked from luck/tmp_suning_uos_patched
Merge branch 'omap/dt' into next/dt
This commit is contained in:
commit
86c1e5a74a
Documentation/devicetree/bindings/arm/omap
arch/arm
boot/dts
include/asm
mach-omap1
mach-omap2
KconfigMakefileboard-2430sdp.cboard-3430sdp.cboard-3630sdp.cboard-4430sdp.cboard-am3517crane.cboard-am3517evm.cboard-apollon.cboard-cm-t35.cboard-cm-t3517.cboard-devkit8000.cboard-flash.cboard-flash.hboard-generic.cboard-h4.cboard-igep0020.cboard-ldp.cboard-n8x0.cboard-omap3beagle.cboard-omap3evm.cboard-omap3logic.cboard-omap3pandora.cboard-omap3stalker.cboard-omap3touchbook.cboard-omap4panda.cboard-overo.cboard-rm680.cboard-rx51.cboard-ti8168evm.cboard-zoom.cclock2420_data.cclock2430_data.cclock3xxx_data.cclock44xx_data.cclockdomain.cclockdomain.hclockdomain2xxx_3xxx.cclockdomain44xx.cclockdomains2420_data.cclockdomains2430_data.cclockdomains2xxx_3xxx_data.cclockdomains3xxx_data.cclockdomains44xx_data.ccommon.cdevices.cdisplay.cdma.cgpio.chsmmc.chwspinlock.cid.cio.cirq.cmcbsp.comap_hwmod.comap_hwmod_2420_data.comap_hwmod_2430_data.comap_hwmod_3xxx_data.comap_hwmod_44xx_data.comap_l3_noc.comap_l3_noc.homap_l3_smx.comap_l3_smx.homap_twl.copp.cpm.cpm24xx.cpm34xx.cpowerdomain-common.cpowerdomain.cpowerdomain.hpowerdomain2xxx_3xxx.cpowerdomains2xxx_3xxx_data.cpowerdomains2xxx_data.cpowerdomains3xxx_data.cpowerdomains44xx_data.cprm2xxx_3xxx.cprm2xxx_3xxx.hprm44xx.cprm44xx.hserial.csmartreflex-class3.csmartreflex.csr_device.ctimer.c
14
Documentation/devicetree/bindings/arm/omap/dsp.txt
Normal file
14
Documentation/devicetree/bindings/arm/omap/dsp.txt
Normal file
@ -0,0 +1,14 @@
|
||||
* TI - DSP (Digital Signal Processor)
|
||||
|
||||
TI DSP included in OMAP SoC
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "ti,omap3-c64" for OMAP3 & 4
|
||||
- ti,hwmods: "dsp"
|
||||
|
||||
Examples:
|
||||
|
||||
dsp {
|
||||
compatible = "ti,omap3-c64";
|
||||
ti,hwmods = "dsp";
|
||||
};
|
19
Documentation/devicetree/bindings/arm/omap/iva.txt
Normal file
19
Documentation/devicetree/bindings/arm/omap/iva.txt
Normal file
@ -0,0 +1,19 @@
|
||||
* TI - IVA (Imaging and Video Accelerator) subsystem
|
||||
|
||||
The IVA contain various audio, video or imaging HW accelerator
|
||||
depending of the version.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be:
|
||||
- "ti,ivahd" for OMAP4
|
||||
- "ti,iva2.2" for OMAP3
|
||||
- "ti,iva2.1" for OMAP2430
|
||||
- "ti,iva1" for OMAP2420
|
||||
- ti,hwmods: "iva"
|
||||
|
||||
Examples:
|
||||
|
||||
iva {
|
||||
compatible = "ti,ivahd", "ti,iva";
|
||||
ti,hwmods = "iva";
|
||||
};
|
19
Documentation/devicetree/bindings/arm/omap/l3-noc.txt
Normal file
19
Documentation/devicetree/bindings/arm/omap/l3-noc.txt
Normal file
@ -0,0 +1,19 @@
|
||||
* TI - L3 Network On Chip (NoC)
|
||||
|
||||
This version is an implementation of the generic NoC IP
|
||||
provided by Arteris.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
|
||||
Should be "ti,omap4-l3-noc" for OMAP4 family
|
||||
- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.
|
||||
|
||||
Examples:
|
||||
|
||||
ocp {
|
||||
compatible = "ti,omap4-l3-noc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
|
||||
};
|
27
Documentation/devicetree/bindings/arm/omap/mpu.txt
Normal file
27
Documentation/devicetree/bindings/arm/omap/mpu.txt
Normal file
@ -0,0 +1,27 @@
|
||||
* TI - MPU (Main Processor Unit) subsystem
|
||||
|
||||
The MPU subsystem contain one or several ARM cores
|
||||
depending of the version.
|
||||
The MPU contain CPUs, GIC, L2 cache and a local PRCM.
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "ti,omap3-mpu" for OMAP3
|
||||
Should be "ti,omap4-mpu" for OMAP4
|
||||
- ti,hwmods: "mpu"
|
||||
|
||||
Examples:
|
||||
|
||||
- For an OMAP4 SMP system:
|
||||
|
||||
mpu {
|
||||
compatible = "ti,omap4-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
};
|
||||
|
||||
|
||||
- For an OMAP3 monocore system:
|
||||
|
||||
mpu {
|
||||
compatible = "ti,omap3-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
};
|
43
Documentation/devicetree/bindings/arm/omap/omap.txt
Normal file
43
Documentation/devicetree/bindings/arm/omap/omap.txt
Normal file
@ -0,0 +1,43 @@
|
||||
* Texas Instruments OMAP
|
||||
|
||||
OMAP is currently using a static file per SoC family to describe the
|
||||
IPs present in the SoC.
|
||||
On top of that an omap_device is created to extend the platform_device
|
||||
capabilities and to allow binding with one or several hwmods.
|
||||
The hwmods will contain all the information to build the device:
|
||||
adresse range, irq lines, dma lines, interconnect, PRCM register,
|
||||
clock domain, input clocks.
|
||||
For the moment just point to the existing hwmod, the next step will be
|
||||
to move data from hwmod to device-tree representation.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: Every devices present in OMAP SoC should be in the
|
||||
form: "ti,XXX"
|
||||
- ti,hwmods: list of hwmod names (ascii strings), that comes from the OMAP
|
||||
HW documentation, attached to a device. Must contain at least
|
||||
one hwmod.
|
||||
|
||||
Optional properties:
|
||||
- ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
|
||||
during suspend.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
spinlock@1 {
|
||||
compatible = "ti,omap4-spinlock";
|
||||
ti,hwmods = "spinlock";
|
||||
};
|
||||
|
||||
|
||||
Boards:
|
||||
|
||||
- OMAP3 BeagleBoard : Low cost community board
|
||||
compatible = "ti,omap3-beagle", "ti,omap3"
|
||||
|
||||
- OMAP4 SDP : Software Developement Board
|
||||
compatible = "ti,omap4-sdp", "ti,omap4430"
|
||||
|
||||
- OMAP4 PandaBoard : Low cost community board
|
||||
compatible = "ti,omap4-panda", "ti,omap4430"
|
29
arch/arm/boot/dts/omap3-beagle.dts
Normal file
29
arch/arm/boot/dts/omap3-beagle.dts
Normal file
@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap3.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP3 BeagleBoard";
|
||||
compatible = "ti,omap3-beagle", "ti,omap3";
|
||||
|
||||
/*
|
||||
* Since the initial device tree board file does not create any
|
||||
* devices (MMC, network...), the only way to boot is to provide a
|
||||
* ramdisk.
|
||||
*/
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
};
|
63
arch/arm/boot/dts/omap3.dtsi
Normal file
63
arch/arm/boot/dts/omap3.dtsi
Normal file
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Device Tree Source for OMAP3 SoC
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,omap3430", "ti,omap3";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a8";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is uses for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
compatible = "ti,omap-infra";
|
||||
mpu {
|
||||
compatible = "ti,omap3-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
};
|
||||
|
||||
iva {
|
||||
compatible = "ti,iva2.2";
|
||||
ti,hwmods = "iva";
|
||||
|
||||
dsp {
|
||||
compatible = "ti,omap3-c64";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX: Use a flat representation of the OMAP3 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
* Since that will not bring real advantage to represent that in DT for
|
||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
*/
|
||||
ocp {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "l3_main";
|
||||
|
||||
intc: interrupt-controller@1 {
|
||||
compatible = "ti,omap3-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
29
arch/arm/boot/dts/omap4-panda.dts
Normal file
29
arch/arm/boot/dts/omap4-panda.dts
Normal file
@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap4.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP4 PandaBoard";
|
||||
compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
|
||||
|
||||
/*
|
||||
* Since the initial device tree board file does not create any
|
||||
* devices (MMC, network...), the only way to boot is to provide a
|
||||
* ramdisk.
|
||||
*/
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
};
|
29
arch/arm/boot/dts/omap4-sdp.dts
Normal file
29
arch/arm/boot/dts/omap4-sdp.dts
Normal file
@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "omap4.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP4 SDP board";
|
||||
compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
|
||||
|
||||
/*
|
||||
* Since the initial device tree board file does not create any
|
||||
* devices (MMC, network...), the only way to boot is to provide a
|
||||
* ramdisk.
|
||||
*/
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
};
|
103
arch/arm/boot/dts/omap4.dtsi
Normal file
103
arch/arm/boot/dts/omap4.dtsi
Normal file
@ -0,0 +1,103 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Carveout for multimedia usecases
|
||||
* It should be the last 48MB of the first 512MB memory part
|
||||
* In theory, it should not even exist. That zone should be reserved
|
||||
* dynamically during the .reserve callback.
|
||||
*/
|
||||
/memreserve/ 0x9d000000 0x03000000;
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,omap4430", "ti,omap4";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
};
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
};
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a9";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is uses for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
compatible = "ti,omap-infra";
|
||||
mpu {
|
||||
compatible = "ti,omap4-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
};
|
||||
|
||||
dsp {
|
||||
compatible = "ti,omap3-c64";
|
||||
ti,hwmods = "dsp";
|
||||
};
|
||||
|
||||
iva {
|
||||
compatible = "ti,ivahd";
|
||||
ti,hwmods = "iva";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX: Use a flat representation of the OMAP4 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
*
|
||||
* MPU -+-- MPU_PRIVATE - GIC, L2
|
||||
* |
|
||||
* +----------------+----------+
|
||||
* | | |
|
||||
* + +- EMIF - DDR |
|
||||
* | | |
|
||||
* | + +--------+
|
||||
* | | |
|
||||
* | +- L4_ABE - AESS, MCBSP, TIMERs...
|
||||
* | |
|
||||
* +- L3_MAIN --+- L4_CORE - IPs...
|
||||
* |
|
||||
* +- L4_PER - IPs...
|
||||
* |
|
||||
* +- L4_CFG -+- L4_WKUP - IPs...
|
||||
* | |
|
||||
* | +- IPs...
|
||||
* +- IPU ----+
|
||||
* | |
|
||||
* +- DSP ----+
|
||||
* | |
|
||||
* +- DSS ----+
|
||||
*
|
||||
* Since that will not bring real advantage to represent that in DT for
|
||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
*/
|
||||
ocp {
|
||||
compatible = "ti,omap4-l3-noc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
|
||||
|
||||
gic: interrupt-controller@48241000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x48241000 0x1000>,
|
||||
<0x48240100 0x0100>;
|
||||
};
|
||||
};
|
||||
};
|
@ -12,7 +12,12 @@ struct dev_archdata {
|
||||
#endif
|
||||
};
|
||||
|
||||
struct omap_device;
|
||||
|
||||
struct pdev_archdata {
|
||||
#ifdef CONFIG_ARCH_OMAP
|
||||
struct omap_device *od;
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif
|
||||
|
@ -4,7 +4,7 @@
|
||||
|
||||
# Common support
|
||||
obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o
|
||||
obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o
|
||||
obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o
|
||||
|
||||
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
|
||||
|
||||
|
@ -31,6 +31,7 @@
|
||||
static int dsp_use;
|
||||
static struct clk *api_clk;
|
||||
static struct clk *dsp_clk;
|
||||
static struct platform_device **omap_mcbsp_devices;
|
||||
|
||||
static void omap1_mcbsp_request(unsigned int id)
|
||||
{
|
||||
@ -78,6 +79,17 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
|
||||
.free = omap1_mcbsp_free,
|
||||
};
|
||||
|
||||
#define OMAP7XX_MCBSP1_BASE 0xfffb1000
|
||||
#define OMAP7XX_MCBSP2_BASE 0xfffb1800
|
||||
|
||||
#define OMAP1510_MCBSP1_BASE 0xe1011800
|
||||
#define OMAP1510_MCBSP2_BASE 0xfffb1000
|
||||
#define OMAP1510_MCBSP3_BASE 0xe1017000
|
||||
|
||||
#define OMAP1610_MCBSP1_BASE 0xe1011800
|
||||
#define OMAP1610_MCBSP2_BASE 0xfffb1000
|
||||
#define OMAP1610_MCBSP3_BASE 0xe1017000
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
||||
struct resource omap7xx_mcbsp_res[][6] = {
|
||||
{
|
||||
@ -369,6 +381,39 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
|
||||
#define OMAP16XX_MCBSP_COUNT 0
|
||||
#endif
|
||||
|
||||
static void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
|
||||
struct omap_mcbsp_platform_data *config, int size)
|
||||
{
|
||||
int i;
|
||||
|
||||
omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *),
|
||||
GFP_KERNEL);
|
||||
if (!omap_mcbsp_devices) {
|
||||
printk(KERN_ERR "Could not register McBSP devices\n");
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
struct platform_device *new_mcbsp;
|
||||
int ret;
|
||||
|
||||
new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
|
||||
if (!new_mcbsp)
|
||||
continue;
|
||||
platform_device_add_resources(new_mcbsp, &res[i * res_count],
|
||||
res_count);
|
||||
config[i].reg_size = 2;
|
||||
config[i].reg_step = 2;
|
||||
new_mcbsp->dev.platform_data = &config[i];
|
||||
ret = platform_device_add(new_mcbsp);
|
||||
if (ret) {
|
||||
platform_device_put(new_mcbsp);
|
||||
continue;
|
||||
}
|
||||
omap_mcbsp_devices[i] = new_mcbsp;
|
||||
}
|
||||
}
|
||||
|
||||
static int __init omap1_mcbsp_init(void)
|
||||
{
|
||||
if (!cpu_class_is_omap1())
|
||||
|
173
arch/arm/mach-omap1/timer.c
Normal file
173
arch/arm/mach-omap1/timer.c
Normal file
@ -0,0 +1,173 @@
|
||||
/**
|
||||
* OMAP1 Dual-Mode Timers - platform device registration
|
||||
*
|
||||
* Contains first level initialization routines which internally
|
||||
* generates timer device information and registers with linux
|
||||
* device model. It also has low level function to chnage the timer
|
||||
* input clock source.
|
||||
*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Tarun Kanti DebBarma <tarun.kanti@ti.com>
|
||||
* Thara Gopinath <thara@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include <plat/dmtimer.h>
|
||||
|
||||
#define OMAP1610_GPTIMER1_BASE 0xfffb1400
|
||||
#define OMAP1610_GPTIMER2_BASE 0xfffb1c00
|
||||
#define OMAP1610_GPTIMER3_BASE 0xfffb2400
|
||||
#define OMAP1610_GPTIMER4_BASE 0xfffb2c00
|
||||
#define OMAP1610_GPTIMER5_BASE 0xfffb3400
|
||||
#define OMAP1610_GPTIMER6_BASE 0xfffb3c00
|
||||
#define OMAP1610_GPTIMER7_BASE 0xfffb7400
|
||||
#define OMAP1610_GPTIMER8_BASE 0xfffbd400
|
||||
|
||||
#define OMAP1_DM_TIMER_COUNT 8
|
||||
|
||||
static int omap1_dm_timer_set_src(struct platform_device *pdev,
|
||||
int source)
|
||||
{
|
||||
int n = (pdev->id - 1) << 1;
|
||||
u32 l;
|
||||
|
||||
l = __raw_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
|
||||
l |= source << n;
|
||||
__raw_writel(l, MOD_CONF_CTRL_1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int __init omap1_dm_timer_init(void)
|
||||
{
|
||||
int i;
|
||||
int ret;
|
||||
struct dmtimer_platform_data *pdata;
|
||||
struct platform_device *pdev;
|
||||
|
||||
if (!cpu_is_omap16xx())
|
||||
return 0;
|
||||
|
||||
for (i = 1; i <= OMAP1_DM_TIMER_COUNT; i++) {
|
||||
struct resource res[2];
|
||||
u32 base, irq;
|
||||
|
||||
switch (i) {
|
||||
case 1:
|
||||
base = OMAP1610_GPTIMER1_BASE;
|
||||
irq = INT_1610_GPTIMER1;
|
||||
break;
|
||||
case 2:
|
||||
base = OMAP1610_GPTIMER2_BASE;
|
||||
irq = INT_1610_GPTIMER2;
|
||||
break;
|
||||
case 3:
|
||||
base = OMAP1610_GPTIMER3_BASE;
|
||||
irq = INT_1610_GPTIMER3;
|
||||
break;
|
||||
case 4:
|
||||
base = OMAP1610_GPTIMER4_BASE;
|
||||
irq = INT_1610_GPTIMER4;
|
||||
break;
|
||||
case 5:
|
||||
base = OMAP1610_GPTIMER5_BASE;
|
||||
irq = INT_1610_GPTIMER5;
|
||||
break;
|
||||
case 6:
|
||||
base = OMAP1610_GPTIMER6_BASE;
|
||||
irq = INT_1610_GPTIMER6;
|
||||
break;
|
||||
case 7:
|
||||
base = OMAP1610_GPTIMER7_BASE;
|
||||
irq = INT_1610_GPTIMER7;
|
||||
break;
|
||||
case 8:
|
||||
base = OMAP1610_GPTIMER8_BASE;
|
||||
irq = INT_1610_GPTIMER8;
|
||||
break;
|
||||
default:
|
||||
/*
|
||||
* not supposed to reach here.
|
||||
* this is to remove warning.
|
||||
*/
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pdev = platform_device_alloc("omap_timer", i);
|
||||
if (!pdev) {
|
||||
pr_err("%s: Failed to device alloc for dmtimer%d\n",
|
||||
__func__, i);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
memset(res, 0, 2 * sizeof(struct resource));
|
||||
res[0].start = base;
|
||||
res[0].end = base + 0x46;
|
||||
res[0].flags = IORESOURCE_MEM;
|
||||
res[1].start = irq;
|
||||
res[1].end = irq;
|
||||
res[1].flags = IORESOURCE_IRQ;
|
||||
ret = platform_device_add_resources(pdev, res,
|
||||
ARRAY_SIZE(res));
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "%s: Failed to add resources.\n",
|
||||
__func__);
|
||||
goto err_free_pdev;
|
||||
}
|
||||
|
||||
pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
|
||||
if (!pdata) {
|
||||
dev_err(&pdev->dev, "%s: Failed to allocate pdata.\n",
|
||||
__func__);
|
||||
ret = -ENOMEM;
|
||||
goto err_free_pdata;
|
||||
}
|
||||
|
||||
pdata->set_timer_src = omap1_dm_timer_set_src;
|
||||
pdata->needs_manual_reset = 1;
|
||||
|
||||
ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "%s: Failed to add platform data.\n",
|
||||
__func__);
|
||||
goto err_free_pdata;
|
||||
}
|
||||
|
||||
ret = platform_device_add(pdev);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "%s: Failed to add platform device.\n",
|
||||
__func__);
|
||||
goto err_free_pdata;
|
||||
}
|
||||
|
||||
dev_dbg(&pdev->dev, " Registered.\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_pdata:
|
||||
kfree(pdata);
|
||||
|
||||
err_free_pdev:
|
||||
platform_device_unregister(pdev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
arch_initcall(omap1_dm_timer_init);
|
@ -106,9 +106,13 @@ comment "OMAP Board Type"
|
||||
depends on ARCH_OMAP2PLUS
|
||||
|
||||
config MACH_OMAP_GENERIC
|
||||
bool "Generic OMAP board"
|
||||
depends on ARCH_OMAP2
|
||||
bool "Generic OMAP2+ board"
|
||||
depends on ARCH_OMAP2PLUS
|
||||
select USE_OF
|
||||
default y
|
||||
help
|
||||
Support for generic TI OMAP2+ boards using Flattened Device Tree.
|
||||
More information at Documentation/devicetree
|
||||
|
||||
config MACH_OMAP2_TUSB6010
|
||||
bool
|
||||
|
@ -89,14 +89,13 @@ obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
|
||||
vp44xx_data.o
|
||||
|
||||
# OMAP voltage domains
|
||||
ifeq ($(CONFIG_PM),y)
|
||||
voltagedomain-common := voltage.o
|
||||
obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common)
|
||||
voltagedomain-common := voltage.o vc.o vp.o
|
||||
obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) \
|
||||
voltagedomains2xxx_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) \
|
||||
voltagedomains3xxx_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) \
|
||||
voltagedomains44xx_data.o
|
||||
endif
|
||||
|
||||
# OMAP powerdomain framework
|
||||
powerdomain-common += powerdomain.o powerdomain-common.o
|
||||
@ -116,9 +115,12 @@ obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \
|
||||
obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \
|
||||
clockdomain2xxx_3xxx.o \
|
||||
clockdomains2xxx_3xxx_data.o
|
||||
obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o
|
||||
obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \
|
||||
clockdomain2xxx_3xxx.o \
|
||||
clockdomains2xxx_3xxx_data.o
|
||||
clockdomains2xxx_3xxx_data.o \
|
||||
clockdomains3xxx_data.o
|
||||
obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
|
||||
clockdomain44xx.o \
|
||||
clockdomains44xx_data.o
|
||||
@ -185,78 +187,66 @@ endif
|
||||
# Specific board support
|
||||
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
|
||||
obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
|
||||
obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o \
|
||||
hsmmc.o
|
||||
obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o
|
||||
obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o
|
||||
obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o \
|
||||
hsmmc.o
|
||||
obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o \
|
||||
hsmmc.o
|
||||
obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o \
|
||||
board-flash.o \
|
||||
hsmmc.o
|
||||
obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o \
|
||||
hsmmc.o
|
||||
obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o \
|
||||
hsmmc.o
|
||||
obj-$(CONFIG_MACH_OVERO) += board-overo.o \
|
||||
hsmmc.o
|
||||
obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o \
|
||||
hsmmc.o
|
||||
obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \
|
||||
hsmmc.o
|
||||
obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \
|
||||
hsmmc.o \
|
||||
board-flash.o
|
||||
obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
|
||||
obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o
|
||||
obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
|
||||
obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o
|
||||
obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o
|
||||
obj-$(CONFIG_MACH_ENCORE) += board-omap3encore.o
|
||||
obj-$(CONFIG_MACH_OVERO) += board-overo.o
|
||||
obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o
|
||||
obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o
|
||||
obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o
|
||||
obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
|
||||
obj-$(CONFIG_MACH_NOKIA_RM680) += board-rm680.o \
|
||||
sdram-nokia.o \
|
||||
hsmmc.o
|
||||
sdram-nokia.o
|
||||
obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \
|
||||
sdram-nokia.o \
|
||||
board-rx51-peripherals.o \
|
||||
board-rx51-video.o \
|
||||
hsmmc.o
|
||||
board-rx51-video.o
|
||||
obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom.o \
|
||||
board-zoom-peripherals.o \
|
||||
board-zoom-display.o \
|
||||
board-flash.o \
|
||||
hsmmc.o \
|
||||
board-zoom-debugboard.o
|
||||
obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom.o \
|
||||
board-zoom-peripherals.o \
|
||||
board-zoom-display.o \
|
||||
board-flash.o \
|
||||
hsmmc.o \
|
||||
board-zoom-debugboard.o
|
||||
obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \
|
||||
board-zoom-peripherals.o \
|
||||
board-zoom-display.o \
|
||||
board-flash.o \
|
||||
hsmmc.o
|
||||
obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \
|
||||
hsmmc.o
|
||||
board-zoom-display.o
|
||||
obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o
|
||||
obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o
|
||||
obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \
|
||||
hsmmc.o
|
||||
obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \
|
||||
hsmmc.o
|
||||
obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o
|
||||
obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o
|
||||
obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o \
|
||||
hsmmc.o \
|
||||
omap_phy_internal.o
|
||||
obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \
|
||||
hsmmc.o \
|
||||
omap_phy_internal.o
|
||||
|
||||
obj-$(CONFIG_MACH_PCM049) += board-omap4pcm049.o \
|
||||
omap_phy_internal.o
|
||||
|
||||
obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o \
|
||||
omap_phy_internal.o \
|
||||
omap_phy_internal.o
|
||||
|
||||
obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
|
||||
|
||||
obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \
|
||||
hsmmc.o
|
||||
obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o
|
||||
obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o
|
||||
|
||||
# Platform specific device init code
|
||||
|
||||
omap-flash-$(CONFIG_MTD_NAND_OMAP2) := board-flash.o
|
||||
omap-flash-$(CONFIG_MTD_ONENAND_OMAP2) := board-flash.o
|
||||
obj-y += $(omap-flash-y) $(omap-flash-m)
|
||||
|
||||
omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o
|
||||
obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y)
|
||||
|
||||
|
||||
usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o
|
||||
obj-y += $(usbfs-m) $(usbfs-y)
|
||||
obj-y += usb-musb.o
|
||||
|
@ -141,12 +141,6 @@ static struct omap_board_config_kernel sdp2430_config[] __initdata = {
|
||||
{OMAP_TAG_LCD, &sdp2430_lcd_config},
|
||||
};
|
||||
|
||||
static void __init omap_2430sdp_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(NULL, NULL);
|
||||
}
|
||||
|
||||
static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
|
||||
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
|
||||
};
|
||||
@ -236,6 +230,7 @@ static void __init omap_2430sdp_init(void)
|
||||
|
||||
platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
omap2_hsmmc_init(mmc);
|
||||
omap2_usbfs_init(&sdp2430_usb_config);
|
||||
|
||||
@ -249,18 +244,12 @@ static void __init omap_2430sdp_init(void)
|
||||
"Secondary LCD backlight");
|
||||
}
|
||||
|
||||
static void __init omap_2430sdp_map_io(void)
|
||||
{
|
||||
omap2_set_globals_243x();
|
||||
omap243x_map_common_io();
|
||||
}
|
||||
|
||||
MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
|
||||
/* Maintainer: Syed Khasim - Texas Instruments Inc */
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap_2430sdp_map_io,
|
||||
.init_early = omap_2430sdp_init_early,
|
||||
.map_io = omap243x_map_io,
|
||||
.init_early = omap2430_init_early,
|
||||
.init_irq = omap2_init_irq,
|
||||
.init_machine = omap_2430sdp_init,
|
||||
.timer = &omap2_timer,
|
||||
|
@ -225,12 +225,6 @@ static struct omap_dss_board_info sdp3430_dss_data = {
|
||||
static struct omap_board_config_kernel sdp3430_config[] __initdata = {
|
||||
};
|
||||
|
||||
static void __init omap_3430sdp_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
|
||||
}
|
||||
|
||||
static struct omap2_hsmmc_info mmc[] = {
|
||||
{
|
||||
.mmc = 1,
|
||||
@ -719,6 +713,7 @@ static void __init omap_3430sdp_init(void)
|
||||
gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
|
||||
omap_ads7846_init(1, gpio_pendown, 310, NULL);
|
||||
board_serial_init();
|
||||
omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
|
||||
usb_musb_init(NULL);
|
||||
board_smc91x_init();
|
||||
board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
|
||||
@ -732,7 +727,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap_3430sdp_init_early,
|
||||
.init_early = omap3430_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = omap_3430sdp_init,
|
||||
.timer = &omap3_timer,
|
||||
|
@ -70,13 +70,6 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
|
||||
static struct omap_board_config_kernel sdp_config[] __initdata = {
|
||||
};
|
||||
|
||||
static void __init omap_sdp_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
|
||||
h8mbx00u0mer0em_sdrc_params);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
@ -207,6 +200,8 @@ static void __init omap_sdp_init(void)
|
||||
omap_board_config = sdp_config;
|
||||
omap_board_config_size = ARRAY_SIZE(sdp_config);
|
||||
zoom_peripherals_init();
|
||||
omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
|
||||
h8mbx00u0mer0em_sdrc_params);
|
||||
zoom_display_init();
|
||||
board_smc91x_init();
|
||||
board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
|
||||
@ -218,7 +213,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap_sdp_init_early,
|
||||
.init_early = omap3630_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = omap_sdp_init,
|
||||
.timer = &omap3_timer,
|
||||
|
@ -129,7 +129,7 @@ static const int sdp4430_keymap[] = {
|
||||
KEY(7, 6, KEY_OK),
|
||||
KEY(7, 7, KEY_DOWN),
|
||||
};
|
||||
static struct omap_device_pad keypad_pads[] __initdata = {
|
||||
static struct omap_device_pad keypad_pads[] = {
|
||||
{ .name = "kpd_col1.kpd_col1",
|
||||
.enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
|
||||
},
|
||||
@ -389,12 +389,6 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
|
||||
{ OMAP_TAG_LCD, &sdp4430_lcd_config },
|
||||
};
|
||||
|
||||
static void __init omap_4430sdp_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(NULL, NULL);
|
||||
}
|
||||
|
||||
static struct omap_musb_board_data musb_board_data = {
|
||||
.interface_type = MUSB_INTERFACE_UTMI,
|
||||
.mode = MUSB_OTG,
|
||||
@ -809,6 +803,7 @@ static void __init omap_4430sdp_init(void)
|
||||
omap_sfh7741prox_init();
|
||||
platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
|
||||
board_serial_init();
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
omap4_sdp4430_wifi_init();
|
||||
omap4_twl6030_hsmmc_init(mmc);
|
||||
|
||||
@ -830,18 +825,12 @@ static void __init omap_4430sdp_init(void)
|
||||
omap_4430sdp_display_init();
|
||||
}
|
||||
|
||||
static void __init omap_4430sdp_map_io(void)
|
||||
{
|
||||
omap2_set_globals_443x();
|
||||
omap44xx_map_common_io();
|
||||
}
|
||||
|
||||
MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
|
||||
/* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap_4430sdp_map_io,
|
||||
.init_early = omap_4430sdp_init_early,
|
||||
.map_io = omap4_map_io,
|
||||
.init_early = omap4430_init_early,
|
||||
.init_irq = gic_init_irq,
|
||||
.init_machine = omap_4430sdp_init,
|
||||
.timer = &omap4_timer,
|
||||
|
@ -47,12 +47,6 @@ static struct omap_board_mux board_mux[] __initdata = {
|
||||
};
|
||||
#endif
|
||||
|
||||
static void __init am3517_crane_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(NULL, NULL);
|
||||
}
|
||||
|
||||
static struct usbhs_omap_board_data usbhs_bdata __initdata = {
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
@ -70,6 +64,7 @@ static void __init am3517_crane_init(void)
|
||||
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
|
||||
omap_board_config = am3517_crane_config;
|
||||
omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
|
||||
@ -101,7 +96,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = am3517_crane_init_early,
|
||||
.init_early = am35xx_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = am3517_crane_init,
|
||||
.timer = &omap3_timer,
|
||||
|
@ -362,11 +362,6 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
|
||||
/*
|
||||
* Board initialization
|
||||
*/
|
||||
static void __init am3517_evm_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(NULL, NULL);
|
||||
}
|
||||
|
||||
static struct omap_musb_board_data musb_board_data = {
|
||||
.interface_type = MUSB_INTERFACE_ULPI,
|
||||
@ -469,6 +464,7 @@ static void __init am3517_evm_init(void)
|
||||
am3517_evm_i2c_init();
|
||||
omap_display_init(&am3517_evm_dss_data);
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
|
||||
/* Configure GPIO for EHCI port */
|
||||
omap_mux_init_gpio(57, OMAP_PIN_OUTPUT);
|
||||
@ -493,7 +489,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = am3517_evm_init_early,
|
||||
.init_early = am35xx_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = am3517_evm_init,
|
||||
.timer = &omap3_timer,
|
||||
|
@ -273,12 +273,6 @@ static struct omap_board_config_kernel apollon_config[] __initdata = {
|
||||
{ OMAP_TAG_LCD, &apollon_lcd_config },
|
||||
};
|
||||
|
||||
static void __init omap_apollon_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(NULL, NULL);
|
||||
}
|
||||
|
||||
static struct gpio apollon_gpio_leds[] __initdata = {
|
||||
{ LED0_GPIO13, GPIOF_OUT_INIT_LOW, "LED0" }, /* LED0 - AA10 */
|
||||
{ LED1_GPIO14, GPIOF_OUT_INIT_LOW, "LED1" }, /* LED1 - AA6 */
|
||||
@ -340,20 +334,15 @@ static void __init omap_apollon_init(void)
|
||||
*/
|
||||
platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
|
||||
omap_serial_init();
|
||||
}
|
||||
|
||||
static void __init omap_apollon_map_io(void)
|
||||
{
|
||||
omap2_set_globals_242x();
|
||||
omap242x_map_common_io();
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
}
|
||||
|
||||
MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
|
||||
/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap_apollon_map_io,
|
||||
.init_early = omap_apollon_init_early,
|
||||
.map_io = omap242x_map_io,
|
||||
.init_early = omap2420_init_early,
|
||||
.init_irq = omap2_init_irq,
|
||||
.init_machine = omap_apollon_init,
|
||||
.timer = &omap2_timer,
|
||||
|
@ -471,13 +471,6 @@ static void __init cm_t35_init_i2c(void)
|
||||
omap3_pmic_init("tps65930", &cm_t35_twldata);
|
||||
}
|
||||
|
||||
static void __init cm_t35_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
/* nCS and IRQ for CM-T35 ethernet */
|
||||
@ -610,6 +603,8 @@ static void __init cm_t3x_common_init(void)
|
||||
omap_board_config_size = ARRAY_SIZE(cm_t35_config);
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
cm_t35_init_i2c();
|
||||
omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL);
|
||||
cm_t35_init_ethernet();
|
||||
@ -637,7 +632,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = cm_t35_init_early,
|
||||
.init_early = omap35xx_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = cm_t35_init,
|
||||
.timer = &omap3_timer,
|
||||
@ -647,7 +642,7 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = cm_t35_init_early,
|
||||
.init_early = omap3630_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = cm_t3730_init,
|
||||
.timer = &omap3_timer,
|
||||
|
@ -251,12 +251,6 @@ static inline void cm_t3517_init_nand(void) {}
|
||||
static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
|
||||
};
|
||||
|
||||
static void __init cm_t3517_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(NULL, NULL);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
/* GPIO186 - Green LED */
|
||||
@ -289,6 +283,7 @@ static void __init cm_t3517_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
omap_board_config = cm_t3517_config;
|
||||
omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
|
||||
cm_t3517_init_leds();
|
||||
@ -302,7 +297,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = cm_t3517_init_early,
|
||||
.init_early = am35xx_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = cm_t3517_init,
|
||||
.timer = &omap3_timer,
|
||||
|
@ -397,19 +397,6 @@ static struct platform_device keys_gpio = {
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
static void __init devkit8000_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
}
|
||||
|
||||
static void __init devkit8000_init_irq(void)
|
||||
{
|
||||
omap3_init_irq();
|
||||
}
|
||||
|
||||
#define OMAP_DM9000_BASE 0x2c000000
|
||||
|
||||
static struct resource omap_dm9000_resources[] = {
|
||||
@ -645,6 +632,8 @@ static void __init devkit8000_init(void)
|
||||
{
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
|
||||
omap_dm9000_init();
|
||||
|
||||
@ -670,8 +659,8 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = devkit8000_init_early,
|
||||
.init_irq = devkit8000_init_irq,
|
||||
.init_early = omap35xx_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = devkit8000_init,
|
||||
.timer = &omap3_secure_timer,
|
||||
MACHINE_END
|
||||
|
@ -148,11 +148,6 @@ __init board_nand_init(struct mtd_partition *nand_parts,
|
||||
board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
|
||||
gpmc_nand_init(&board_nand_data);
|
||||
}
|
||||
#else
|
||||
void
|
||||
__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, int nand_type)
|
||||
{
|
||||
}
|
||||
#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
|
||||
|
||||
/**
|
||||
|
@ -24,7 +24,26 @@ struct flash_partitions {
|
||||
int nr_parts;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_MTD_NAND_OMAP2) || \
|
||||
defined(CONFIG_MTD_NAND_OMAP2_MODULE) || \
|
||||
defined(CONFIG_MTD_ONENAND_OMAP2) || \
|
||||
defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
|
||||
extern void board_flash_init(struct flash_partitions [],
|
||||
char chip_sel[][GPMC_CS_NUM], int nand_type);
|
||||
#else
|
||||
static inline void board_flash_init(struct flash_partitions part[],
|
||||
char chip_sel[][GPMC_CS_NUM], int nand_type)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MTD_NAND_OMAP2) || \
|
||||
defined(CONFIG_MTD_NAND_OMAP2_MODULE)
|
||||
extern void board_nand_init(struct mtd_partition *nand_parts,
|
||||
u8 nr_parts, u8 cs, int nand_type);
|
||||
#else
|
||||
static inline void board_nand_init(struct mtd_partition *nand_parts,
|
||||
u8 nr_parts, u8 cs, int nand_type)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
@ -1,76 +1,154 @@
|
||||
/*
|
||||
* linux/arch/arm/mach-omap2/board-generic.c
|
||||
*
|
||||
* Copyright (C) 2005 Nokia Corporation
|
||||
* Author: Paul Mundt <paul.mundt@nokia.com>
|
||||
*
|
||||
* Modified from mach-omap/omap1/board-generic.c
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* Code for generic OMAP2 board. Should work on many OMAP2 systems where
|
||||
* the bootloader passes the board-specific data to the kernel.
|
||||
* Do not put any board specific code to this file; create a new machine
|
||||
* type if you need custom low-level initializations.
|
||||
* Modified from the original mach-omap/omap2/board-generic.c did by Paul
|
||||
* to support the OMAP2+ device tree boards with an unique board file.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/i2c/twl.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/gpio.h>
|
||||
#include <plat/usb.h>
|
||||
#include <plat/board.h>
|
||||
#include <plat/common.h>
|
||||
#include <mach/omap4-common.h>
|
||||
#include "common-board-devices.h"
|
||||
|
||||
static struct omap_board_config_kernel generic_config[] = {
|
||||
/*
|
||||
* XXX: Still needed to boot until the i2c & twl driver is adapted to
|
||||
* device-tree
|
||||
*/
|
||||
static struct twl4030_platform_data sdp4430_twldata = {
|
||||
.irq_base = TWL6030_IRQ_BASE,
|
||||
.irq_end = TWL6030_IRQ_END,
|
||||
};
|
||||
|
||||
static void __init omap_generic_init_early(void)
|
||||
static void __init omap4_i2c_init(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(NULL, NULL);
|
||||
omap4_pmic_init("twl6030", &sdp4430_twldata);
|
||||
}
|
||||
|
||||
static struct twl4030_platform_data beagle_twldata = {
|
||||
.irq_base = TWL4030_IRQ_BASE,
|
||||
.irq_end = TWL4030_IRQ_END,
|
||||
};
|
||||
|
||||
static void __init omap3_i2c_init(void)
|
||||
{
|
||||
omap3_pmic_init("twl4030", &beagle_twldata);
|
||||
}
|
||||
|
||||
static struct of_device_id omap_dt_match_table[] __initdata = {
|
||||
{ .compatible = "simple-bus", },
|
||||
{ .compatible = "ti,omap-infra", },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct of_device_id intc_match[] __initdata = {
|
||||
{ .compatible = "ti,omap3-intc", },
|
||||
{ .compatible = "arm,cortex-a9-gic", },
|
||||
{ }
|
||||
};
|
||||
|
||||
static void __init omap_generic_init(void)
|
||||
{
|
||||
struct device_node *node = of_find_matching_node(NULL, intc_match);
|
||||
if (node)
|
||||
irq_domain_add_simple(node, 0);
|
||||
|
||||
omap_serial_init();
|
||||
omap_board_config = generic_config;
|
||||
omap_board_config_size = ARRAY_SIZE(generic_config);
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
|
||||
of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static void __init omap_generic_map_io(void)
|
||||
static void __init omap4_init(void)
|
||||
{
|
||||
if (cpu_is_omap242x()) {
|
||||
omap2_set_globals_242x();
|
||||
omap242x_map_common_io();
|
||||
} else if (cpu_is_omap243x()) {
|
||||
omap2_set_globals_243x();
|
||||
omap243x_map_common_io();
|
||||
} else if (cpu_is_omap34xx()) {
|
||||
omap2_set_globals_3xxx();
|
||||
omap34xx_map_common_io();
|
||||
} else if (cpu_is_omap44xx()) {
|
||||
omap2_set_globals_443x();
|
||||
omap44xx_map_common_io();
|
||||
}
|
||||
omap4_i2c_init();
|
||||
omap_generic_init();
|
||||
}
|
||||
|
||||
/* XXX This machine entry name should be updated */
|
||||
MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
|
||||
/* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
|
||||
.boot_params = 0x80000100,
|
||||
static void __init omap3_init(void)
|
||||
{
|
||||
omap3_i2c_init();
|
||||
omap_generic_init();
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SOC_OMAP2420)
|
||||
static const char *omap242x_boards_compat[] __initdata = {
|
||||
"ti,omap2420",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap_generic_map_io,
|
||||
.init_early = omap_generic_init_early,
|
||||
.map_io = omap242x_map_io,
|
||||
.init_early = omap2420_init_early,
|
||||
.init_irq = omap2_init_irq,
|
||||
.init_machine = omap_generic_init,
|
||||
.timer = &omap2_timer,
|
||||
.dt_compat = omap242x_boards_compat,
|
||||
MACHINE_END
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_OMAP2430)
|
||||
static const char *omap243x_boards_compat[] __initdata = {
|
||||
"ti,omap2430",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap243x_map_io,
|
||||
.init_early = omap2430_init_early,
|
||||
.init_irq = omap2_init_irq,
|
||||
.init_machine = omap_generic_init,
|
||||
.timer = &omap2_timer,
|
||||
.dt_compat = omap243x_boards_compat,
|
||||
MACHINE_END
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP3)
|
||||
static const char *omap3_boards_compat[] __initdata = {
|
||||
"ti,omap3",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap3430_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = omap3_init,
|
||||
.timer = &omap3_timer,
|
||||
.dt_compat = omap3_boards_compat,
|
||||
MACHINE_END
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP4)
|
||||
static const char *omap4_boards_compat[] __initdata = {
|
||||
"ti,omap4",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap4_map_io,
|
||||
.init_early = omap4430_init_early,
|
||||
.init_irq = gic_init_irq,
|
||||
.init_machine = omap4_init,
|
||||
.timer = &omap4_timer,
|
||||
.dt_compat = omap4_boards_compat,
|
||||
MACHINE_END
|
||||
#endif
|
||||
|
@ -290,17 +290,6 @@ static struct omap_board_config_kernel h4_config[] __initdata = {
|
||||
{ OMAP_TAG_LCD, &h4_lcd_config },
|
||||
};
|
||||
|
||||
static void __init omap_h4_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(NULL, NULL);
|
||||
}
|
||||
|
||||
static void __init omap_h4_init_irq(void)
|
||||
{
|
||||
omap2_init_irq();
|
||||
}
|
||||
|
||||
static struct at24_platform_data m24c01 = {
|
||||
.byte_len = SZ_1K / 8,
|
||||
.page_size = 16,
|
||||
@ -371,22 +360,17 @@ static void __init omap_h4_init(void)
|
||||
platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
|
||||
omap2_usbfs_init(&h4_usb_config);
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
h4_init_flash();
|
||||
}
|
||||
|
||||
static void __init omap_h4_map_io(void)
|
||||
{
|
||||
omap2_set_globals_242x();
|
||||
omap242x_map_common_io();
|
||||
}
|
||||
|
||||
MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
|
||||
/* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap_h4_map_io,
|
||||
.init_early = omap_h4_init_early,
|
||||
.init_irq = omap_h4_init_irq,
|
||||
.map_io = omap242x_map_io,
|
||||
.init_early = omap2420_init_early,
|
||||
.init_irq = omap2_init_irq,
|
||||
.init_machine = omap_h4_init,
|
||||
.timer = &omap2_timer,
|
||||
MACHINE_END
|
||||
|
@ -491,13 +491,6 @@ static struct platform_device *igep_devices[] __initdata = {
|
||||
&igep_vwlan_device,
|
||||
};
|
||||
|
||||
static void __init igep_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(m65kxxxxam_sdrc_params,
|
||||
m65kxxxxam_sdrc_params);
|
||||
}
|
||||
|
||||
static int igep2_keymap[] = {
|
||||
KEY(0, 0, KEY_LEFT),
|
||||
KEY(0, 1, KEY_RIGHT),
|
||||
@ -650,6 +643,8 @@ static void __init igep_init(void)
|
||||
igep_i2c_init();
|
||||
platform_add_devices(igep_devices, ARRAY_SIZE(igep_devices));
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(m65kxxxxam_sdrc_params,
|
||||
m65kxxxxam_sdrc_params);
|
||||
usb_musb_init(NULL);
|
||||
|
||||
igep_flash_init();
|
||||
@ -675,7 +670,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = igep_init_early,
|
||||
.init_early = omap35xx_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = igep_init,
|
||||
.timer = &omap3_timer,
|
||||
@ -685,7 +680,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = igep_init_early,
|
||||
.init_early = omap35xx_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = igep_init,
|
||||
.timer = &omap3_timer,
|
||||
|
@ -193,12 +193,6 @@ static struct omap_board_config_kernel ldp_config[] __initdata = {
|
||||
{ OMAP_TAG_LCD, &ldp_lcd_config },
|
||||
};
|
||||
|
||||
static void __init omap_ldp_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(NULL, NULL);
|
||||
}
|
||||
|
||||
static struct twl4030_gpio_platform_data ldp_gpio_data = {
|
||||
.gpio_base = OMAP_MAX_GPIO_LINES,
|
||||
.irq_base = TWL4030_GPIO_IRQ_BASE,
|
||||
@ -325,6 +319,7 @@ static void __init omap_ldp_init(void)
|
||||
platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
|
||||
omap_ads7846_init(1, 54, 310, NULL);
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
usb_musb_init(NULL);
|
||||
board_nand_init(ldp_nand_partitions,
|
||||
ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
|
||||
@ -336,7 +331,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap_ldp_init_early,
|
||||
.init_early = omap3430_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = omap_ldp_init,
|
||||
.timer = &omap3_timer,
|
||||
|
@ -616,18 +616,6 @@ static struct i2c_board_info n810_i2c_board_info_2[] __initdata = {
|
||||
},
|
||||
};
|
||||
|
||||
static void __init n8x0_map_io(void)
|
||||
{
|
||||
omap2_set_globals_242x();
|
||||
omap242x_map_common_io();
|
||||
}
|
||||
|
||||
static void __init n8x0_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(NULL, NULL);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
/* I2S codec port pins for McBSP block */
|
||||
@ -689,6 +677,7 @@ static void __init n8x0_init_machine(void)
|
||||
i2c_register_board_info(2, n810_i2c_board_info_2,
|
||||
ARRAY_SIZE(n810_i2c_board_info_2));
|
||||
board_serial_init();
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
gpmc_onenand_init(board_onenand_data);
|
||||
n8x0_mmc_init();
|
||||
n8x0_usb_init();
|
||||
@ -697,8 +686,8 @@ static void __init n8x0_init_machine(void)
|
||||
MACHINE_START(NOKIA_N800, "Nokia N800")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = n8x0_map_io,
|
||||
.init_early = n8x0_init_early,
|
||||
.map_io = omap242x_map_io,
|
||||
.init_early = omap2420_init_early,
|
||||
.init_irq = omap2_init_irq,
|
||||
.init_machine = n8x0_init_machine,
|
||||
.timer = &omap2_timer,
|
||||
@ -707,8 +696,8 @@ MACHINE_END
|
||||
MACHINE_START(NOKIA_N810, "Nokia N810")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = n8x0_map_io,
|
||||
.init_early = n8x0_init_early,
|
||||
.map_io = omap242x_map_io,
|
||||
.init_early = omap2420_init_early,
|
||||
.init_irq = omap2_init_irq,
|
||||
.init_machine = n8x0_init_machine,
|
||||
.timer = &omap2_timer,
|
||||
@ -717,8 +706,8 @@ MACHINE_END
|
||||
MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = n8x0_map_io,
|
||||
.init_early = n8x0_init_early,
|
||||
.map_io = omap242x_map_io,
|
||||
.init_early = omap2420_init_early,
|
||||
.init_irq = omap2_init_irq,
|
||||
.init_machine = n8x0_init_machine,
|
||||
.timer = &omap2_timer,
|
||||
|
@ -447,13 +447,6 @@ static struct platform_device keys_gpio = {
|
||||
static void __init omap3_beagle_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
}
|
||||
|
||||
static void __init omap3_beagle_init_irq(void)
|
||||
{
|
||||
omap3_init_irq();
|
||||
}
|
||||
|
||||
static struct platform_device *omap3_beagle_devices[] __initdata = {
|
||||
@ -493,8 +486,8 @@ static void __init beagle_opp_init(void)
|
||||
if (cpu_is_omap3630()) {
|
||||
struct device *mpu_dev, *iva_dev;
|
||||
|
||||
mpu_dev = omap2_get_mpuss_device();
|
||||
iva_dev = omap2_get_iva_device();
|
||||
mpu_dev = omap_device_get_by_hwmod_name("mpu");
|
||||
iva_dev = omap_device_get_by_hwmod_name("iva");
|
||||
|
||||
if (!mpu_dev || !iva_dev) {
|
||||
pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
|
||||
@ -534,6 +527,8 @@ static void __init omap3_beagle_init(void)
|
||||
ARRAY_SIZE(omap3_beagle_devices));
|
||||
omap_display_init(&beagle_dss_data);
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
|
||||
omap_mux_init_gpio(170, OMAP_PIN_INPUT);
|
||||
/* REVISIT leave DVI powered down until it's needed ... */
|
||||
@ -561,7 +556,7 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap3_beagle_init_early,
|
||||
.init_irq = omap3_beagle_init_irq,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = omap3_beagle_init,
|
||||
.timer = &omap3_secure_timer,
|
||||
MACHINE_END
|
||||
|
@ -520,12 +520,6 @@ static int __init omap3_evm_i2c_init(void)
|
||||
static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
|
||||
};
|
||||
|
||||
static void __init omap3_evm_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
|
||||
}
|
||||
|
||||
static struct usbhs_omap_board_data usbhs_bdata __initdata = {
|
||||
|
||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
@ -640,6 +634,7 @@ static void __init omap3_evm_init(void)
|
||||
omap_display_init(&omap3_evm_dss_data);
|
||||
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
|
||||
|
||||
/* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
|
||||
usb_nop_xceiv_register();
|
||||
@ -684,7 +679,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap3_evm_init_early,
|
||||
.init_early = omap35xx_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = omap3_evm_init,
|
||||
.timer = &omap3_timer,
|
||||
|
@ -182,12 +182,6 @@ static inline void __init board_smsc911x_init(void)
|
||||
gpmc_smsc911x_init(&board_smsc911x_data);
|
||||
}
|
||||
|
||||
static void __init omap3logic_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(NULL, NULL);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
@ -200,6 +194,7 @@ static void __init omap3logic_init(void)
|
||||
omap3torpedo_fix_pbias_voltage();
|
||||
omap3logic_i2c_init();
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
board_mmc_init();
|
||||
board_smsc911x_init();
|
||||
|
||||
@ -211,7 +206,7 @@ static void __init omap3logic_init(void)
|
||||
MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
|
||||
.boot_params = 0x80000100,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap3logic_init_early,
|
||||
.init_early = omap35xx_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = omap3logic_init,
|
||||
.timer = &omap3_timer,
|
||||
@ -220,7 +215,7 @@ MACHINE_END
|
||||
MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
|
||||
.boot_params = 0x80000100,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap3logic_init_early,
|
||||
.init_early = omap35xx_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = omap3logic_init,
|
||||
.timer = &omap3_timer,
|
||||
|
@ -525,13 +525,6 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
|
||||
}
|
||||
};
|
||||
|
||||
static void __init omap3pandora_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
}
|
||||
|
||||
static void __init pandora_wl1251_init(void)
|
||||
{
|
||||
struct wl12xx_platform_data pandora_wl1251_pdata;
|
||||
@ -593,6 +586,8 @@ static void __init omap3pandora_init(void)
|
||||
ARRAY_SIZE(omap3pandora_devices));
|
||||
omap_display_init(&pandora_dss_data);
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
spi_register_board_info(omap3pandora_spi_board_info,
|
||||
ARRAY_SIZE(omap3pandora_spi_board_info));
|
||||
omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
|
||||
@ -609,7 +604,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap3pandora_init_early,
|
||||
.init_early = omap35xx_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = omap3pandora_init,
|
||||
.timer = &omap3_timer,
|
||||
|
@ -428,17 +428,6 @@ static int __init omap3_stalker_i2c_init(void)
|
||||
static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
|
||||
};
|
||||
|
||||
static void __init omap3_stalker_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
|
||||
}
|
||||
|
||||
static void __init omap3_stalker_init_irq(void)
|
||||
{
|
||||
omap3_init_irq();
|
||||
}
|
||||
|
||||
static struct platform_device *omap3_stalker_devices[] __initdata = {
|
||||
&keys_gpio,
|
||||
};
|
||||
@ -478,6 +467,7 @@ static void __init omap3_stalker_init(void)
|
||||
omap_display_init(&omap3_stalker_dss_data);
|
||||
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL);
|
||||
usb_musb_init(NULL);
|
||||
usbhs_init(&usbhs_bdata);
|
||||
omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL);
|
||||
@ -496,8 +486,8 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
|
||||
/* Maintainer: Jason Lam -lzg@ema-tech.com */
|
||||
.boot_params = 0x80000100,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap3_stalker_init_early,
|
||||
.init_irq = omap3_stalker_init_irq,
|
||||
.init_early = omap35xx_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = omap3_stalker_init,
|
||||
.timer = &omap3_secure_timer,
|
||||
MACHINE_END
|
||||
|
@ -326,18 +326,6 @@ static struct omap_board_mux board_mux[] __initdata = {
|
||||
};
|
||||
#endif
|
||||
|
||||
static void __init omap3_touchbook_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
}
|
||||
|
||||
static void __init omap3_touchbook_init_irq(void)
|
||||
{
|
||||
omap3_init_irq();
|
||||
}
|
||||
|
||||
static struct platform_device *omap3_touchbook_devices[] __initdata = {
|
||||
&omap3_touchbook_lcd_device,
|
||||
&leds_gpio,
|
||||
@ -385,6 +373,8 @@ static void __init omap3_touchbook_init(void)
|
||||
platform_add_devices(omap3_touchbook_devices,
|
||||
ARRAY_SIZE(omap3_touchbook_devices));
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
|
||||
omap_mux_init_gpio(170, OMAP_PIN_INPUT);
|
||||
/* REVISIT leave DVI powered down until it's needed ... */
|
||||
@ -407,8 +397,8 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap3_touchbook_init_early,
|
||||
.init_irq = omap3_touchbook_init_irq,
|
||||
.init_early = omap3430_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = omap3_touchbook_init,
|
||||
.timer = &omap3_secure_timer,
|
||||
MACHINE_END
|
||||
|
@ -95,12 +95,6 @@ static struct platform_device *panda_devices[] __initdata = {
|
||||
&wl1271_device,
|
||||
};
|
||||
|
||||
static void __init omap4_panda_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(NULL, NULL);
|
||||
}
|
||||
|
||||
static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
|
||||
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
@ -569,24 +563,19 @@ static void __init omap4_panda_init(void)
|
||||
platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
|
||||
platform_device_register(&omap_vwlan_device);
|
||||
board_serial_init();
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
omap4_twl6030_hsmmc_init(mmc);
|
||||
omap4_ehci_init();
|
||||
usb_musb_init(&musb_board_data);
|
||||
omap4_panda_display_init();
|
||||
}
|
||||
|
||||
static void __init omap4_panda_map_io(void)
|
||||
{
|
||||
omap2_set_globals_443x();
|
||||
omap44xx_map_common_io();
|
||||
}
|
||||
|
||||
MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
|
||||
/* Maintainer: David Anders - Texas Instruments Inc */
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap4_panda_map_io,
|
||||
.init_early = omap4_panda_init_early,
|
||||
.map_io = omap4_map_io,
|
||||
.init_early = omap4430_init_early,
|
||||
.init_irq = gic_init_irq,
|
||||
.init_machine = omap4_panda_init,
|
||||
.timer = &omap4_timer,
|
||||
|
@ -478,13 +478,6 @@ static int __init overo_spi_init(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init overo_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
}
|
||||
|
||||
static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
|
||||
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
|
||||
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
|
||||
@ -514,6 +507,8 @@ static void __init overo_init(void)
|
||||
overo_i2c_init();
|
||||
omap_display_init(&overo_dss_data);
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
omap_nand_flash_init(0, overo_nand_partitions,
|
||||
ARRAY_SIZE(overo_nand_partitions));
|
||||
usb_musb_init(NULL);
|
||||
@ -564,7 +559,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = overo_init_early,
|
||||
.init_early = omap35xx_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = overo_init,
|
||||
.timer = &omap3_timer,
|
||||
|
@ -123,15 +123,6 @@ static void __init rm680_peripherals_init(void)
|
||||
omap2_hsmmc_init(mmc);
|
||||
}
|
||||
|
||||
static void __init rm680_init_early(void)
|
||||
{
|
||||
struct omap_sdrc_params *sdrc_params;
|
||||
|
||||
omap2_init_common_infrastructure();
|
||||
sdrc_params = nokia_get_sdram_timings();
|
||||
omap2_init_common_devices(sdrc_params, sdrc_params);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
{ .reg_offset = OMAP_MUX_TERMINATOR },
|
||||
@ -140,23 +131,23 @@ static struct omap_board_mux board_mux[] __initdata = {
|
||||
|
||||
static void __init rm680_init(void)
|
||||
{
|
||||
struct omap_sdrc_params *sdrc_params;
|
||||
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
omap_serial_init();
|
||||
|
||||
sdrc_params = nokia_get_sdram_timings();
|
||||
omap_sdrc_init(sdrc_params, sdrc_params);
|
||||
|
||||
usb_musb_init(NULL);
|
||||
rm680_peripherals_init();
|
||||
}
|
||||
|
||||
static void __init rm680_map_io(void)
|
||||
{
|
||||
omap2_set_globals_3xxx();
|
||||
omap34xx_map_common_io();
|
||||
}
|
||||
|
||||
MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = rm680_map_io,
|
||||
.init_early = rm680_init_early,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap3630_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = rm680_init,
|
||||
.timer = &omap3_timer,
|
||||
|
@ -102,15 +102,6 @@ static struct omap_board_config_kernel rx51_config[] = {
|
||||
{ OMAP_TAG_LCD, &rx51_lcd_config },
|
||||
};
|
||||
|
||||
static void __init rx51_init_early(void)
|
||||
{
|
||||
struct omap_sdrc_params *sdrc_params;
|
||||
|
||||
omap2_init_common_infrastructure();
|
||||
sdrc_params = nokia_get_sdram_timings();
|
||||
omap2_init_common_devices(sdrc_params, sdrc_params);
|
||||
}
|
||||
|
||||
extern void __init rx51_peripherals_init(void);
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
@ -127,11 +118,17 @@ static struct omap_musb_board_data musb_board_data = {
|
||||
|
||||
static void __init rx51_init(void)
|
||||
{
|
||||
struct omap_sdrc_params *sdrc_params;
|
||||
|
||||
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
|
||||
omap_board_config = rx51_config;
|
||||
omap_board_config_size = ARRAY_SIZE(rx51_config);
|
||||
omap3_pm_init_cpuidle(rx51_cpuidle_params);
|
||||
omap_serial_init();
|
||||
|
||||
sdrc_params = nokia_get_sdram_timings();
|
||||
omap_sdrc_init(sdrc_params, sdrc_params);
|
||||
|
||||
usb_musb_init(&musb_board_data);
|
||||
rx51_peripherals_init();
|
||||
|
||||
@ -142,12 +139,6 @@ static void __init rx51_init(void)
|
||||
platform_device_register(&leds_gpio);
|
||||
}
|
||||
|
||||
static void __init rx51_map_io(void)
|
||||
{
|
||||
omap2_set_globals_3xxx();
|
||||
omap34xx_map_common_io();
|
||||
}
|
||||
|
||||
static void __init rx51_reserve(void)
|
||||
{
|
||||
rx51_video_mem_init();
|
||||
@ -158,8 +149,8 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
|
||||
/* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = rx51_reserve,
|
||||
.map_io = rx51_map_io,
|
||||
.init_early = rx51_init_early,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap3430_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = rx51_init,
|
||||
.timer = &omap3_timer,
|
||||
|
@ -27,15 +27,10 @@
|
||||
static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
|
||||
};
|
||||
|
||||
static void __init ti8168_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
omap2_init_common_devices(NULL, NULL);
|
||||
}
|
||||
|
||||
static void __init ti8168_evm_init(void)
|
||||
{
|
||||
omap_serial_init();
|
||||
omap_sdrc_init(NULL, NULL);
|
||||
omap_board_config = ti8168_evm_config;
|
||||
omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
|
||||
}
|
||||
@ -50,7 +45,7 @@ MACHINE_START(TI8168EVM, "ti8168evm")
|
||||
/* Maintainer: Texas Instruments */
|
||||
.boot_params = 0x80000100,
|
||||
.map_io = ti8168_evm_map_io,
|
||||
.init_early = ti8168_init_early,
|
||||
.init_early = ti816x_init_early,
|
||||
.init_irq = ti816x_init_irq,
|
||||
.timer = &omap3_timer,
|
||||
.init_machine = ti8168_evm_init,
|
||||
|
@ -34,17 +34,6 @@
|
||||
|
||||
#define ZOOM3_EHCI_RESET_GPIO 64
|
||||
|
||||
static void __init omap_zoom_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
if (machine_is_omap_zoom2())
|
||||
omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
else if (machine_is_omap_zoom3())
|
||||
omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
|
||||
h8mbx00u0mer0em_sdrc_params);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX
|
||||
static struct omap_board_mux board_mux[] __initdata = {
|
||||
/* WLAN IRQ - GPIO 162 */
|
||||
@ -129,6 +118,14 @@ static void __init omap_zoom_init(void)
|
||||
ZOOM_NAND_CS, NAND_BUSWIDTH_16);
|
||||
zoom_debugboard_init();
|
||||
zoom_peripherals_init();
|
||||
|
||||
if (machine_is_omap_zoom2())
|
||||
omap_sdrc_init(mt46h32m32lf6_sdrc_params,
|
||||
mt46h32m32lf6_sdrc_params);
|
||||
else if (machine_is_omap_zoom3())
|
||||
omap_sdrc_init(h8mbx00u0mer0em_sdrc_params,
|
||||
h8mbx00u0mer0em_sdrc_params);
|
||||
|
||||
zoom_display_init();
|
||||
}
|
||||
|
||||
@ -136,7 +133,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap_zoom_init_early,
|
||||
.init_early = omap3430_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = omap_zoom_init,
|
||||
.timer = &omap3_timer,
|
||||
@ -146,7 +143,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
|
||||
.boot_params = 0x80000100,
|
||||
.reserve = omap_reserve,
|
||||
.map_io = omap3_map_io,
|
||||
.init_early = omap_zoom_init_early,
|
||||
.init_early = omap3630_init_early,
|
||||
.init_irq = omap3_init_irq,
|
||||
.init_machine = omap_zoom_init,
|
||||
.timer = &omap3_timer,
|
||||
|
@ -1898,6 +1898,54 @@ static struct omap_clk omap2420_clks[] = {
|
||||
CLK(NULL, "pka_ick", &pka_ick, CK_242X),
|
||||
CLK(NULL, "usb_fck", &usb_fck, CK_242X),
|
||||
CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
|
||||
CLK("omap_timer.1", "fck", &gpt1_fck, CK_242X),
|
||||
CLK("omap_timer.2", "fck", &gpt2_fck, CK_242X),
|
||||
CLK("omap_timer.3", "fck", &gpt3_fck, CK_242X),
|
||||
CLK("omap_timer.4", "fck", &gpt4_fck, CK_242X),
|
||||
CLK("omap_timer.5", "fck", &gpt5_fck, CK_242X),
|
||||
CLK("omap_timer.6", "fck", &gpt6_fck, CK_242X),
|
||||
CLK("omap_timer.7", "fck", &gpt7_fck, CK_242X),
|
||||
CLK("omap_timer.8", "fck", &gpt8_fck, CK_242X),
|
||||
CLK("omap_timer.9", "fck", &gpt9_fck, CK_242X),
|
||||
CLK("omap_timer.10", "fck", &gpt10_fck, CK_242X),
|
||||
CLK("omap_timer.11", "fck", &gpt11_fck, CK_242X),
|
||||
CLK("omap_timer.12", "fck", &gpt12_fck, CK_242X),
|
||||
CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.4", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.5", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.6", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.7", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.8", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.9", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.10", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.11", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.12", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.1", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.2", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.3", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.4", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.5", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.6", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.7", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.8", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.9", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.10", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.11", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.12", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.1", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.2", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.3", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.4", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.5", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.6", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.7", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.8", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.9", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.10", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.11", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.12", "alt_ck", &alt_ck, CK_243X),
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -1998,6 +1998,54 @@ static struct omap_clk omap2430_clks[] = {
|
||||
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
|
||||
CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
|
||||
CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
|
||||
CLK("omap_timer.1", "fck", &gpt1_fck, CK_243X),
|
||||
CLK("omap_timer.2", "fck", &gpt2_fck, CK_243X),
|
||||
CLK("omap_timer.3", "fck", &gpt3_fck, CK_243X),
|
||||
CLK("omap_timer.4", "fck", &gpt4_fck, CK_243X),
|
||||
CLK("omap_timer.5", "fck", &gpt5_fck, CK_243X),
|
||||
CLK("omap_timer.6", "fck", &gpt6_fck, CK_243X),
|
||||
CLK("omap_timer.7", "fck", &gpt7_fck, CK_243X),
|
||||
CLK("omap_timer.8", "fck", &gpt8_fck, CK_243X),
|
||||
CLK("omap_timer.9", "fck", &gpt9_fck, CK_243X),
|
||||
CLK("omap_timer.10", "fck", &gpt10_fck, CK_243X),
|
||||
CLK("omap_timer.11", "fck", &gpt11_fck, CK_243X),
|
||||
CLK("omap_timer.12", "fck", &gpt12_fck, CK_243X),
|
||||
CLK("omap_timer.1", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.2", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.3", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.4", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.5", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.6", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.7", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.8", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.9", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.10", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.11", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.12", "32k_ck", &func_32k_ck, CK_243X),
|
||||
CLK("omap_timer.1", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.2", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.3", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.4", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.5", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.6", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.7", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.8", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.9", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.10", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.11", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.12", "sys_ck", &sys_ck, CK_243X),
|
||||
CLK("omap_timer.1", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.2", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.3", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.4", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.5", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.6", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.7", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.8", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.9", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.10", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.11", "alt_ck", &alt_ck, CK_243X),
|
||||
CLK("omap_timer.12", "alt_ck", &alt_ck, CK_243X),
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -3464,6 +3464,42 @@ static struct omap_clk omap3xxx_clks[] = {
|
||||
CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
|
||||
CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
|
||||
CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
|
||||
CLK("omap_timer.1", "fck", &gpt1_fck, CK_3XXX),
|
||||
CLK("omap_timer.2", "fck", &gpt2_fck, CK_3XXX),
|
||||
CLK("omap_timer.3", "fck", &gpt3_fck, CK_3XXX),
|
||||
CLK("omap_timer.4", "fck", &gpt4_fck, CK_3XXX),
|
||||
CLK("omap_timer.5", "fck", &gpt5_fck, CK_3XXX),
|
||||
CLK("omap_timer.6", "fck", &gpt6_fck, CK_3XXX),
|
||||
CLK("omap_timer.7", "fck", &gpt7_fck, CK_3XXX),
|
||||
CLK("omap_timer.8", "fck", &gpt8_fck, CK_3XXX),
|
||||
CLK("omap_timer.9", "fck", &gpt9_fck, CK_3XXX),
|
||||
CLK("omap_timer.10", "fck", &gpt10_fck, CK_3XXX),
|
||||
CLK("omap_timer.11", "fck", &gpt11_fck, CK_3XXX),
|
||||
CLK("omap_timer.12", "fck", &gpt12_fck, CK_3XXX),
|
||||
CLK("omap_timer.1", "32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
CLK("omap_timer.2", "32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
CLK("omap_timer.3", "32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
CLK("omap_timer.4", "32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
CLK("omap_timer.5", "32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
CLK("omap_timer.6", "32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
CLK("omap_timer.7", "32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
CLK("omap_timer.8", "32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
CLK("omap_timer.9", "32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
CLK("omap_timer.10", "32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
CLK("omap_timer.11", "32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
CLK("omap_timer.12", "32k_ck", &omap_32k_fck, CK_3XXX),
|
||||
CLK("omap_timer.1", "sys_ck", &sys_ck, CK_3XXX),
|
||||
CLK("omap_timer.2", "sys_ck", &sys_ck, CK_3XXX),
|
||||
CLK("omap_timer.3", "sys_ck", &sys_ck, CK_3XXX),
|
||||
CLK("omap_timer.4", "sys_ck", &sys_ck, CK_3XXX),
|
||||
CLK("omap_timer.5", "sys_ck", &sys_ck, CK_3XXX),
|
||||
CLK("omap_timer.6", "sys_ck", &sys_ck, CK_3XXX),
|
||||
CLK("omap_timer.7", "sys_ck", &sys_ck, CK_3XXX),
|
||||
CLK("omap_timer.8", "sys_ck", &sys_ck, CK_3XXX),
|
||||
CLK("omap_timer.9", "sys_ck", &sys_ck, CK_3XXX),
|
||||
CLK("omap_timer.10", "sys_ck", &sys_ck, CK_3XXX),
|
||||
CLK("omap_timer.11", "sys_ck", &sys_ck, CK_3XXX),
|
||||
CLK("omap_timer.12", "sys_ck", &sys_ck, CK_3XXX),
|
||||
};
|
||||
|
||||
|
||||
@ -3472,7 +3508,16 @@ int __init omap3xxx_clk_init(void)
|
||||
struct omap_clk *c;
|
||||
u32 cpu_clkflg = 0;
|
||||
|
||||
if (cpu_is_omap3517()) {
|
||||
/*
|
||||
* 3505 must be tested before 3517, since 3517 returns true
|
||||
* for both AM3517 chips and AM3517 family chips, which
|
||||
* includes 3505. Unfortunately there's no obvious family
|
||||
* test for 3517/3505 :-(
|
||||
*/
|
||||
if (cpu_is_omap3505()) {
|
||||
cpu_mask = RATE_IN_34XX;
|
||||
cpu_clkflg = CK_3505;
|
||||
} else if (cpu_is_omap3517()) {
|
||||
cpu_mask = RATE_IN_34XX;
|
||||
cpu_clkflg = CK_3517;
|
||||
} else if (cpu_is_omap3505()) {
|
||||
|
@ -3363,6 +3363,39 @@ static struct omap_clk omap44xx_clks[] = {
|
||||
CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
|
||||
CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
|
||||
CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
|
||||
CLK("omap_timer.1", "fck", &timer1_fck, CK_443X),
|
||||
CLK("omap_timer.2", "fck", &timer2_fck, CK_443X),
|
||||
CLK("omap_timer.3", "fck", &timer3_fck, CK_443X),
|
||||
CLK("omap_timer.4", "fck", &timer4_fck, CK_443X),
|
||||
CLK("omap_timer.5", "fck", &timer5_fck, CK_443X),
|
||||
CLK("omap_timer.6", "fck", &timer6_fck, CK_443X),
|
||||
CLK("omap_timer.7", "fck", &timer7_fck, CK_443X),
|
||||
CLK("omap_timer.8", "fck", &timer8_fck, CK_443X),
|
||||
CLK("omap_timer.9", "fck", &timer9_fck, CK_443X),
|
||||
CLK("omap_timer.10", "fck", &timer10_fck, CK_443X),
|
||||
CLK("omap_timer.11", "fck", &timer11_fck, CK_443X),
|
||||
CLK("omap_timer.1", "32k_ck", &sys_32k_ck, CK_443X),
|
||||
CLK("omap_timer.2", "32k_ck", &sys_32k_ck, CK_443X),
|
||||
CLK("omap_timer.3", "32k_ck", &sys_32k_ck, CK_443X),
|
||||
CLK("omap_timer.4", "32k_ck", &sys_32k_ck, CK_443X),
|
||||
CLK("omap_timer.5", "32k_ck", &sys_32k_ck, CK_443X),
|
||||
CLK("omap_timer.6", "32k_ck", &sys_32k_ck, CK_443X),
|
||||
CLK("omap_timer.7", "32k_ck", &sys_32k_ck, CK_443X),
|
||||
CLK("omap_timer.8", "32k_ck", &sys_32k_ck, CK_443X),
|
||||
CLK("omap_timer.9", "32k_ck", &sys_32k_ck, CK_443X),
|
||||
CLK("omap_timer.10", "32k_ck", &sys_32k_ck, CK_443X),
|
||||
CLK("omap_timer.11", "32k_ck", &sys_32k_ck, CK_443X),
|
||||
CLK("omap_timer.1", "sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("omap_timer.2", "sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("omap_timer.3", "sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("omap_timer.4", "sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("omap_timer.9", "sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("omap_timer.10", "sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("omap_timer.11", "sys_ck", &sys_clkin_ck, CK_443X),
|
||||
CLK("omap_timer.5", "sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("omap_timer.6", "sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("omap_timer.7", "sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
CLK("omap_timer.8", "sys_ck", &syc_clk_div_ck, CK_443X),
|
||||
};
|
||||
|
||||
int __init omap4xxx_clk_init(void)
|
||||
|
@ -73,9 +73,6 @@ static int _clkdm_register(struct clockdomain *clkdm)
|
||||
if (!clkdm || !clkdm->name)
|
||||
return -EINVAL;
|
||||
|
||||
if (!omap_chip_is(clkdm->omap_chip))
|
||||
return -EINVAL;
|
||||
|
||||
pwrdm = pwrdm_lookup(clkdm->pwrdm.name);
|
||||
if (!pwrdm) {
|
||||
pr_err("clockdomain: %s: powerdomain %s does not exist\n",
|
||||
@ -105,13 +102,10 @@ static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
|
||||
{
|
||||
struct clkdm_dep *cd;
|
||||
|
||||
if (!clkdm || !deps || !omap_chip_is(clkdm->omap_chip))
|
||||
if (!clkdm || !deps)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
for (cd = deps; cd->clkdm_name; cd++) {
|
||||
if (!omap_chip_is(cd->omap_chip))
|
||||
continue;
|
||||
|
||||
if (!cd->clkdm && cd->clkdm_name)
|
||||
cd->clkdm = _clkdm_lookup(cd->clkdm_name);
|
||||
|
||||
@ -148,9 +142,6 @@ static void _autodep_lookup(struct clkdm_autodep *autodep)
|
||||
if (!autodep)
|
||||
return;
|
||||
|
||||
if (!omap_chip_is(autodep->omap_chip))
|
||||
return;
|
||||
|
||||
clkdm = clkdm_lookup(autodep->clkdm.name);
|
||||
if (!clkdm) {
|
||||
pr_err("clockdomain: autodeps: clockdomain %s does not exist\n",
|
||||
@ -182,9 +173,6 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm)
|
||||
if (IS_ERR(autodep->clkdm.ptr))
|
||||
continue;
|
||||
|
||||
if (!omap_chip_is(autodep->omap_chip))
|
||||
continue;
|
||||
|
||||
pr_debug("clockdomain: adding %s sleepdep/wkdep for "
|
||||
"clkdm %s\n", autodep->clkdm.ptr->name,
|
||||
clkdm->name);
|
||||
@ -216,9 +204,6 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm)
|
||||
if (IS_ERR(autodep->clkdm.ptr))
|
||||
continue;
|
||||
|
||||
if (!omap_chip_is(autodep->omap_chip))
|
||||
continue;
|
||||
|
||||
pr_debug("clockdomain: removing %s sleepdep/wkdep for "
|
||||
"clkdm %s\n", autodep->clkdm.ptr->name,
|
||||
clkdm->name);
|
||||
@ -243,8 +228,6 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm,
|
||||
struct clkdm_dep *cd;
|
||||
|
||||
for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
|
||||
if (!omap_chip_is(cd->omap_chip))
|
||||
continue;
|
||||
if (cd->clkdm)
|
||||
continue;
|
||||
cd->clkdm = _clkdm_lookup(cd->clkdm_name);
|
||||
@ -257,43 +240,113 @@ static void _resolve_clkdm_deps(struct clockdomain *clkdm,
|
||||
/* Public functions */
|
||||
|
||||
/**
|
||||
* clkdm_init - set up the clockdomain layer
|
||||
* @clkdms: optional pointer to an array of clockdomains to register
|
||||
* @init_autodeps: optional pointer to an array of autodeps to register
|
||||
* @custom_funcs: func pointers for arch specific implementations
|
||||
* clkdm_register_platform_funcs - register clockdomain implementation fns
|
||||
* @co: func pointers for arch specific implementations
|
||||
*
|
||||
* Set up internal state. If a pointer to an array of clockdomains
|
||||
* @clkdms was supplied, loop through the list of clockdomains,
|
||||
* register all that are available on the current platform. Similarly,
|
||||
* if a pointer to an array of clockdomain autodependencies
|
||||
* @init_autodeps was provided, register those. No return value.
|
||||
* Register the list of function pointers used to implement the
|
||||
* clockdomain functions on different OMAP SoCs. Should be called
|
||||
* before any other clkdm_register*() function. Returns -EINVAL if
|
||||
* @co is null, -EEXIST if platform functions have already been
|
||||
* registered, or 0 upon success.
|
||||
*/
|
||||
void clkdm_init(struct clockdomain **clkdms,
|
||||
struct clkdm_autodep *init_autodeps,
|
||||
struct clkdm_ops *custom_funcs)
|
||||
int clkdm_register_platform_funcs(struct clkdm_ops *co)
|
||||
{
|
||||
if (!co)
|
||||
return -EINVAL;
|
||||
|
||||
if (arch_clkdm)
|
||||
return -EEXIST;
|
||||
|
||||
arch_clkdm = co;
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
/**
|
||||
* clkdm_register_clkdms - register SoC clockdomains
|
||||
* @cs: pointer to an array of struct clockdomain to register
|
||||
*
|
||||
* Register the clockdomains available on a particular OMAP SoC. Must
|
||||
* be called after clkdm_register_platform_funcs(). May be called
|
||||
* multiple times. Returns -EACCES if called before
|
||||
* clkdm_register_platform_funcs(); -EINVAL if the argument @cs is
|
||||
* null; or 0 upon success.
|
||||
*/
|
||||
int clkdm_register_clkdms(struct clockdomain **cs)
|
||||
{
|
||||
struct clockdomain **c = NULL;
|
||||
struct clockdomain *clkdm;
|
||||
struct clkdm_autodep *autodep = NULL;
|
||||
|
||||
if (!custom_funcs)
|
||||
WARN(1, "No custom clkdm functions registered\n");
|
||||
else
|
||||
arch_clkdm = custom_funcs;
|
||||
if (!arch_clkdm)
|
||||
return -EACCES;
|
||||
|
||||
if (clkdms)
|
||||
for (c = clkdms; *c; c++)
|
||||
_clkdm_register(*c);
|
||||
if (!cs)
|
||||
return -EINVAL;
|
||||
|
||||
for (c = cs; *c; c++)
|
||||
_clkdm_register(*c);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* clkdm_register_autodeps - register autodeps (if required)
|
||||
* @ia: pointer to a static array of struct clkdm_autodep to register
|
||||
*
|
||||
* Register clockdomain "automatic dependencies." These are
|
||||
* clockdomain wakeup and sleep dependencies that are automatically
|
||||
* added whenever the first clock inside a clockdomain is enabled, and
|
||||
* removed whenever the last clock inside a clockdomain is disabled.
|
||||
* These are currently only used on OMAP3 devices, and are deprecated,
|
||||
* since they waste energy. However, until the OMAP2/3 IP block
|
||||
* enable/disable sequence can be converted to match the OMAP4
|
||||
* sequence, they are needed.
|
||||
*
|
||||
* Must be called only after all of the SoC clockdomains are
|
||||
* registered, since the function will resolve autodep clockdomain
|
||||
* names into clockdomain pointers.
|
||||
*
|
||||
* The struct clkdm_autodep @ia array must be static, as this function
|
||||
* does not copy the array elements.
|
||||
*
|
||||
* Returns -EACCES if called before any clockdomains have been
|
||||
* registered, -EINVAL if called with a null @ia argument, -EEXIST if
|
||||
* autodeps have already been registered, or 0 upon success.
|
||||
*/
|
||||
int clkdm_register_autodeps(struct clkdm_autodep *ia)
|
||||
{
|
||||
struct clkdm_autodep *a = NULL;
|
||||
|
||||
if (list_empty(&clkdm_list))
|
||||
return -EACCES;
|
||||
|
||||
if (!ia)
|
||||
return -EINVAL;
|
||||
|
||||
autodeps = init_autodeps;
|
||||
if (autodeps)
|
||||
for (autodep = autodeps; autodep->clkdm.ptr; autodep++)
|
||||
_autodep_lookup(autodep);
|
||||
return -EEXIST;
|
||||
|
||||
autodeps = ia;
|
||||
for (a = autodeps; a->clkdm.ptr; a++)
|
||||
_autodep_lookup(a);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* clkdm_complete_init - set up the clockdomain layer
|
||||
*
|
||||
* Put all clockdomains into software-supervised mode; PM code should
|
||||
* later enable hardware-supervised mode as appropriate. Must be
|
||||
* called after clkdm_register_clkdms(). Returns -EACCES if called
|
||||
* before clkdm_register_clkdms(), or 0 upon success.
|
||||
*/
|
||||
int clkdm_complete_init(void)
|
||||
{
|
||||
struct clockdomain *clkdm;
|
||||
|
||||
if (list_empty(&clkdm_list))
|
||||
return -EACCES;
|
||||
|
||||
/*
|
||||
* Put all clockdomains into software-supervised mode; PM code
|
||||
* should later enable hardware-supervised mode as appropriate
|
||||
*/
|
||||
list_for_each_entry(clkdm, &clkdm_list, node) {
|
||||
if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
|
||||
clkdm_wakeup(clkdm);
|
||||
@ -306,6 +359,8 @@ void clkdm_init(struct clockdomain **clkdms,
|
||||
_resolve_clkdm_deps(clkdm, clkdm->sleepdep_srcs);
|
||||
clkdm_clear_all_sleepdeps(clkdm);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -45,7 +45,6 @@
|
||||
/**
|
||||
* struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
|
||||
* @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
|
||||
* @omap_chip: OMAP chip types that this autodep is valid on
|
||||
*
|
||||
* A clockdomain that should have wkdeps and sleepdeps added when a
|
||||
* clockdomain should stay active in hwsup mode; and conversely,
|
||||
@ -60,14 +59,12 @@ struct clkdm_autodep {
|
||||
const char *name;
|
||||
struct clockdomain *ptr;
|
||||
} clkdm;
|
||||
const struct omap_chip_id omap_chip;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct clkdm_dep - encode dependencies between clockdomains
|
||||
* @clkdm_name: clockdomain name
|
||||
* @clkdm: pointer to the struct clockdomain of @clkdm_name
|
||||
* @omap_chip: OMAP chip types that this dependency is valid on
|
||||
* @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake
|
||||
* @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle
|
||||
*
|
||||
@ -81,7 +78,6 @@ struct clkdm_dep {
|
||||
struct clockdomain *clkdm;
|
||||
atomic_t wkdep_usecount;
|
||||
atomic_t sleepdep_usecount;
|
||||
const struct omap_chip_id omap_chip;
|
||||
};
|
||||
|
||||
/* Possible flags for struct clockdomain._flags */
|
||||
@ -101,7 +97,6 @@ struct clkdm_dep {
|
||||
* @clkdm_offs: (OMAP4 only) CM clockdomain register offset
|
||||
* @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
|
||||
* @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
|
||||
* @omap_chip: OMAP chip types that this clockdomain is valid on
|
||||
* @usecount: Usecount tracking
|
||||
* @node: list_head to link all clockdomains together
|
||||
*
|
||||
@ -126,7 +121,6 @@ struct clockdomain {
|
||||
const u16 clkdm_offs;
|
||||
struct clkdm_dep *wkdep_srcs;
|
||||
struct clkdm_dep *sleepdep_srcs;
|
||||
const struct omap_chip_id omap_chip;
|
||||
atomic_t usecount;
|
||||
struct list_head node;
|
||||
spinlock_t lock;
|
||||
@ -166,8 +160,11 @@ struct clkdm_ops {
|
||||
int (*clkdm_clk_disable)(struct clockdomain *clkdm);
|
||||
};
|
||||
|
||||
void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps,
|
||||
struct clkdm_ops *custom_funcs);
|
||||
int clkdm_register_platform_funcs(struct clkdm_ops *co);
|
||||
int clkdm_register_autodeps(struct clkdm_autodep *ia);
|
||||
int clkdm_register_clkdms(struct clockdomain **c);
|
||||
int clkdm_complete_init(void);
|
||||
|
||||
struct clockdomain *clkdm_lookup(const char *name);
|
||||
|
||||
int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user),
|
||||
@ -195,7 +192,8 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
|
||||
int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
|
||||
int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
|
||||
|
||||
extern void __init omap2xxx_clockdomains_init(void);
|
||||
extern void __init omap242x_clockdomains_init(void);
|
||||
extern void __init omap243x_clockdomains_init(void);
|
||||
extern void __init omap3xxx_clockdomains_init(void);
|
||||
extern void __init omap44xx_clockdomains_init(void);
|
||||
extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
|
||||
@ -205,4 +203,10 @@ extern struct clkdm_ops omap2_clkdm_operations;
|
||||
extern struct clkdm_ops omap3_clkdm_operations;
|
||||
extern struct clkdm_ops omap4_clkdm_operations;
|
||||
|
||||
extern struct clkdm_dep gfx_24xx_wkdeps[];
|
||||
extern struct clkdm_dep dsp_24xx_wkdeps[];
|
||||
extern struct clockdomain wkup_common_clkdm;
|
||||
extern struct clockdomain prm_common_clkdm;
|
||||
extern struct clockdomain cm_common_clkdm;
|
||||
|
||||
#endif
|
||||
|
@ -52,8 +52,6 @@ static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
|
||||
u32 mask = 0;
|
||||
|
||||
for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
|
||||
if (!omap_chip_is(cd->omap_chip))
|
||||
continue;
|
||||
if (!cd->clkdm)
|
||||
continue; /* only happens if data is erroneous */
|
||||
|
||||
@ -98,8 +96,6 @@ static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
|
||||
u32 mask = 0;
|
||||
|
||||
for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
|
||||
if (!omap_chip_is(cd->omap_chip))
|
||||
continue;
|
||||
if (!cd->clkdm)
|
||||
continue; /* only happens if data is erroneous */
|
||||
|
||||
|
@ -52,8 +52,6 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
|
||||
u32 mask = 0;
|
||||
|
||||
for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
|
||||
if (!omap_chip_is(cd->omap_chip))
|
||||
continue;
|
||||
if (!cd->clkdm)
|
||||
continue; /* only happens if data is erroneous */
|
||||
|
||||
|
154
arch/arm/mach-omap2/clockdomains2420_data.c
Normal file
154
arch/arm/mach-omap2/clockdomains2420_data.c
Normal file
@ -0,0 +1,154 @@
|
||||
/*
|
||||
* OMAP2420 clockdomains
|
||||
*
|
||||
* Copyright (C) 2008-2011 Texas Instruments, Inc.
|
||||
* Copyright (C) 2008-2010 Nokia Corporation
|
||||
*
|
||||
* Paul Walmsley, Jouni Högander
|
||||
*
|
||||
* This file contains clockdomains and clockdomain wakeup dependencies
|
||||
* for OMAP2420 chips. Some notes:
|
||||
*
|
||||
* A useful validation rule for struct clockdomain: Any clockdomain
|
||||
* referenced by a wkdep_srcs must have a dep_bit assigned. So
|
||||
* wkdep_srcs are really just software-controllable dependencies.
|
||||
* Non-software-controllable dependencies do exist, but they are not
|
||||
* encoded below (yet).
|
||||
*
|
||||
* 24xx does not support programmable sleep dependencies (SLEEPDEP)
|
||||
*
|
||||
* The overly-specific dep_bit names are due to a bit name collision
|
||||
* with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
|
||||
* value are the same for all powerdomains: 2
|
||||
*
|
||||
* XXX should dep_bit be a mask, so we can test to see if it is 0 as a
|
||||
* sanity check?
|
||||
* XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
|
||||
*/
|
||||
|
||||
/*
|
||||
* To-Do List
|
||||
* -> Port the Sleep/Wakeup dependencies for the domains
|
||||
* from the Power domain framework
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include "clockdomain.h"
|
||||
#include "prm2xxx_3xxx.h"
|
||||
#include "cm2xxx_3xxx.h"
|
||||
#include "cm-regbits-24xx.h"
|
||||
#include "prm-regbits-24xx.h"
|
||||
|
||||
/*
|
||||
* Clockdomain dependencies for wkdeps
|
||||
*
|
||||
* XXX Hardware dependencies (e.g., dependencies that cannot be
|
||||
* changed in software) are not included here yet, but should be.
|
||||
*/
|
||||
|
||||
/* Wakeup dependency source arrays */
|
||||
|
||||
/* 2420-specific possible wakeup dependencies */
|
||||
|
||||
/* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP */
|
||||
static struct clkdm_dep mpu_2420_wkdeps[] = {
|
||||
{ .clkdm_name = "core_l3_clkdm" },
|
||||
{ .clkdm_name = "core_l4_clkdm" },
|
||||
{ .clkdm_name = "dsp_clkdm" },
|
||||
{ .clkdm_name = "wkup_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP */
|
||||
static struct clkdm_dep core_2420_wkdeps[] = {
|
||||
{ .clkdm_name = "dsp_clkdm" },
|
||||
{ .clkdm_name = "gfx_clkdm" },
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ .clkdm_name = "wkup_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/*
|
||||
* 2420-only clockdomains
|
||||
*/
|
||||
|
||||
static struct clockdomain mpu_2420_clkdm = {
|
||||
.name = "mpu_clkdm",
|
||||
.pwrdm = { .name = "mpu_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.wkdep_srcs = mpu_2420_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain iva1_2420_clkdm = {
|
||||
.name = "iva1_clkdm",
|
||||
.pwrdm = { .name = "dsp_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
|
||||
.wkdep_srcs = dsp_24xx_wkdeps,
|
||||
.clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain dsp_2420_clkdm = {
|
||||
.name = "dsp_clkdm",
|
||||
.pwrdm = { .name = "dsp_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain gfx_2420_clkdm = {
|
||||
.name = "gfx_clkdm",
|
||||
.pwrdm = { .name = "gfx_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = gfx_24xx_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain core_l3_2420_clkdm = {
|
||||
.name = "core_l3_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.wkdep_srcs = core_2420_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain core_l4_2420_clkdm = {
|
||||
.name = "core_l4_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.wkdep_srcs = core_2420_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain dss_2420_clkdm = {
|
||||
.name = "dss_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain *clockdomains_omap242x[] __initdata = {
|
||||
&wkup_common_clkdm,
|
||||
&cm_common_clkdm,
|
||||
&prm_common_clkdm,
|
||||
&mpu_2420_clkdm,
|
||||
&iva1_2420_clkdm,
|
||||
&dsp_2420_clkdm,
|
||||
&gfx_2420_clkdm,
|
||||
&core_l3_2420_clkdm,
|
||||
&core_l4_2420_clkdm,
|
||||
&dss_2420_clkdm,
|
||||
NULL,
|
||||
};
|
||||
|
||||
void __init omap242x_clockdomains_init(void)
|
||||
{
|
||||
if (!cpu_is_omap242x())
|
||||
return;
|
||||
|
||||
clkdm_register_platform_funcs(&omap2_clkdm_operations);
|
||||
clkdm_register_clkdms(clockdomains_omap242x);
|
||||
clkdm_complete_init();
|
||||
}
|
181
arch/arm/mach-omap2/clockdomains2430_data.c
Normal file
181
arch/arm/mach-omap2/clockdomains2430_data.c
Normal file
@ -0,0 +1,181 @@
|
||||
/*
|
||||
* OMAP2xxx clockdomains
|
||||
*
|
||||
* Copyright (C) 2008-2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2008-2010 Nokia Corporation
|
||||
*
|
||||
* Paul Walmsley, Jouni Högander
|
||||
*
|
||||
* This file contains clockdomains and clockdomain wakeup dependencies
|
||||
* for OMAP2xxx chips. Some notes:
|
||||
*
|
||||
* A useful validation rule for struct clockdomain: Any clockdomain
|
||||
* referenced by a wkdep_srcs must have a dep_bit assigned. So
|
||||
* wkdep_srcs are really just software-controllable dependencies.
|
||||
* Non-software-controllable dependencies do exist, but they are not
|
||||
* encoded below (yet).
|
||||
*
|
||||
* 24xx does not support programmable sleep dependencies (SLEEPDEP)
|
||||
*
|
||||
* The overly-specific dep_bit names are due to a bit name collision
|
||||
* with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
|
||||
* value are the same for all powerdomains: 2
|
||||
*
|
||||
* XXX should dep_bit be a mask, so we can test to see if it is 0 as a
|
||||
* sanity check?
|
||||
* XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
|
||||
*/
|
||||
|
||||
/*
|
||||
* To-Do List
|
||||
* -> Port the Sleep/Wakeup dependencies for the domains
|
||||
* from the Power domain framework
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include "clockdomain.h"
|
||||
#include "prm2xxx_3xxx.h"
|
||||
#include "cm2xxx_3xxx.h"
|
||||
#include "cm-regbits-24xx.h"
|
||||
#include "prm-regbits-24xx.h"
|
||||
|
||||
/*
|
||||
* Clockdomain dependencies for wkdeps
|
||||
*
|
||||
* XXX Hardware dependencies (e.g., dependencies that cannot be
|
||||
* changed in software) are not included here yet, but should be.
|
||||
*/
|
||||
|
||||
/* Wakeup dependency source arrays */
|
||||
|
||||
/* 2430-specific possible wakeup dependencies */
|
||||
|
||||
/* 2430 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP, MDM */
|
||||
static struct clkdm_dep core_2430_wkdeps[] = {
|
||||
{ .clkdm_name = "dsp_clkdm" },
|
||||
{ .clkdm_name = "gfx_clkdm" },
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ .clkdm_name = "wkup_clkdm" },
|
||||
{ .clkdm_name = "mdm_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 2430 PM_WKDEP_MPU: CORE, DSP, WKUP, MDM */
|
||||
static struct clkdm_dep mpu_2430_wkdeps[] = {
|
||||
{ .clkdm_name = "core_l3_clkdm" },
|
||||
{ .clkdm_name = "core_l4_clkdm" },
|
||||
{ .clkdm_name = "dsp_clkdm" },
|
||||
{ .clkdm_name = "wkup_clkdm" },
|
||||
{ .clkdm_name = "mdm_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
|
||||
static struct clkdm_dep mdm_2430_wkdeps[] = {
|
||||
{ .clkdm_name = "core_l3_clkdm" },
|
||||
{ .clkdm_name = "core_l4_clkdm" },
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ .clkdm_name = "wkup_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/*
|
||||
* 2430-only clockdomains
|
||||
*/
|
||||
|
||||
static struct clockdomain mpu_2430_clkdm = {
|
||||
.name = "mpu_clkdm",
|
||||
.pwrdm = { .name = "mpu_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = mpu_2430_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
|
||||
};
|
||||
|
||||
/* Another case of bit name collisions between several registers: EN_MDM */
|
||||
static struct clockdomain mdm_clkdm = {
|
||||
.name = "mdm_clkdm",
|
||||
.pwrdm = { .name = "mdm_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
|
||||
.wkdep_srcs = mdm_2430_wkdeps,
|
||||
.clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain dsp_2430_clkdm = {
|
||||
.name = "dsp_clkdm",
|
||||
.pwrdm = { .name = "dsp_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
|
||||
.wkdep_srcs = dsp_24xx_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain gfx_2430_clkdm = {
|
||||
.name = "gfx_clkdm",
|
||||
.pwrdm = { .name = "gfx_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = gfx_24xx_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX add usecounting for clkdm dependencies, otherwise the presence
|
||||
* of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
|
||||
* could cause trouble
|
||||
*/
|
||||
static struct clockdomain core_l3_2430_clkdm = {
|
||||
.name = "core_l3_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.dep_bit = OMAP24XX_EN_CORE_SHIFT,
|
||||
.wkdep_srcs = core_2430_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX add usecounting for clkdm dependencies, otherwise the presence
|
||||
* of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
|
||||
* could cause trouble
|
||||
*/
|
||||
static struct clockdomain core_l4_2430_clkdm = {
|
||||
.name = "core_l4_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.dep_bit = OMAP24XX_EN_CORE_SHIFT,
|
||||
.wkdep_srcs = core_2430_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain dss_2430_clkdm = {
|
||||
.name = "dss_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain *clockdomains_omap243x[] __initdata = {
|
||||
&wkup_common_clkdm,
|
||||
&cm_common_clkdm,
|
||||
&prm_common_clkdm,
|
||||
&mpu_2430_clkdm,
|
||||
&mdm_clkdm,
|
||||
&dsp_2430_clkdm,
|
||||
&gfx_2430_clkdm,
|
||||
&core_l3_2430_clkdm,
|
||||
&core_l4_2430_clkdm,
|
||||
&dss_2430_clkdm,
|
||||
NULL,
|
||||
};
|
||||
|
||||
void __init omap243x_clockdomains_init(void)
|
||||
{
|
||||
if (!cpu_is_omap243x())
|
||||
return;
|
||||
|
||||
clkdm_register_platform_funcs(&omap2_clkdm_operations);
|
||||
clkdm_register_clkdms(clockdomains_omap243x);
|
||||
clkdm_complete_init();
|
||||
}
|
||||
|
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* OMAP2/3 clockdomains
|
||||
* OMAP2/3 clockdomain common data
|
||||
*
|
||||
* Copyright (C) 2008-2009 Texas Instruments, Inc.
|
||||
* Copyright (C) 2008-2011 Texas Instruments, Inc.
|
||||
* Copyright (C) 2008-2010 Nokia Corporation
|
||||
*
|
||||
* Paul Walmsley, Jouni Högander
|
||||
@ -51,374 +51,28 @@
|
||||
* changed in software) are not included here yet, but should be.
|
||||
*/
|
||||
|
||||
/* OMAP2/3-common wakeup dependencies */
|
||||
|
||||
/*
|
||||
* 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
|
||||
* 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
|
||||
* 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
|
||||
* These can share data since they will never be present simultaneously
|
||||
* on the same device.
|
||||
*/
|
||||
static struct clkdm_dep gfx_sgx_wkdeps[] = {
|
||||
{
|
||||
.clkdm_name = "core_l3_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "core_l4_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "iva2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
|
||||
CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "wkup_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
|
||||
CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
|
||||
/* 24XX-specific possible dependencies */
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2
|
||||
|
||||
/* Wakeup dependency source arrays */
|
||||
|
||||
/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
|
||||
static struct clkdm_dep dsp_24xx_wkdeps[] = {
|
||||
{
|
||||
.clkdm_name = "core_l3_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "core_l4_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "wkup_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
/* 2xxx-specific possible dependencies */
|
||||
|
||||
/* 2xxx PM_WKDEP_GFX: CORE, MPU, WKUP */
|
||||
struct clkdm_dep gfx_24xx_wkdeps[] = {
|
||||
{ .clkdm_name = "core_l3_clkdm" },
|
||||
{ .clkdm_name = "core_l4_clkdm" },
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ .clkdm_name = "wkup_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/*
|
||||
* 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
|
||||
* 2430 adds MDM
|
||||
*/
|
||||
static struct clkdm_dep mpu_24xx_wkdeps[] = {
|
||||
{
|
||||
.clkdm_name = "core_l3_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "core_l4_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "dsp_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "wkup_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "mdm_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
},
|
||||
/* 2xxx PM_WKDEP_DSP: CORE, MPU, WKUP */
|
||||
struct clkdm_dep dsp_24xx_wkdeps[] = {
|
||||
{ .clkdm_name = "core_l3_clkdm" },
|
||||
{ .clkdm_name = "core_l4_clkdm" },
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ .clkdm_name = "wkup_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/*
|
||||
* 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
|
||||
* 2430 adds MDM
|
||||
*/
|
||||
static struct clkdm_dep core_24xx_wkdeps[] = {
|
||||
{
|
||||
.clkdm_name = "dsp_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "gfx_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "wkup_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "mdm_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
#endif /* CONFIG_ARCH_OMAP2 */
|
||||
|
||||
/* 2430-specific possible wakeup dependencies */
|
||||
|
||||
#ifdef CONFIG_SOC_OMAP2430
|
||||
|
||||
/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
|
||||
static struct clkdm_dep mdm_2430_wkdeps[] = {
|
||||
{
|
||||
.clkdm_name = "core_l3_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "core_l4_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "wkup_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
#endif /* CONFIG_SOC_OMAP2430 */
|
||||
|
||||
|
||||
/* OMAP3-specific possible dependencies */
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
|
||||
/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
|
||||
static struct clkdm_dep per_wkdeps[] = {
|
||||
{
|
||||
.clkdm_name = "core_l3_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "core_l4_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "iva2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "wkup_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
|
||||
static struct clkdm_dep usbhost_wkdeps[] = {
|
||||
{
|
||||
.clkdm_name = "core_l3_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "core_l4_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "iva2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "wkup_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
|
||||
static struct clkdm_dep mpu_3xxx_wkdeps[] = {
|
||||
{
|
||||
.clkdm_name = "core_l3_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "core_l4_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "iva2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "dss_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "per_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
|
||||
static struct clkdm_dep iva2_wkdeps[] = {
|
||||
{
|
||||
.clkdm_name = "core_l3_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "core_l4_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "wkup_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "dss_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "per_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
|
||||
/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
|
||||
static struct clkdm_dep cam_wkdeps[] = {
|
||||
{
|
||||
.clkdm_name = "iva2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "wkup_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
|
||||
static struct clkdm_dep dss_wkdeps[] = {
|
||||
{
|
||||
.clkdm_name = "iva2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "wkup_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430: PM_WKDEP_NEON: MPU */
|
||||
static struct clkdm_dep neon_wkdeps[] = {
|
||||
{
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
|
||||
/* Sleep dependency source arrays for OMAP3-specific clkdms */
|
||||
|
||||
/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
|
||||
static struct clkdm_dep dss_sleepdeps[] = {
|
||||
{
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "iva2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
|
||||
static struct clkdm_dep per_sleepdeps[] = {
|
||||
{
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "iva2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
|
||||
static struct clkdm_dep usbhost_sleepdeps[] = {
|
||||
{
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "iva2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430: CM_SLEEPDEP_CAM: MPU */
|
||||
static struct clkdm_dep cam_sleepdeps[] = {
|
||||
{
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/*
|
||||
* 3430ES1: CM_SLEEPDEP_GFX: MPU
|
||||
* 3430ES2: CM_SLEEPDEP_SGX: MPU
|
||||
* These can share data since they will never be present simultaneously
|
||||
* on the same device.
|
||||
*/
|
||||
static struct clkdm_dep gfx_sgx_sleepdeps[] = {
|
||||
{
|
||||
.clkdm_name = "mpu_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
#endif /* CONFIG_ARCH_OMAP3 */
|
||||
|
||||
|
||||
/*
|
||||
* OMAP2/3-common clockdomains
|
||||
@ -430,439 +84,18 @@ static struct clkdm_dep gfx_sgx_sleepdeps[] = {
|
||||
*/
|
||||
|
||||
/* This is an implicit clockdomain - it is never defined as such in TRM */
|
||||
static struct clockdomain wkup_clkdm = {
|
||||
struct clockdomain wkup_common_clkdm = {
|
||||
.name = "wkup_clkdm",
|
||||
.pwrdm = { .name = "wkup_pwrdm" },
|
||||
.dep_bit = OMAP_EN_WKUP_SHIFT,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain prm_clkdm = {
|
||||
struct clockdomain prm_common_clkdm = {
|
||||
.name = "prm_clkdm",
|
||||
.pwrdm = { .name = "wkup_pwrdm" },
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain cm_clkdm = {
|
||||
struct clockdomain cm_common_clkdm = {
|
||||
.name = "cm_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/*
|
||||
* 2420-only clockdomains
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SOC_OMAP2420)
|
||||
|
||||
static struct clockdomain mpu_2420_clkdm = {
|
||||
.name = "mpu_clkdm",
|
||||
.pwrdm = { .name = "mpu_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.wkdep_srcs = mpu_24xx_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
static struct clockdomain iva1_2420_clkdm = {
|
||||
.name = "iva1_clkdm",
|
||||
.pwrdm = { .name = "dsp_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
|
||||
.wkdep_srcs = dsp_24xx_wkdeps,
|
||||
.clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
static struct clockdomain dsp_2420_clkdm = {
|
||||
.name = "dsp_clkdm",
|
||||
.pwrdm = { .name = "dsp_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
static struct clockdomain gfx_2420_clkdm = {
|
||||
.name = "gfx_clkdm",
|
||||
.pwrdm = { .name = "gfx_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = gfx_sgx_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
static struct clockdomain core_l3_2420_clkdm = {
|
||||
.name = "core_l3_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.wkdep_srcs = core_24xx_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
static struct clockdomain core_l4_2420_clkdm = {
|
||||
.name = "core_l4_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.wkdep_srcs = core_24xx_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
static struct clockdomain dss_2420_clkdm = {
|
||||
.name = "dss_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
#endif /* CONFIG_SOC_OMAP2420 */
|
||||
|
||||
|
||||
/*
|
||||
* 2430-only clockdomains
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SOC_OMAP2430)
|
||||
|
||||
static struct clockdomain mpu_2430_clkdm = {
|
||||
.name = "mpu_clkdm",
|
||||
.pwrdm = { .name = "mpu_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = mpu_24xx_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* Another case of bit name collisions between several registers: EN_MDM */
|
||||
static struct clockdomain mdm_clkdm = {
|
||||
.name = "mdm_clkdm",
|
||||
.pwrdm = { .name = "mdm_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
|
||||
.wkdep_srcs = mdm_2430_wkdeps,
|
||||
.clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
static struct clockdomain dsp_2430_clkdm = {
|
||||
.name = "dsp_clkdm",
|
||||
.pwrdm = { .name = "dsp_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
|
||||
.wkdep_srcs = dsp_24xx_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
static struct clockdomain gfx_2430_clkdm = {
|
||||
.name = "gfx_clkdm",
|
||||
.pwrdm = { .name = "gfx_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = gfx_sgx_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX add usecounting for clkdm dependencies, otherwise the presence
|
||||
* of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
|
||||
* could cause trouble
|
||||
*/
|
||||
static struct clockdomain core_l3_2430_clkdm = {
|
||||
.name = "core_l3_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.dep_bit = OMAP24XX_EN_CORE_SHIFT,
|
||||
.wkdep_srcs = core_24xx_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX add usecounting for clkdm dependencies, otherwise the presence
|
||||
* of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
|
||||
* could cause trouble
|
||||
*/
|
||||
static struct clockdomain core_l4_2430_clkdm = {
|
||||
.name = "core_l4_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.dep_bit = OMAP24XX_EN_CORE_SHIFT,
|
||||
.wkdep_srcs = core_24xx_wkdeps,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
static struct clockdomain dss_2430_clkdm = {
|
||||
.name = "dss_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
#endif /* CONFIG_SOC_OMAP2430 */
|
||||
|
||||
|
||||
/*
|
||||
* OMAP3 clockdomains
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP3)
|
||||
|
||||
static struct clockdomain mpu_3xxx_clkdm = {
|
||||
.name = "mpu_clkdm",
|
||||
.pwrdm = { .name = "mpu_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
|
||||
.dep_bit = OMAP3430_EN_MPU_SHIFT,
|
||||
.wkdep_srcs = mpu_3xxx_wkdeps,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain neon_clkdm = {
|
||||
.name = "neon_clkdm",
|
||||
.pwrdm = { .name = "neon_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = neon_wkdeps,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain iva2_clkdm = {
|
||||
.name = "iva2_clkdm",
|
||||
.pwrdm = { .name = "iva2_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
|
||||
.wkdep_srcs = iva2_wkdeps,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain gfx_3430es1_clkdm = {
|
||||
.name = "gfx_clkdm",
|
||||
.pwrdm = { .name = "gfx_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = gfx_sgx_wkdeps,
|
||||
.sleepdep_srcs = gfx_sgx_sleepdeps,
|
||||
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
|
||||
};
|
||||
|
||||
static struct clockdomain sgx_clkdm = {
|
||||
.name = "sgx_clkdm",
|
||||
.pwrdm = { .name = "sgx_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = gfx_sgx_wkdeps,
|
||||
.sleepdep_srcs = gfx_sgx_sleepdeps,
|
||||
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
|
||||
};
|
||||
|
||||
/*
|
||||
* The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
|
||||
* then that information was removed from the 34xx ES2+ TRM. It is
|
||||
* unclear whether the core is still there, but the clockdomain logic
|
||||
* is there, and must be programmed to an appropriate state if the
|
||||
* CORE clockdomain is to become inactive.
|
||||
*/
|
||||
static struct clockdomain d2d_clkdm = {
|
||||
.name = "d2d_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX add usecounting for clkdm dependencies, otherwise the presence
|
||||
* of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
|
||||
* could cause trouble
|
||||
*/
|
||||
static struct clockdomain core_l3_3xxx_clkdm = {
|
||||
.name = "core_l3_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.dep_bit = OMAP3430_EN_CORE_SHIFT,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX add usecounting for clkdm dependencies, otherwise the presence
|
||||
* of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
|
||||
* could cause trouble
|
||||
*/
|
||||
static struct clockdomain core_l4_3xxx_clkdm = {
|
||||
.name = "core_l4_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.dep_bit = OMAP3430_EN_CORE_SHIFT,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* Another case of bit name collisions between several registers: EN_DSS */
|
||||
static struct clockdomain dss_3xxx_clkdm = {
|
||||
.name = "dss_clkdm",
|
||||
.pwrdm = { .name = "dss_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
|
||||
.wkdep_srcs = dss_wkdeps,
|
||||
.sleepdep_srcs = dss_sleepdeps,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain cam_clkdm = {
|
||||
.name = "cam_clkdm",
|
||||
.pwrdm = { .name = "cam_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = cam_wkdeps,
|
||||
.sleepdep_srcs = cam_sleepdeps,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain usbhost_clkdm = {
|
||||
.name = "usbhost_clkdm",
|
||||
.pwrdm = { .name = "usbhost_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = usbhost_wkdeps,
|
||||
.sleepdep_srcs = usbhost_sleepdeps,
|
||||
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
|
||||
};
|
||||
|
||||
static struct clockdomain per_clkdm = {
|
||||
.name = "per_clkdm",
|
||||
.pwrdm = { .name = "per_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.dep_bit = OMAP3430_EN_PER_SHIFT,
|
||||
.wkdep_srcs = per_wkdeps,
|
||||
.sleepdep_srcs = per_sleepdeps,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/*
|
||||
* Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
|
||||
* switched of even if sdti is in use
|
||||
*/
|
||||
static struct clockdomain emu_clkdm = {
|
||||
.name = "emu_clkdm",
|
||||
.pwrdm = { .name = "emu_pwrdm" },
|
||||
.flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain dpll1_clkdm = {
|
||||
.name = "dpll1_clkdm",
|
||||
.pwrdm = { .name = "dpll1_pwrdm" },
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain dpll2_clkdm = {
|
||||
.name = "dpll2_clkdm",
|
||||
.pwrdm = { .name = "dpll2_pwrdm" },
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain dpll3_clkdm = {
|
||||
.name = "dpll3_clkdm",
|
||||
.pwrdm = { .name = "dpll3_pwrdm" },
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain dpll4_clkdm = {
|
||||
.name = "dpll4_clkdm",
|
||||
.pwrdm = { .name = "dpll4_pwrdm" },
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static struct clockdomain dpll5_clkdm = {
|
||||
.name = "dpll5_clkdm",
|
||||
.pwrdm = { .name = "dpll5_pwrdm" },
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
|
||||
};
|
||||
|
||||
#endif /* CONFIG_ARCH_OMAP3 */
|
||||
|
||||
/*
|
||||
* Clockdomain hwsup dependencies (OMAP3 only)
|
||||
*/
|
||||
|
||||
static struct clkdm_autodep clkdm_autodeps[] = {
|
||||
{
|
||||
.clkdm = { .name = "mpu_clkdm" },
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm = { .name = "iva2_clkdm" },
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
},
|
||||
{
|
||||
.clkdm = { .name = NULL },
|
||||
}
|
||||
};
|
||||
|
||||
static struct clockdomain *clockdomains_omap2[] __initdata = {
|
||||
&wkup_clkdm,
|
||||
&cm_clkdm,
|
||||
&prm_clkdm,
|
||||
|
||||
#ifdef CONFIG_SOC_OMAP2420
|
||||
&mpu_2420_clkdm,
|
||||
&iva1_2420_clkdm,
|
||||
&dsp_2420_clkdm,
|
||||
&gfx_2420_clkdm,
|
||||
&core_l3_2420_clkdm,
|
||||
&core_l4_2420_clkdm,
|
||||
&dss_2420_clkdm,
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_OMAP2430
|
||||
&mpu_2430_clkdm,
|
||||
&mdm_clkdm,
|
||||
&dsp_2430_clkdm,
|
||||
&gfx_2430_clkdm,
|
||||
&core_l3_2430_clkdm,
|
||||
&core_l4_2430_clkdm,
|
||||
&dss_2430_clkdm,
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
&mpu_3xxx_clkdm,
|
||||
&neon_clkdm,
|
||||
&iva2_clkdm,
|
||||
&gfx_3430es1_clkdm,
|
||||
&sgx_clkdm,
|
||||
&d2d_clkdm,
|
||||
&core_l3_3xxx_clkdm,
|
||||
&core_l4_3xxx_clkdm,
|
||||
&dss_3xxx_clkdm,
|
||||
&cam_clkdm,
|
||||
&usbhost_clkdm,
|
||||
&per_clkdm,
|
||||
&emu_clkdm,
|
||||
&dpll1_clkdm,
|
||||
&dpll2_clkdm,
|
||||
&dpll3_clkdm,
|
||||
&dpll4_clkdm,
|
||||
&dpll5_clkdm,
|
||||
#endif
|
||||
NULL,
|
||||
};
|
||||
|
||||
void __init omap2xxx_clockdomains_init(void)
|
||||
{
|
||||
clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap2_clkdm_operations);
|
||||
}
|
||||
|
||||
void __init omap3xxx_clockdomains_init(void)
|
||||
{
|
||||
clkdm_init(clockdomains_omap2, clkdm_autodeps, &omap3_clkdm_operations);
|
||||
}
|
||||
|
398
arch/arm/mach-omap2/clockdomains3xxx_data.c
Normal file
398
arch/arm/mach-omap2/clockdomains3xxx_data.c
Normal file
@ -0,0 +1,398 @@
|
||||
/*
|
||||
* OMAP3xxx clockdomains
|
||||
*
|
||||
* Copyright (C) 2008-2011 Texas Instruments, Inc.
|
||||
* Copyright (C) 2008-2010 Nokia Corporation
|
||||
*
|
||||
* Paul Walmsley, Jouni Högander
|
||||
*
|
||||
* This file contains clockdomains and clockdomain wakeup/sleep
|
||||
* dependencies for the OMAP3xxx chips. Some notes:
|
||||
*
|
||||
* A useful validation rule for struct clockdomain: Any clockdomain
|
||||
* referenced by a wkdep_srcs or sleepdep_srcs array must have a
|
||||
* dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just
|
||||
* software-controllable dependencies. Non-software-controllable
|
||||
* dependencies do exist, but they are not encoded below (yet).
|
||||
*
|
||||
* The overly-specific dep_bit names are due to a bit name collision
|
||||
* with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
|
||||
* value are the same for all powerdomains: 2
|
||||
*
|
||||
* XXX should dep_bit be a mask, so we can test to see if it is 0 as a
|
||||
* sanity check?
|
||||
* XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
|
||||
*/
|
||||
|
||||
/*
|
||||
* To-Do List
|
||||
* -> Port the Sleep/Wakeup dependencies for the domains
|
||||
* from the Power domain framework
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include "clockdomain.h"
|
||||
#include "prm2xxx_3xxx.h"
|
||||
#include "cm2xxx_3xxx.h"
|
||||
#include "cm-regbits-34xx.h"
|
||||
#include "prm-regbits-34xx.h"
|
||||
|
||||
/*
|
||||
* Clockdomain dependencies for wkdeps/sleepdeps
|
||||
*
|
||||
* XXX Hardware dependencies (e.g., dependencies that cannot be
|
||||
* changed in software) are not included here yet, but should be.
|
||||
*/
|
||||
|
||||
/* OMAP3-specific possible dependencies */
|
||||
|
||||
/*
|
||||
* 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
|
||||
* 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
|
||||
*/
|
||||
static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
|
||||
{ .clkdm_name = "iva2_clkdm", },
|
||||
{ .clkdm_name = "mpu_clkdm", },
|
||||
{ .clkdm_name = "wkup_clkdm", },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
|
||||
static struct clkdm_dep per_wkdeps[] = {
|
||||
{ .clkdm_name = "core_l3_clkdm" },
|
||||
{ .clkdm_name = "core_l4_clkdm" },
|
||||
{ .clkdm_name = "iva2_clkdm" },
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ .clkdm_name = "wkup_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
|
||||
static struct clkdm_dep usbhost_wkdeps[] = {
|
||||
{ .clkdm_name = "core_l3_clkdm" },
|
||||
{ .clkdm_name = "core_l4_clkdm" },
|
||||
{ .clkdm_name = "iva2_clkdm" },
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ .clkdm_name = "wkup_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
|
||||
static struct clkdm_dep mpu_3xxx_wkdeps[] = {
|
||||
{ .clkdm_name = "core_l3_clkdm" },
|
||||
{ .clkdm_name = "core_l4_clkdm" },
|
||||
{ .clkdm_name = "iva2_clkdm" },
|
||||
{ .clkdm_name = "dss_clkdm" },
|
||||
{ .clkdm_name = "per_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
|
||||
static struct clkdm_dep iva2_wkdeps[] = {
|
||||
{ .clkdm_name = "core_l3_clkdm" },
|
||||
{ .clkdm_name = "core_l4_clkdm" },
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ .clkdm_name = "wkup_clkdm" },
|
||||
{ .clkdm_name = "dss_clkdm" },
|
||||
{ .clkdm_name = "per_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
|
||||
static struct clkdm_dep cam_wkdeps[] = {
|
||||
{ .clkdm_name = "iva2_clkdm" },
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ .clkdm_name = "wkup_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
|
||||
static struct clkdm_dep dss_wkdeps[] = {
|
||||
{ .clkdm_name = "iva2_clkdm" },
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ .clkdm_name = "wkup_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430: PM_WKDEP_NEON: MPU */
|
||||
static struct clkdm_dep neon_wkdeps[] = {
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* Sleep dependency source arrays for OMAP3-specific clkdms */
|
||||
|
||||
/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
|
||||
static struct clkdm_dep dss_sleepdeps[] = {
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ .clkdm_name = "iva2_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
|
||||
static struct clkdm_dep per_sleepdeps[] = {
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ .clkdm_name = "iva2_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
|
||||
static struct clkdm_dep usbhost_sleepdeps[] = {
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ .clkdm_name = "iva2_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/* 3430: CM_SLEEPDEP_CAM: MPU */
|
||||
static struct clkdm_dep cam_sleepdeps[] = {
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/*
|
||||
* 3430ES1: CM_SLEEPDEP_GFX: MPU
|
||||
* 3430ES2: CM_SLEEPDEP_SGX: MPU
|
||||
* These can share data since they will never be present simultaneously
|
||||
* on the same device.
|
||||
*/
|
||||
static struct clkdm_dep gfx_sgx_sleepdeps[] = {
|
||||
{ .clkdm_name = "mpu_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
/*
|
||||
* OMAP3 clockdomains
|
||||
*/
|
||||
|
||||
static struct clockdomain mpu_3xxx_clkdm = {
|
||||
.name = "mpu_clkdm",
|
||||
.pwrdm = { .name = "mpu_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
|
||||
.dep_bit = OMAP3430_EN_MPU_SHIFT,
|
||||
.wkdep_srcs = mpu_3xxx_wkdeps,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain neon_clkdm = {
|
||||
.name = "neon_clkdm",
|
||||
.pwrdm = { .name = "neon_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = neon_wkdeps,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain iva2_clkdm = {
|
||||
.name = "iva2_clkdm",
|
||||
.pwrdm = { .name = "iva2_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
|
||||
.wkdep_srcs = iva2_wkdeps,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain gfx_3430es1_clkdm = {
|
||||
.name = "gfx_clkdm",
|
||||
.pwrdm = { .name = "gfx_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = gfx_sgx_3xxx_wkdeps,
|
||||
.sleepdep_srcs = gfx_sgx_sleepdeps,
|
||||
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain sgx_clkdm = {
|
||||
.name = "sgx_clkdm",
|
||||
.pwrdm = { .name = "sgx_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = gfx_sgx_3xxx_wkdeps,
|
||||
.sleepdep_srcs = gfx_sgx_sleepdeps,
|
||||
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
|
||||
};
|
||||
|
||||
/*
|
||||
* The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
|
||||
* then that information was removed from the 34xx ES2+ TRM. It is
|
||||
* unclear whether the core is still there, but the clockdomain logic
|
||||
* is there, and must be programmed to an appropriate state if the
|
||||
* CORE clockdomain is to become inactive.
|
||||
*/
|
||||
static struct clockdomain d2d_clkdm = {
|
||||
.name = "d2d_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX add usecounting for clkdm dependencies, otherwise the presence
|
||||
* of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
|
||||
* could cause trouble
|
||||
*/
|
||||
static struct clockdomain core_l3_3xxx_clkdm = {
|
||||
.name = "core_l3_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.dep_bit = OMAP3430_EN_CORE_SHIFT,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX add usecounting for clkdm dependencies, otherwise the presence
|
||||
* of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
|
||||
* could cause trouble
|
||||
*/
|
||||
static struct clockdomain core_l4_3xxx_clkdm = {
|
||||
.name = "core_l4_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.dep_bit = OMAP3430_EN_CORE_SHIFT,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
|
||||
};
|
||||
|
||||
/* Another case of bit name collisions between several registers: EN_DSS */
|
||||
static struct clockdomain dss_3xxx_clkdm = {
|
||||
.name = "dss_clkdm",
|
||||
.pwrdm = { .name = "dss_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
|
||||
.wkdep_srcs = dss_wkdeps,
|
||||
.sleepdep_srcs = dss_sleepdeps,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain cam_clkdm = {
|
||||
.name = "cam_clkdm",
|
||||
.pwrdm = { .name = "cam_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = cam_wkdeps,
|
||||
.sleepdep_srcs = cam_sleepdeps,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain usbhost_clkdm = {
|
||||
.name = "usbhost_clkdm",
|
||||
.pwrdm = { .name = "usbhost_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.wkdep_srcs = usbhost_wkdeps,
|
||||
.sleepdep_srcs = usbhost_sleepdeps,
|
||||
.clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain per_clkdm = {
|
||||
.name = "per_clkdm",
|
||||
.pwrdm = { .name = "per_pwrdm" },
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.dep_bit = OMAP3430_EN_PER_SHIFT,
|
||||
.wkdep_srcs = per_wkdeps,
|
||||
.sleepdep_srcs = per_sleepdeps,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
|
||||
};
|
||||
|
||||
/*
|
||||
* Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
|
||||
* switched of even if sdti is in use
|
||||
*/
|
||||
static struct clockdomain emu_clkdm = {
|
||||
.name = "emu_clkdm",
|
||||
.pwrdm = { .name = "emu_pwrdm" },
|
||||
.flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP,
|
||||
.clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
|
||||
};
|
||||
|
||||
static struct clockdomain dpll1_clkdm = {
|
||||
.name = "dpll1_clkdm",
|
||||
.pwrdm = { .name = "dpll1_pwrdm" },
|
||||
};
|
||||
|
||||
static struct clockdomain dpll2_clkdm = {
|
||||
.name = "dpll2_clkdm",
|
||||
.pwrdm = { .name = "dpll2_pwrdm" },
|
||||
};
|
||||
|
||||
static struct clockdomain dpll3_clkdm = {
|
||||
.name = "dpll3_clkdm",
|
||||
.pwrdm = { .name = "dpll3_pwrdm" },
|
||||
};
|
||||
|
||||
static struct clockdomain dpll4_clkdm = {
|
||||
.name = "dpll4_clkdm",
|
||||
.pwrdm = { .name = "dpll4_pwrdm" },
|
||||
};
|
||||
|
||||
static struct clockdomain dpll5_clkdm = {
|
||||
.name = "dpll5_clkdm",
|
||||
.pwrdm = { .name = "dpll5_pwrdm" },
|
||||
};
|
||||
|
||||
/*
|
||||
* Clockdomain hwsup dependencies
|
||||
*/
|
||||
|
||||
static struct clkdm_autodep clkdm_autodeps[] = {
|
||||
{
|
||||
.clkdm = { .name = "mpu_clkdm" },
|
||||
},
|
||||
{
|
||||
.clkdm = { .name = "iva2_clkdm" },
|
||||
},
|
||||
{
|
||||
.clkdm = { .name = NULL },
|
||||
}
|
||||
};
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
|
||||
static struct clockdomain *clockdomains_omap3430_common[] __initdata = {
|
||||
&wkup_common_clkdm,
|
||||
&cm_common_clkdm,
|
||||
&prm_common_clkdm,
|
||||
&mpu_3xxx_clkdm,
|
||||
&neon_clkdm,
|
||||
&iva2_clkdm,
|
||||
&d2d_clkdm,
|
||||
&core_l3_3xxx_clkdm,
|
||||
&core_l4_3xxx_clkdm,
|
||||
&dss_3xxx_clkdm,
|
||||
&cam_clkdm,
|
||||
&per_clkdm,
|
||||
&emu_clkdm,
|
||||
&dpll1_clkdm,
|
||||
&dpll2_clkdm,
|
||||
&dpll3_clkdm,
|
||||
&dpll4_clkdm,
|
||||
NULL
|
||||
};
|
||||
|
||||
static struct clockdomain *clockdomains_omap3430es1[] __initdata = {
|
||||
&gfx_3430es1_clkdm,
|
||||
NULL,
|
||||
};
|
||||
|
||||
static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = {
|
||||
&sgx_clkdm,
|
||||
&dpll5_clkdm,
|
||||
&usbhost_clkdm,
|
||||
NULL,
|
||||
};
|
||||
|
||||
void __init omap3xxx_clockdomains_init(void)
|
||||
{
|
||||
struct clockdomain **sc;
|
||||
|
||||
if (!cpu_is_omap34xx())
|
||||
return;
|
||||
|
||||
clkdm_register_platform_funcs(&omap3_clkdm_operations);
|
||||
clkdm_register_clkdms(clockdomains_omap3430_common);
|
||||
|
||||
sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 :
|
||||
clockdomains_omap3430es2plus;
|
||||
|
||||
clkdm_register_clkdms(sc);
|
||||
|
||||
clkdm_register_autodeps(clkdm_autodeps);
|
||||
clkdm_complete_init();
|
||||
}
|
@ -34,350 +34,122 @@
|
||||
/* Static Dependencies for OMAP4 Clock Domains */
|
||||
|
||||
static struct clkdm_dep d2d_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "abe_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "ivahd_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_1_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_init_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_cfg_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_per_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{ .clkdm_name = "abe_clkdm" },
|
||||
{ .clkdm_name = "ivahd_clkdm" },
|
||||
{ .clkdm_name = "l3_1_clkdm" },
|
||||
{ .clkdm_name = "l3_2_clkdm" },
|
||||
{ .clkdm_name = "l3_emif_clkdm" },
|
||||
{ .clkdm_name = "l3_init_clkdm" },
|
||||
{ .clkdm_name = "l4_cfg_clkdm" },
|
||||
{ .clkdm_name = "l4_per_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
static struct clkdm_dep ducati_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "abe_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "ivahd_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_1_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_dss_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_gfx_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_init_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_cfg_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_per_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_secure_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_wkup_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "tesla_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{ .clkdm_name = "abe_clkdm" },
|
||||
{ .clkdm_name = "ivahd_clkdm" },
|
||||
{ .clkdm_name = "l3_1_clkdm" },
|
||||
{ .clkdm_name = "l3_2_clkdm" },
|
||||
{ .clkdm_name = "l3_dss_clkdm" },
|
||||
{ .clkdm_name = "l3_emif_clkdm" },
|
||||
{ .clkdm_name = "l3_gfx_clkdm" },
|
||||
{ .clkdm_name = "l3_init_clkdm" },
|
||||
{ .clkdm_name = "l4_cfg_clkdm" },
|
||||
{ .clkdm_name = "l4_per_clkdm" },
|
||||
{ .clkdm_name = "l4_secure_clkdm" },
|
||||
{ .clkdm_name = "l4_wkup_clkdm" },
|
||||
{ .clkdm_name = "tesla_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
static struct clkdm_dep iss_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "ivahd_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_1_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{ .clkdm_name = "ivahd_clkdm" },
|
||||
{ .clkdm_name = "l3_1_clkdm" },
|
||||
{ .clkdm_name = "l3_emif_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "l3_1_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{ .clkdm_name = "l3_1_clkdm" },
|
||||
{ .clkdm_name = "l3_emif_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "abe_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "ducati_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "ivahd_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_1_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_dss_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_init_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_cfg_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_per_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_secure_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_wkup_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{ .clkdm_name = "abe_clkdm" },
|
||||
{ .clkdm_name = "ducati_clkdm" },
|
||||
{ .clkdm_name = "ivahd_clkdm" },
|
||||
{ .clkdm_name = "l3_1_clkdm" },
|
||||
{ .clkdm_name = "l3_dss_clkdm" },
|
||||
{ .clkdm_name = "l3_emif_clkdm" },
|
||||
{ .clkdm_name = "l3_init_clkdm" },
|
||||
{ .clkdm_name = "l4_cfg_clkdm" },
|
||||
{ .clkdm_name = "l4_per_clkdm" },
|
||||
{ .clkdm_name = "l4_secure_clkdm" },
|
||||
{ .clkdm_name = "l4_wkup_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "ivahd_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{ .clkdm_name = "ivahd_clkdm" },
|
||||
{ .clkdm_name = "l3_2_clkdm" },
|
||||
{ .clkdm_name = "l3_emif_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "ivahd_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_1_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{ .clkdm_name = "ivahd_clkdm" },
|
||||
{ .clkdm_name = "l3_1_clkdm" },
|
||||
{ .clkdm_name = "l3_emif_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "abe_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "ivahd_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_cfg_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_per_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_secure_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_wkup_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{ .clkdm_name = "abe_clkdm" },
|
||||
{ .clkdm_name = "ivahd_clkdm" },
|
||||
{ .clkdm_name = "l3_emif_clkdm" },
|
||||
{ .clkdm_name = "l4_cfg_clkdm" },
|
||||
{ .clkdm_name = "l4_per_clkdm" },
|
||||
{ .clkdm_name = "l4_secure_clkdm" },
|
||||
{ .clkdm_name = "l4_wkup_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "l3_1_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_per_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{ .clkdm_name = "l3_1_clkdm" },
|
||||
{ .clkdm_name = "l3_emif_clkdm" },
|
||||
{ .clkdm_name = "l4_per_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
static struct clkdm_dep mpu_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "abe_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "ducati_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "ivahd_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_1_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_dss_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_gfx_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_init_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_cfg_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_per_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_secure_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_wkup_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "tesla_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{ .clkdm_name = "abe_clkdm" },
|
||||
{ .clkdm_name = "ducati_clkdm" },
|
||||
{ .clkdm_name = "ivahd_clkdm" },
|
||||
{ .clkdm_name = "l3_1_clkdm" },
|
||||
{ .clkdm_name = "l3_2_clkdm" },
|
||||
{ .clkdm_name = "l3_dss_clkdm" },
|
||||
{ .clkdm_name = "l3_emif_clkdm" },
|
||||
{ .clkdm_name = "l3_gfx_clkdm" },
|
||||
{ .clkdm_name = "l3_init_clkdm" },
|
||||
{ .clkdm_name = "l4_cfg_clkdm" },
|
||||
{ .clkdm_name = "l4_per_clkdm" },
|
||||
{ .clkdm_name = "l4_secure_clkdm" },
|
||||
{ .clkdm_name = "l4_wkup_clkdm" },
|
||||
{ .clkdm_name = "tesla_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
static struct clkdm_dep tesla_wkup_sleep_deps[] = {
|
||||
{
|
||||
.clkdm_name = "abe_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "ivahd_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_1_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_2_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_emif_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l3_init_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_cfg_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_per_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{
|
||||
.clkdm_name = "l4_wkup_clkdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
|
||||
},
|
||||
{ .clkdm_name = "abe_clkdm" },
|
||||
{ .clkdm_name = "ivahd_clkdm" },
|
||||
{ .clkdm_name = "l3_1_clkdm" },
|
||||
{ .clkdm_name = "l3_2_clkdm" },
|
||||
{ .clkdm_name = "l3_emif_clkdm" },
|
||||
{ .clkdm_name = "l3_init_clkdm" },
|
||||
{ .clkdm_name = "l4_cfg_clkdm" },
|
||||
{ .clkdm_name = "l4_per_clkdm" },
|
||||
{ .clkdm_name = "l4_wkup_clkdm" },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
@ -388,7 +160,6 @@ static struct clockdomain l4_cefuse_44xx_clkdm = {
|
||||
.cm_inst = OMAP4430_CM2_CEFUSE_INST,
|
||||
.clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
|
||||
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain l4_cfg_44xx_clkdm = {
|
||||
@ -399,7 +170,6 @@ static struct clockdomain l4_cfg_44xx_clkdm = {
|
||||
.clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
|
||||
.dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT,
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain tesla_44xx_clkdm = {
|
||||
@ -412,7 +182,6 @@ static struct clockdomain tesla_44xx_clkdm = {
|
||||
.wkdep_srcs = tesla_wkup_sleep_deps,
|
||||
.sleepdep_srcs = tesla_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain l3_gfx_44xx_clkdm = {
|
||||
@ -425,7 +194,6 @@ static struct clockdomain l3_gfx_44xx_clkdm = {
|
||||
.wkdep_srcs = l3_gfx_wkup_sleep_deps,
|
||||
.sleepdep_srcs = l3_gfx_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain ivahd_44xx_clkdm = {
|
||||
@ -438,7 +206,6 @@ static struct clockdomain ivahd_44xx_clkdm = {
|
||||
.wkdep_srcs = ivahd_wkup_sleep_deps,
|
||||
.sleepdep_srcs = ivahd_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain l4_secure_44xx_clkdm = {
|
||||
@ -451,7 +218,6 @@ static struct clockdomain l4_secure_44xx_clkdm = {
|
||||
.wkdep_srcs = l4_secure_wkup_sleep_deps,
|
||||
.sleepdep_srcs = l4_secure_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain l4_per_44xx_clkdm = {
|
||||
@ -462,7 +228,6 @@ static struct clockdomain l4_per_44xx_clkdm = {
|
||||
.clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
|
||||
.dep_bit = OMAP4430_L4PER_STATDEP_SHIFT,
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain abe_44xx_clkdm = {
|
||||
@ -473,7 +238,6 @@ static struct clockdomain abe_44xx_clkdm = {
|
||||
.clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS,
|
||||
.dep_bit = OMAP4430_ABE_STATDEP_SHIFT,
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain l3_instr_44xx_clkdm = {
|
||||
@ -482,7 +246,6 @@ static struct clockdomain l3_instr_44xx_clkdm = {
|
||||
.prcm_partition = OMAP4430_CM2_PARTITION,
|
||||
.cm_inst = OMAP4430_CM2_CORE_INST,
|
||||
.clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain l3_init_44xx_clkdm = {
|
||||
@ -495,7 +258,6 @@ static struct clockdomain l3_init_44xx_clkdm = {
|
||||
.wkdep_srcs = l3_init_wkup_sleep_deps,
|
||||
.sleepdep_srcs = l3_init_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain d2d_44xx_clkdm = {
|
||||
@ -507,7 +269,6 @@ static struct clockdomain d2d_44xx_clkdm = {
|
||||
.wkdep_srcs = d2d_wkup_sleep_deps,
|
||||
.sleepdep_srcs = d2d_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain mpu0_44xx_clkdm = {
|
||||
@ -517,7 +278,6 @@ static struct clockdomain mpu0_44xx_clkdm = {
|
||||
.cm_inst = OMAP4430_PRCM_MPU_CPU0_INST,
|
||||
.clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
|
||||
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain mpu1_44xx_clkdm = {
|
||||
@ -527,7 +287,6 @@ static struct clockdomain mpu1_44xx_clkdm = {
|
||||
.cm_inst = OMAP4430_PRCM_MPU_CPU1_INST,
|
||||
.clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
|
||||
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain l3_emif_44xx_clkdm = {
|
||||
@ -538,7 +297,6 @@ static struct clockdomain l3_emif_44xx_clkdm = {
|
||||
.clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
|
||||
.dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT,
|
||||
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain l4_ao_44xx_clkdm = {
|
||||
@ -548,7 +306,6 @@ static struct clockdomain l4_ao_44xx_clkdm = {
|
||||
.cm_inst = OMAP4430_CM2_ALWAYS_ON_INST,
|
||||
.clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
|
||||
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain ducati_44xx_clkdm = {
|
||||
@ -561,7 +318,6 @@ static struct clockdomain ducati_44xx_clkdm = {
|
||||
.wkdep_srcs = ducati_wkup_sleep_deps,
|
||||
.sleepdep_srcs = ducati_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain mpu_44xx_clkdm = {
|
||||
@ -573,7 +329,6 @@ static struct clockdomain mpu_44xx_clkdm = {
|
||||
.wkdep_srcs = mpu_wkup_sleep_deps,
|
||||
.sleepdep_srcs = mpu_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain l3_2_44xx_clkdm = {
|
||||
@ -584,7 +339,6 @@ static struct clockdomain l3_2_44xx_clkdm = {
|
||||
.clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS,
|
||||
.dep_bit = OMAP4430_L3_2_STATDEP_SHIFT,
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain l3_1_44xx_clkdm = {
|
||||
@ -595,7 +349,6 @@ static struct clockdomain l3_1_44xx_clkdm = {
|
||||
.clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS,
|
||||
.dep_bit = OMAP4430_L3_1_STATDEP_SHIFT,
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain iss_44xx_clkdm = {
|
||||
@ -607,7 +360,6 @@ static struct clockdomain iss_44xx_clkdm = {
|
||||
.wkdep_srcs = iss_wkup_sleep_deps,
|
||||
.sleepdep_srcs = iss_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain l3_dss_44xx_clkdm = {
|
||||
@ -620,7 +372,6 @@ static struct clockdomain l3_dss_44xx_clkdm = {
|
||||
.wkdep_srcs = l3_dss_wkup_sleep_deps,
|
||||
.sleepdep_srcs = l3_dss_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_HWSUP_SWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain l4_wkup_44xx_clkdm = {
|
||||
@ -631,7 +382,6 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
|
||||
.clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
|
||||
.dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT,
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain emu_sys_44xx_clkdm = {
|
||||
@ -641,7 +391,6 @@ static struct clockdomain emu_sys_44xx_clkdm = {
|
||||
.cm_inst = OMAP4430_PRM_EMU_CM_INST,
|
||||
.clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
|
||||
.flags = CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct clockdomain l3_dma_44xx_clkdm = {
|
||||
@ -653,7 +402,6 @@ static struct clockdomain l3_dma_44xx_clkdm = {
|
||||
.wkdep_srcs = l3_dma_wkup_sleep_deps,
|
||||
.sleepdep_srcs = l3_dma_wkup_sleep_deps,
|
||||
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* As clockdomains are added or removed above, this list must also be changed */
|
||||
@ -685,7 +433,10 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
|
||||
NULL
|
||||
};
|
||||
|
||||
|
||||
void __init omap44xx_clockdomains_init(void)
|
||||
{
|
||||
clkdm_init(clockdomains_omap44xx, NULL, &omap4_clkdm_operations);
|
||||
clkdm_register_platform_funcs(&omap4_clkdm_operations);
|
||||
clkdm_register_clkdms(clockdomains_omap44xx);
|
||||
clkdm_complete_init();
|
||||
}
|
||||
|
@ -56,6 +56,12 @@ void __init omap2_set_globals_242x(void)
|
||||
{
|
||||
__omap2_set_globals(&omap242x_globals);
|
||||
}
|
||||
|
||||
void __init omap242x_map_io(void)
|
||||
{
|
||||
omap2_set_globals_242x();
|
||||
omap242x_map_common_io();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_OMAP2430)
|
||||
@ -74,6 +80,12 @@ void __init omap2_set_globals_243x(void)
|
||||
{
|
||||
__omap2_set_globals(&omap243x_globals);
|
||||
}
|
||||
|
||||
void __init omap243x_map_io(void)
|
||||
{
|
||||
omap2_set_globals_243x();
|
||||
omap243x_map_common_io();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP3)
|
||||
@ -138,5 +150,11 @@ void __init omap2_set_globals_443x(void)
|
||||
omap2_set_globals_control(&omap4_globals);
|
||||
omap2_set_globals_prcm(&omap4_globals);
|
||||
}
|
||||
|
||||
void __init omap4_map_io(void)
|
||||
{
|
||||
omap2_set_globals_443x();
|
||||
omap44xx_map_common_io();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -16,6 +16,7 @@
|
||||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/irqs.h>
|
||||
@ -44,7 +45,7 @@ static int __init omap3_l3_init(void)
|
||||
{
|
||||
int l;
|
||||
struct omap_hwmod *oh;
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
char oh_name[L3_MODULES_MAX_LEN];
|
||||
|
||||
/*
|
||||
@ -61,12 +62,12 @@ static int __init omap3_l3_init(void)
|
||||
if (!oh)
|
||||
pr_err("could not look up %s\n", oh_name);
|
||||
|
||||
od = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
|
||||
pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
|
||||
NULL, 0, 0);
|
||||
|
||||
WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
|
||||
WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
|
||||
|
||||
return IS_ERR(od) ? PTR_ERR(od) : 0;
|
||||
return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
|
||||
}
|
||||
postcore_initcall(omap3_l3_init);
|
||||
|
||||
@ -74,9 +75,13 @@ static int __init omap4_l3_init(void)
|
||||
{
|
||||
int l, i;
|
||||
struct omap_hwmod *oh[3];
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
char oh_name[L3_MODULES_MAX_LEN];
|
||||
|
||||
/* If dtb is there, the devices will be created dynamically */
|
||||
if (of_have_populated_dt())
|
||||
return -ENODEV;
|
||||
|
||||
/*
|
||||
* To avoid code running on other OMAPs in
|
||||
* multi-omap builds
|
||||
@ -92,12 +97,12 @@ static int __init omap4_l3_init(void)
|
||||
pr_err("could not look up %s\n", oh_name);
|
||||
}
|
||||
|
||||
od = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
|
||||
pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
|
||||
0, NULL, 0, 0);
|
||||
|
||||
WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
|
||||
WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
|
||||
|
||||
return IS_ERR(od) ? PTR_ERR(od) : 0;
|
||||
return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
|
||||
}
|
||||
postcore_initcall(omap4_l3_init);
|
||||
|
||||
@ -221,18 +226,10 @@ static inline void omap_init_camera(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
struct omap_device_pm_latency omap_keyboard_latency[] = {
|
||||
{
|
||||
.deactivate_func = omap_device_idle_hwmods,
|
||||
.activate_func = omap_device_enable_hwmods,
|
||||
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
|
||||
},
|
||||
};
|
||||
|
||||
int __init omap4_keyboard_init(struct omap4_keypad_platform_data
|
||||
*sdp4430_keypad_data, struct omap_board_data *bdata)
|
||||
{
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
struct omap_hwmod *oh;
|
||||
struct omap4_keypad_platform_data *keypad_data;
|
||||
unsigned int id = -1;
|
||||
@ -247,15 +244,13 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
|
||||
|
||||
keypad_data = sdp4430_keypad_data;
|
||||
|
||||
od = omap_device_build(name, id, oh, keypad_data,
|
||||
sizeof(struct omap4_keypad_platform_data),
|
||||
omap_keyboard_latency,
|
||||
ARRAY_SIZE(omap_keyboard_latency), 0);
|
||||
pdev = omap_device_build(name, id, oh, keypad_data,
|
||||
sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
|
||||
|
||||
if (IS_ERR(od)) {
|
||||
if (IS_ERR(pdev)) {
|
||||
WARN(1, "Can't build omap_device for %s:%s.\n",
|
||||
name, oh->name);
|
||||
return PTR_ERR(od);
|
||||
return PTR_ERR(pdev);
|
||||
}
|
||||
oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
|
||||
|
||||
@ -263,18 +258,10 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
|
||||
static struct omap_device_pm_latency mbox_latencies[] = {
|
||||
[0] = {
|
||||
.activate_func = omap_device_enable_hwmods,
|
||||
.deactivate_func = omap_device_idle_hwmods,
|
||||
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
|
||||
},
|
||||
};
|
||||
|
||||
static inline void omap_init_mbox(void)
|
||||
{
|
||||
struct omap_hwmod *oh;
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
|
||||
oh = omap_hwmod_lookup("mailbox");
|
||||
if (!oh) {
|
||||
@ -282,10 +269,9 @@ static inline void omap_init_mbox(void)
|
||||
return;
|
||||
}
|
||||
|
||||
od = omap_device_build("omap-mailbox", -1, oh, NULL, 0,
|
||||
mbox_latencies, ARRAY_SIZE(mbox_latencies), 0);
|
||||
WARN(IS_ERR(od), "%s: could not build device, err %ld\n",
|
||||
__func__, PTR_ERR(od));
|
||||
pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
|
||||
WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
|
||||
__func__, PTR_ERR(pdev));
|
||||
}
|
||||
#else
|
||||
static inline void omap_init_mbox(void) { }
|
||||
@ -334,17 +320,9 @@ static inline void omap_init_audio(void) {}
|
||||
|
||||
#include <plat/mcspi.h>
|
||||
|
||||
struct omap_device_pm_latency omap_mcspi_latency[] = {
|
||||
[0] = {
|
||||
.deactivate_func = omap_device_idle_hwmods,
|
||||
.activate_func = omap_device_enable_hwmods,
|
||||
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
|
||||
},
|
||||
};
|
||||
|
||||
static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
|
||||
{
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
char *name = "omap2_mcspi";
|
||||
struct omap2_mcspi_platform_config *pdata;
|
||||
static int spi_num;
|
||||
@ -371,10 +349,9 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
|
||||
}
|
||||
|
||||
spi_num++;
|
||||
od = omap_device_build(name, spi_num, oh, pdata,
|
||||
sizeof(*pdata), omap_mcspi_latency,
|
||||
ARRAY_SIZE(omap_mcspi_latency), 0);
|
||||
WARN(IS_ERR(od), "Can't build omap_device for %s:%s\n",
|
||||
pdev = omap_device_build(name, spi_num, oh, pdata,
|
||||
sizeof(*pdata), NULL, 0, 0);
|
||||
WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
|
||||
name, oh->name);
|
||||
kfree(pdata);
|
||||
return 0;
|
||||
@ -698,18 +675,10 @@ static int __init omap2_init_devices(void)
|
||||
arch_initcall(omap2_init_devices);
|
||||
|
||||
#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
|
||||
static struct omap_device_pm_latency omap_wdt_latency[] = {
|
||||
[0] = {
|
||||
.deactivate_func = omap_device_idle_hwmods,
|
||||
.activate_func = omap_device_enable_hwmods,
|
||||
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init omap_init_wdt(void)
|
||||
{
|
||||
int id = -1;
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
struct omap_hwmod *oh;
|
||||
char *oh_name = "wd_timer2";
|
||||
char *dev_name = "omap_wdt";
|
||||
@ -723,10 +692,8 @@ static int __init omap_init_wdt(void)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
od = omap_device_build(dev_name, id, oh, NULL, 0,
|
||||
omap_wdt_latency,
|
||||
ARRAY_SIZE(omap_wdt_latency), 0);
|
||||
WARN(IS_ERR(od), "Can't build omap_device for %s:%s.\n",
|
||||
pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
|
||||
WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
|
||||
dev_name, oh->name);
|
||||
return 0;
|
||||
}
|
||||
|
@ -35,14 +35,6 @@ static struct platform_device omap_display_device = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct omap_device_pm_latency omap_dss_latency[] = {
|
||||
[0] = {
|
||||
.deactivate_func = omap_device_idle_hwmods,
|
||||
.activate_func = omap_device_enable_hwmods,
|
||||
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
|
||||
},
|
||||
};
|
||||
|
||||
struct omap_dss_hwmod_data {
|
||||
const char *oh_name;
|
||||
const char *dev_name;
|
||||
@ -78,7 +70,7 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
|
||||
{
|
||||
int r = 0;
|
||||
struct omap_hwmod *oh;
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
int i, oh_count;
|
||||
struct omap_display_platform_data pdata;
|
||||
const struct omap_dss_hwmod_data *curr_dss_hwmod;
|
||||
@ -108,13 +100,12 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
od = omap_device_build(curr_dss_hwmod[i].dev_name,
|
||||
pdev = omap_device_build(curr_dss_hwmod[i].dev_name,
|
||||
curr_dss_hwmod[i].id, oh, &pdata,
|
||||
sizeof(struct omap_display_platform_data),
|
||||
omap_dss_latency,
|
||||
ARRAY_SIZE(omap_dss_latency), 0);
|
||||
NULL, 0, 0);
|
||||
|
||||
if (WARN((IS_ERR(od)), "Could not build omap_device for %s\n",
|
||||
if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n",
|
||||
curr_dss_hwmod[i].oh_name))
|
||||
return -ENODEV;
|
||||
}
|
||||
|
@ -87,14 +87,6 @@ static u16 reg_map[] = {
|
||||
[CCDN] = 0xd8,
|
||||
};
|
||||
|
||||
static struct omap_device_pm_latency omap2_dma_latency[] = {
|
||||
{
|
||||
.deactivate_func = omap_device_idle_hwmods,
|
||||
.activate_func = omap_device_enable_hwmods,
|
||||
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
|
||||
},
|
||||
};
|
||||
|
||||
static void __iomem *dma_base;
|
||||
static inline void dma_write(u32 val, int reg, int lch)
|
||||
{
|
||||
@ -228,7 +220,7 @@ static u32 configure_dma_errata(void)
|
||||
/* One time initializations */
|
||||
static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
|
||||
{
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
struct omap_system_dma_plat_info *p;
|
||||
struct resource *mem;
|
||||
char *name = "omap_dma_system";
|
||||
@ -258,23 +250,22 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
|
||||
|
||||
p->errata = configure_dma_errata();
|
||||
|
||||
od = omap_device_build(name, 0, oh, p, sizeof(*p),
|
||||
omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0);
|
||||
pdev = omap_device_build(name, 0, oh, p, sizeof(*p), NULL, 0, 0);
|
||||
kfree(p);
|
||||
if (IS_ERR(od)) {
|
||||
if (IS_ERR(pdev)) {
|
||||
pr_err("%s: Can't build omap_device for %s:%s.\n",
|
||||
__func__, name, oh->name);
|
||||
return PTR_ERR(od);
|
||||
return PTR_ERR(pdev);
|
||||
}
|
||||
|
||||
mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0);
|
||||
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!mem) {
|
||||
dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__);
|
||||
dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
dma_base = ioremap(mem->start, resource_size(mem));
|
||||
if (!dma_base) {
|
||||
dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__);
|
||||
dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
@ -283,7 +274,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
|
||||
(d->lch_count), GFP_KERNEL);
|
||||
|
||||
if (!d->chan) {
|
||||
dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__);
|
||||
dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
return 0;
|
||||
|
@ -24,17 +24,9 @@
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/omap_device.h>
|
||||
|
||||
static struct omap_device_pm_latency omap_gpio_latency[] = {
|
||||
[0] = {
|
||||
.deactivate_func = omap_device_idle_hwmods,
|
||||
.activate_func = omap_device_enable_hwmods,
|
||||
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
|
||||
},
|
||||
};
|
||||
|
||||
static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
|
||||
{
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
struct omap_gpio_platform_data *pdata;
|
||||
struct omap_gpio_dev_attr *dev_attr;
|
||||
char *name = "omap_gpio";
|
||||
@ -107,19 +99,17 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
od = omap_device_build(name, id - 1, oh, pdata,
|
||||
sizeof(*pdata), omap_gpio_latency,
|
||||
ARRAY_SIZE(omap_gpio_latency),
|
||||
false);
|
||||
pdev = omap_device_build(name, id - 1, oh, pdata,
|
||||
sizeof(*pdata), NULL, 0, false);
|
||||
kfree(pdata);
|
||||
|
||||
if (IS_ERR(od)) {
|
||||
if (IS_ERR(pdev)) {
|
||||
WARN(1, "Can't build omap_device for %s:%s.\n",
|
||||
name, oh->name);
|
||||
return PTR_ERR(od);
|
||||
return PTR_ERR(pdev);
|
||||
}
|
||||
|
||||
omap_device_disable_idle_on_suspend(od);
|
||||
omap_device_disable_idle_on_suspend(pdev);
|
||||
|
||||
gpio_bank_count++;
|
||||
return 0;
|
||||
|
@ -409,31 +409,17 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct omap_device_pm_latency omap_hsmmc_latency[] = {
|
||||
[0] = {
|
||||
.deactivate_func = omap_device_idle_hwmods,
|
||||
.activate_func = omap_device_enable_hwmods,
|
||||
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
|
||||
},
|
||||
/*
|
||||
* XXX There should also be an entry here to power off/on the
|
||||
* MMC regulators/PBIAS cells, etc.
|
||||
*/
|
||||
};
|
||||
|
||||
#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
|
||||
|
||||
void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
|
||||
{
|
||||
struct omap_hwmod *oh;
|
||||
struct omap_device *od;
|
||||
struct omap_device_pm_latency *ohl;
|
||||
struct platform_device *pdev;
|
||||
char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
|
||||
struct omap_mmc_platform_data *mmc_data;
|
||||
struct omap_mmc_dev_attr *mmc_dev_attr;
|
||||
char *name;
|
||||
int l;
|
||||
int ohl_cnt = 0;
|
||||
|
||||
mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
|
||||
if (!mmc_data) {
|
||||
@ -448,8 +434,6 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
|
||||
omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
|
||||
|
||||
name = "omap_hsmmc";
|
||||
ohl = omap_hsmmc_latency;
|
||||
ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
|
||||
|
||||
l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
|
||||
"mmc%d", ctrl_nr);
|
||||
@ -467,9 +451,9 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
|
||||
mmc_data->controller_flags = mmc_dev_attr->flags;
|
||||
}
|
||||
|
||||
od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
|
||||
sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
|
||||
if (IS_ERR(od)) {
|
||||
pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
|
||||
sizeof(struct omap_mmc_platform_data), NULL, 0, false);
|
||||
if (IS_ERR(pdev)) {
|
||||
WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
|
||||
kfree(mmc_data->slots[0].name);
|
||||
goto done;
|
||||
@ -478,7 +462,7 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
|
||||
* return device handle to board setup code
|
||||
* required to populate for regulator framework structure
|
||||
*/
|
||||
hsmmcinfo->dev = &od->pdev.dev;
|
||||
hsmmcinfo->dev = &pdev->dev;
|
||||
|
||||
done:
|
||||
kfree(mmc_data);
|
||||
|
@ -23,19 +23,11 @@
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/omap_device.h>
|
||||
|
||||
struct omap_device_pm_latency omap_spinlock_latency[] = {
|
||||
{
|
||||
.deactivate_func = omap_device_idle_hwmods,
|
||||
.activate_func = omap_device_enable_hwmods,
|
||||
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
|
||||
}
|
||||
};
|
||||
|
||||
int __init hwspinlocks_init(void)
|
||||
{
|
||||
int retval = 0;
|
||||
struct omap_hwmod *oh;
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
const char *oh_name = "spinlock";
|
||||
const char *dev_name = "omap_hwspinlock";
|
||||
|
||||
@ -48,13 +40,11 @@ int __init hwspinlocks_init(void)
|
||||
if (oh == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
od = omap_device_build(dev_name, 0, oh, NULL, 0,
|
||||
omap_spinlock_latency,
|
||||
ARRAY_SIZE(omap_spinlock_latency), false);
|
||||
if (IS_ERR(od)) {
|
||||
pdev = omap_device_build(dev_name, 0, oh, NULL, 0, NULL, 0, false);
|
||||
if (IS_ERR(pdev)) {
|
||||
pr_err("Can't build omap_device for %s:%s\n", dev_name,
|
||||
oh_name);
|
||||
retval = PTR_ERR(od);
|
||||
retval = PTR_ERR(pdev);
|
||||
}
|
||||
|
||||
return retval;
|
||||
|
@ -28,7 +28,6 @@
|
||||
|
||||
#include "control.h"
|
||||
|
||||
static struct omap_chip_id omap_chip;
|
||||
static unsigned int omap_revision;
|
||||
|
||||
u32 omap_features;
|
||||
@ -39,19 +38,6 @@ unsigned int omap_rev(void)
|
||||
}
|
||||
EXPORT_SYMBOL(omap_rev);
|
||||
|
||||
/**
|
||||
* omap_chip_is - test whether currently running OMAP matches a chip type
|
||||
* @oc: omap_chip_t to test against
|
||||
*
|
||||
* Test whether the currently-running OMAP chip matches the supplied
|
||||
* chip type 'oc'. Returns 1 upon a match; 0 upon failure.
|
||||
*/
|
||||
int omap_chip_is(struct omap_chip_id oci)
|
||||
{
|
||||
return (oci.oc & omap_chip.oc) ? 1 : 0;
|
||||
}
|
||||
EXPORT_SYMBOL(omap_chip_is);
|
||||
|
||||
int omap_type(void)
|
||||
{
|
||||
u32 val = 0;
|
||||
@ -242,14 +228,12 @@ static void __init ti816x_check_features(void)
|
||||
omap_features = OMAP3_HAS_NEON;
|
||||
}
|
||||
|
||||
static void __init omap3_check_revision(void)
|
||||
static void __init omap3_check_revision(const char **cpu_rev)
|
||||
{
|
||||
u32 cpuid, idcode;
|
||||
u16 hawkeye;
|
||||
u8 rev;
|
||||
|
||||
omap_chip.oc = CHIP_IS_OMAP3430;
|
||||
|
||||
/*
|
||||
* We cannot access revision registers on ES1.0.
|
||||
* If the processor type is Cortex-A8 and the revision is 0x0
|
||||
@ -258,7 +242,7 @@ static void __init omap3_check_revision(void)
|
||||
cpuid = read_cpuid(CPUID_ID);
|
||||
if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
|
||||
omap_revision = OMAP3430_REV_ES1_0;
|
||||
omap_chip.oc |= CHIP_IS_OMAP3430ES1;
|
||||
*cpu_rev = "1.0";
|
||||
return;
|
||||
}
|
||||
|
||||
@ -279,77 +263,85 @@ static void __init omap3_check_revision(void)
|
||||
case 0: /* Take care of early samples */
|
||||
case 1:
|
||||
omap_revision = OMAP3430_REV_ES2_0;
|
||||
omap_chip.oc |= CHIP_IS_OMAP3430ES2;
|
||||
*cpu_rev = "2.0";
|
||||
break;
|
||||
case 2:
|
||||
omap_revision = OMAP3430_REV_ES2_1;
|
||||
omap_chip.oc |= CHIP_IS_OMAP3430ES2;
|
||||
*cpu_rev = "2.1";
|
||||
break;
|
||||
case 3:
|
||||
omap_revision = OMAP3430_REV_ES3_0;
|
||||
omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
|
||||
*cpu_rev = "3.0";
|
||||
break;
|
||||
case 4:
|
||||
omap_revision = OMAP3430_REV_ES3_1;
|
||||
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
|
||||
*cpu_rev = "3.1";
|
||||
break;
|
||||
case 7:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
/* Use the latest known revision as default */
|
||||
omap_revision = OMAP3430_REV_ES3_1_2;
|
||||
|
||||
/* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
|
||||
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
|
||||
*cpu_rev = "3.1.2";
|
||||
}
|
||||
break;
|
||||
case 0xb868:
|
||||
/* Handle OMAP35xx/AM35xx devices
|
||||
/*
|
||||
* Handle OMAP/AM 3505/3517 devices
|
||||
*
|
||||
* Set the device to be OMAP3505 here. Actual device
|
||||
* Set the device to be OMAP3517 here. Actual device
|
||||
* is identified later based on the features.
|
||||
*
|
||||
* REVISIT: AM3505/AM3517 should have their own CHIP_IS
|
||||
*/
|
||||
omap_revision = OMAP3505_REV(rev);
|
||||
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
|
||||
switch (rev) {
|
||||
case 0:
|
||||
omap_revision = OMAP3517_REV_ES1_0;
|
||||
*cpu_rev = "1.0";
|
||||
break;
|
||||
case 1:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = OMAP3517_REV_ES1_1;
|
||||
*cpu_rev = "1.1";
|
||||
}
|
||||
break;
|
||||
case 0xb891:
|
||||
/* Handle 36xx devices */
|
||||
omap_chip.oc |= CHIP_IS_OMAP3630ES1;
|
||||
|
||||
switch(rev) {
|
||||
case 0: /* Take care of early samples */
|
||||
omap_revision = OMAP3630_REV_ES1_0;
|
||||
*cpu_rev = "1.0";
|
||||
break;
|
||||
case 1:
|
||||
omap_revision = OMAP3630_REV_ES1_1;
|
||||
omap_chip.oc |= CHIP_IS_OMAP3630ES1_1;
|
||||
*cpu_rev = "1.1";
|
||||
break;
|
||||
case 2:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = OMAP3630_REV_ES1_2;
|
||||
omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
|
||||
omap_revision = OMAP3630_REV_ES1_2;
|
||||
*cpu_rev = "1.2";
|
||||
}
|
||||
break;
|
||||
case 0xb81e:
|
||||
omap_chip.oc = CHIP_IS_TI816X;
|
||||
|
||||
switch (rev) {
|
||||
case 0:
|
||||
omap_revision = TI8168_REV_ES1_0;
|
||||
*cpu_rev = "1.0";
|
||||
break;
|
||||
case 1:
|
||||
omap_revision = TI8168_REV_ES1_1;
|
||||
break;
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = TI8168_REV_ES1_1;
|
||||
omap_revision = TI8168_REV_ES1_1;
|
||||
*cpu_rev = "1.1";
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
/* Unknown default to latest silicon rev as default*/
|
||||
omap_revision = OMAP3630_REV_ES1_2;
|
||||
omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
|
||||
/* Unknown default to latest silicon rev as default */
|
||||
omap_revision = OMAP3630_REV_ES1_2;
|
||||
*cpu_rev = "1.2";
|
||||
pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
|
||||
}
|
||||
}
|
||||
|
||||
@ -382,24 +374,20 @@ static void __init omap4_check_revision(void)
|
||||
switch (rev) {
|
||||
case 0:
|
||||
omap_revision = OMAP4430_REV_ES1_0;
|
||||
omap_chip.oc |= CHIP_IS_OMAP4430ES1;
|
||||
break;
|
||||
case 1:
|
||||
default:
|
||||
omap_revision = OMAP4430_REV_ES2_0;
|
||||
omap_chip.oc |= CHIP_IS_OMAP4430ES2;
|
||||
}
|
||||
break;
|
||||
case 0xb95c:
|
||||
switch (rev) {
|
||||
case 3:
|
||||
omap_revision = OMAP4430_REV_ES2_1;
|
||||
omap_chip.oc |= CHIP_IS_OMAP4430ES2_1;
|
||||
break;
|
||||
case 4:
|
||||
default:
|
||||
omap_revision = OMAP4430_REV_ES2_2;
|
||||
omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
|
||||
}
|
||||
break;
|
||||
case 0xb94e:
|
||||
@ -407,14 +395,12 @@ static void __init omap4_check_revision(void)
|
||||
case 0:
|
||||
default:
|
||||
omap_revision = OMAP4460_REV_ES1_0;
|
||||
omap_chip.oc |= CHIP_IS_OMAP4460ES1_0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
/* Unknown default to latest silicon rev as default */
|
||||
omap_revision = OMAP4430_REV_ES2_2;
|
||||
omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
|
||||
}
|
||||
|
||||
pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
|
||||
@ -425,94 +411,33 @@ static void __init omap4_check_revision(void)
|
||||
if (omap3_has_ ##feat()) \
|
||||
printk(#feat" ");
|
||||
|
||||
static void __init omap3_cpuinfo(void)
|
||||
static void __init omap3_cpuinfo(const char *cpu_rev)
|
||||
{
|
||||
u8 rev = GET_OMAP_REVISION();
|
||||
char cpu_name[16], cpu_rev[16];
|
||||
const char *cpu_name;
|
||||
|
||||
/* OMAP3430 and OMAP3530 are assumed to be same.
|
||||
/*
|
||||
* OMAP3430 and OMAP3530 are assumed to be same.
|
||||
*
|
||||
* OMAP3525, OMAP3515 and OMAP3503 can be detected only based
|
||||
* on available features. Upon detection, update the CPU id
|
||||
* and CPU class bits.
|
||||
*/
|
||||
if (cpu_is_omap3630()) {
|
||||
strcpy(cpu_name, "OMAP3630");
|
||||
} else if (cpu_is_omap3505()) {
|
||||
/*
|
||||
* AM35xx devices
|
||||
*/
|
||||
if (omap3_has_sgx()) {
|
||||
omap_revision = OMAP3517_REV(rev);
|
||||
strcpy(cpu_name, "AM3517");
|
||||
} else {
|
||||
/* Already set in omap3_check_revision() */
|
||||
strcpy(cpu_name, "AM3505");
|
||||
}
|
||||
cpu_name = "OMAP3630";
|
||||
} else if (cpu_is_omap3517()) {
|
||||
/* AM35xx devices */
|
||||
cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
|
||||
} else if (cpu_is_ti816x()) {
|
||||
strcpy(cpu_name, "TI816X");
|
||||
cpu_name = "TI816X";
|
||||
} else if (omap3_has_iva() && omap3_has_sgx()) {
|
||||
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
|
||||
strcpy(cpu_name, "OMAP3430/3530");
|
||||
cpu_name = "OMAP3430/3530";
|
||||
} else if (omap3_has_iva()) {
|
||||
omap_revision = OMAP3525_REV(rev);
|
||||
strcpy(cpu_name, "OMAP3525");
|
||||
cpu_name = "OMAP3525";
|
||||
} else if (omap3_has_sgx()) {
|
||||
omap_revision = OMAP3515_REV(rev);
|
||||
strcpy(cpu_name, "OMAP3515");
|
||||
cpu_name = "OMAP3515";
|
||||
} else {
|
||||
omap_revision = OMAP3503_REV(rev);
|
||||
strcpy(cpu_name, "OMAP3503");
|
||||
}
|
||||
|
||||
if (cpu_is_omap3630() || cpu_is_ti816x()) {
|
||||
switch (rev) {
|
||||
case OMAP_REVBITS_00:
|
||||
strcpy(cpu_rev, "1.0");
|
||||
break;
|
||||
case OMAP_REVBITS_01:
|
||||
strcpy(cpu_rev, "1.1");
|
||||
break;
|
||||
case OMAP_REVBITS_02:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
/* Use the latest known revision as default */
|
||||
strcpy(cpu_rev, "1.2");
|
||||
}
|
||||
} else if (cpu_is_omap3505() || cpu_is_omap3517()) {
|
||||
switch (rev) {
|
||||
case OMAP_REVBITS_00:
|
||||
strcpy(cpu_rev, "1.0");
|
||||
break;
|
||||
case OMAP_REVBITS_01:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
/* Use the latest known revision as default */
|
||||
strcpy(cpu_rev, "1.1");
|
||||
}
|
||||
} else {
|
||||
switch (rev) {
|
||||
case OMAP_REVBITS_00:
|
||||
strcpy(cpu_rev, "1.0");
|
||||
break;
|
||||
case OMAP_REVBITS_01:
|
||||
strcpy(cpu_rev, "2.0");
|
||||
break;
|
||||
case OMAP_REVBITS_02:
|
||||
strcpy(cpu_rev, "2.1");
|
||||
break;
|
||||
case OMAP_REVBITS_03:
|
||||
strcpy(cpu_rev, "3.0");
|
||||
break;
|
||||
case OMAP_REVBITS_04:
|
||||
strcpy(cpu_rev, "3.1");
|
||||
break;
|
||||
case OMAP_REVBITS_05:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
/* Use the latest known revision as default */
|
||||
strcpy(cpu_rev, "3.1.2");
|
||||
}
|
||||
cpu_name = "OMAP3503";
|
||||
}
|
||||
|
||||
/* Print verbose information */
|
||||
@ -533,6 +458,8 @@ static void __init omap3_cpuinfo(void)
|
||||
*/
|
||||
void __init omap2_check_revision(void)
|
||||
{
|
||||
const char *cpu_rev;
|
||||
|
||||
/*
|
||||
* At this point we have an idea about the processor revision set
|
||||
* earlier with omap2_set_globals_tap().
|
||||
@ -540,7 +467,7 @@ void __init omap2_check_revision(void)
|
||||
if (cpu_is_omap24xx()) {
|
||||
omap24xx_check_revision();
|
||||
} else if (cpu_is_omap34xx()) {
|
||||
omap3_check_revision();
|
||||
omap3_check_revision(&cpu_rev);
|
||||
|
||||
/* TI816X doesn't have feature register */
|
||||
if (!cpu_is_ti816x())
|
||||
@ -548,7 +475,7 @@ void __init omap2_check_revision(void)
|
||||
else
|
||||
ti816x_check_features();
|
||||
|
||||
omap3_cpuinfo();
|
||||
omap3_cpuinfo(cpu_rev);
|
||||
return;
|
||||
} else if (cpu_is_omap44xx()) {
|
||||
omap4_check_revision();
|
||||
@ -557,22 +484,6 @@ void __init omap2_check_revision(void)
|
||||
} else {
|
||||
pr_err("OMAP revision unknown, please fix!\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* OK, now we know the exact revision. Initialize omap_chip bits
|
||||
* for powerdowmain and clockdomain code.
|
||||
*/
|
||||
if (cpu_is_omap243x()) {
|
||||
/* Currently only supports 2430ES2.1 and 2430-all */
|
||||
omap_chip.oc |= CHIP_IS_OMAP2430;
|
||||
return;
|
||||
} else if (cpu_is_omap242x()) {
|
||||
/* Currently only supports 2420ES2.1.1 and 2420-all */
|
||||
omap_chip.oc |= CHIP_IS_OMAP2420;
|
||||
return;
|
||||
}
|
||||
|
||||
pr_err("Uninitialized omap_chip, please fix!\n");
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -38,6 +38,7 @@
|
||||
#include "io.h"
|
||||
|
||||
#include <plat/omap-pm.h>
|
||||
#include "voltage.h"
|
||||
#include "powerdomain.h"
|
||||
|
||||
#include "clockdomain.h"
|
||||
@ -341,18 +342,22 @@ void __init omap2_init_common_infrastructure(void)
|
||||
u8 postsetup_state;
|
||||
|
||||
if (cpu_is_omap242x()) {
|
||||
omap2xxx_powerdomains_init();
|
||||
omap2xxx_clockdomains_init();
|
||||
omap2xxx_voltagedomains_init();
|
||||
omap242x_powerdomains_init();
|
||||
omap242x_clockdomains_init();
|
||||
omap2420_hwmod_init();
|
||||
} else if (cpu_is_omap243x()) {
|
||||
omap2xxx_powerdomains_init();
|
||||
omap2xxx_clockdomains_init();
|
||||
omap2xxx_voltagedomains_init();
|
||||
omap243x_powerdomains_init();
|
||||
omap243x_clockdomains_init();
|
||||
omap2430_hwmod_init();
|
||||
} else if (cpu_is_omap34xx()) {
|
||||
omap3xxx_voltagedomains_init();
|
||||
omap3xxx_powerdomains_init();
|
||||
omap3xxx_clockdomains_init();
|
||||
omap3xxx_hwmod_init();
|
||||
} else if (cpu_is_omap44xx()) {
|
||||
omap44xx_voltagedomains_init();
|
||||
omap44xx_powerdomains_init();
|
||||
omap44xx_clockdomains_init();
|
||||
omap44xx_hwmod_init();
|
||||
@ -376,7 +381,7 @@ void __init omap2_init_common_infrastructure(void)
|
||||
* omap_hwmod_late_init(), so boards that desire full watchdog
|
||||
* coverage of kernel initialization can reprogram the
|
||||
* postsetup_state between the calls to
|
||||
* omap2_init_common_infra() and omap2_init_common_devices().
|
||||
* omap2_init_common_infra() and omap_sdrc_init().
|
||||
*
|
||||
* XXX ideally we could detect whether the MPU WDT was currently
|
||||
* enabled here and make this conditional
|
||||
@ -400,7 +405,47 @@ void __init omap2_init_common_infrastructure(void)
|
||||
pr_err("Could not init clock framework - unknown SoC\n");
|
||||
}
|
||||
|
||||
void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
|
||||
void __init omap2420_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
}
|
||||
|
||||
void __init omap2430_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
}
|
||||
|
||||
void __init omap3430_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
}
|
||||
|
||||
void __init omap35xx_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
}
|
||||
|
||||
void __init omap3630_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
}
|
||||
|
||||
void __init am35xx_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
}
|
||||
|
||||
void __init ti816x_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
}
|
||||
|
||||
void __init omap4430_init_early(void)
|
||||
{
|
||||
omap2_init_common_infrastructure();
|
||||
}
|
||||
|
||||
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
|
||||
struct omap_sdrc_params *sdrc_cs1)
|
||||
{
|
||||
if (cpu_is_omap24xx() || omap3_has_sdrc()) {
|
||||
|
@ -165,8 +165,8 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
|
||||
|
||||
omap_irq_bank_init_one(bank);
|
||||
|
||||
for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20)
|
||||
omap_alloc_gc(bank->base_reg + j, i, 32);
|
||||
for (j = 0; j < bank->nr_irqs; j += 32)
|
||||
omap_alloc_gc(bank->base_reg + j, j, 32);
|
||||
|
||||
nr_of_irqs += bank->nr_irqs;
|
||||
nr_banks++;
|
||||
|
@ -27,66 +27,69 @@
|
||||
|
||||
#include "control.h"
|
||||
|
||||
/* McBSP internal signal muxing functions */
|
||||
/*
|
||||
* FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
|
||||
* Sidetone needs non-gated ICLK and sidetone autoidle is broken.
|
||||
*/
|
||||
#include "cm2xxx_3xxx.h"
|
||||
#include "cm-regbits-34xx.h"
|
||||
|
||||
void omap2_mcbsp1_mux_clkr_src(u8 mux)
|
||||
/* McBSP internal signal muxing function */
|
||||
static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
|
||||
const char *src)
|
||||
{
|
||||
u32 v;
|
||||
|
||||
v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
|
||||
if (mux == CLKR_SRC_CLKR)
|
||||
v &= ~OMAP2_MCBSP1_CLKR_MASK;
|
||||
else if (mux == CLKR_SRC_CLKX)
|
||||
v |= OMAP2_MCBSP1_CLKR_MASK;
|
||||
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
|
||||
}
|
||||
EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src);
|
||||
|
||||
void omap2_mcbsp1_mux_fsr_src(u8 mux)
|
||||
{
|
||||
u32 v;
|
||||
if (!strcmp(signal, "clkr")) {
|
||||
if (!strcmp(src, "clkr"))
|
||||
v &= ~OMAP2_MCBSP1_CLKR_MASK;
|
||||
else if (!strcmp(src, "clkx"))
|
||||
v |= OMAP2_MCBSP1_CLKR_MASK;
|
||||
else
|
||||
return -EINVAL;
|
||||
} else if (!strcmp(signal, "fsr")) {
|
||||
if (!strcmp(src, "fsr"))
|
||||
v &= ~OMAP2_MCBSP1_FSR_MASK;
|
||||
else if (!strcmp(src, "fsx"))
|
||||
v |= OMAP2_MCBSP1_FSR_MASK;
|
||||
else
|
||||
return -EINVAL;
|
||||
} else {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
|
||||
if (mux == FSR_SRC_FSR)
|
||||
v &= ~OMAP2_MCBSP1_FSR_MASK;
|
||||
else if (mux == FSR_SRC_FSX)
|
||||
v |= OMAP2_MCBSP1_FSR_MASK;
|
||||
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src);
|
||||
|
||||
/* McBSP CLKS source switching function */
|
||||
|
||||
int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
|
||||
static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
|
||||
const char *src)
|
||||
{
|
||||
struct omap_mcbsp *mcbsp;
|
||||
struct clk *fck_src;
|
||||
char *fck_src_name;
|
||||
int r;
|
||||
|
||||
if (!omap_mcbsp_check_valid_id(id)) {
|
||||
pr_err("%s: Invalid id (%d)\n", __func__, id + 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
mcbsp = id_to_mcbsp_ptr(id);
|
||||
|
||||
if (fck_src_id == MCBSP_CLKS_PAD_SRC)
|
||||
if (!strcmp(src, "clks_ext"))
|
||||
fck_src_name = "pad_fck";
|
||||
else if (fck_src_id == MCBSP_CLKS_PRCM_SRC)
|
||||
else if (!strcmp(src, "clks_fclk"))
|
||||
fck_src_name = "prcm_fck";
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
fck_src = clk_get(mcbsp->dev, fck_src_name);
|
||||
fck_src = clk_get(dev, fck_src_name);
|
||||
if (IS_ERR_OR_NULL(fck_src)) {
|
||||
pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
|
||||
fck_src_name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pm_runtime_put_sync(mcbsp->dev);
|
||||
pm_runtime_put_sync(dev);
|
||||
|
||||
r = clk_set_parent(mcbsp->fclk, fck_src);
|
||||
r = clk_set_parent(clk, fck_src);
|
||||
if (IS_ERR_VALUE(r)) {
|
||||
pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
|
||||
"clks", fck_src_name);
|
||||
@ -94,21 +97,30 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pm_runtime_get_sync(mcbsp->dev);
|
||||
pm_runtime_get_sync(dev);
|
||||
|
||||
clk_put(fck_src);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
|
||||
|
||||
struct omap_device_pm_latency omap2_mcbsp_latency[] = {
|
||||
{
|
||||
.deactivate_func = omap_device_idle_hwmods,
|
||||
.activate_func = omap_device_enable_hwmods,
|
||||
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
|
||||
},
|
||||
};
|
||||
static int omap3_enable_st_clock(unsigned int id, bool enable)
|
||||
{
|
||||
unsigned int w;
|
||||
|
||||
/*
|
||||
* Sidetone uses McBSP ICLK - which must not idle when sidetones
|
||||
* are enabled or sidetones start sounding ugly.
|
||||
*/
|
||||
w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
|
||||
if (enable)
|
||||
w &= ~(1 << (id - 2));
|
||||
else
|
||||
w |= 1 << (id - 2);
|
||||
omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
|
||||
{
|
||||
@ -116,7 +128,7 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
|
||||
char *name = "omap-mcbsp";
|
||||
struct omap_hwmod *oh_device[2];
|
||||
struct omap_mcbsp_platform_data *pdata = NULL;
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
|
||||
sscanf(oh->name, "mcbsp%d", &id);
|
||||
|
||||
@ -126,7 +138,13 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
pdata->mcbsp_config_type = oh->class->rev;
|
||||
pdata->reg_step = 4;
|
||||
if (oh->class->rev < MCBSP_CONFIG_TYPE2) {
|
||||
pdata->reg_size = 2;
|
||||
} else {
|
||||
pdata->reg_size = 4;
|
||||
pdata->has_ccr = true;
|
||||
}
|
||||
|
||||
if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
|
||||
if (id == 2)
|
||||
@ -137,22 +155,28 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
|
||||
pdata->buffer_size = 0x80;
|
||||
}
|
||||
|
||||
if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
|
||||
pdata->has_wakeup = true;
|
||||
|
||||
oh_device[0] = oh;
|
||||
|
||||
if (oh->dev_attr) {
|
||||
oh_device[1] = omap_hwmod_lookup((
|
||||
(struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
|
||||
pdata->enable_st_clock = omap3_enable_st_clock;
|
||||
count++;
|
||||
}
|
||||
od = omap_device_build_ss(name, id, oh_device, count, pdata,
|
||||
sizeof(*pdata), omap2_mcbsp_latency,
|
||||
ARRAY_SIZE(omap2_mcbsp_latency), false);
|
||||
pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
|
||||
sizeof(*pdata), NULL, 0, false);
|
||||
kfree(pdata);
|
||||
if (IS_ERR(od)) {
|
||||
if (IS_ERR(pdev)) {
|
||||
pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
|
||||
name, oh->name);
|
||||
return PTR_ERR(od);
|
||||
return PTR_ERR(pdev);
|
||||
}
|
||||
pdata->set_clk_src = omap2_mcbsp_set_clk_src;
|
||||
if (id == 1)
|
||||
pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
|
||||
omap_mcbsp_count++;
|
||||
return 0;
|
||||
}
|
||||
|
@ -1954,9 +1954,6 @@ int __init omap_hwmod_register(struct omap_hwmod **ohs)
|
||||
|
||||
i = 0;
|
||||
do {
|
||||
if (!omap_chip_is(ohs[i]->omap_chip))
|
||||
continue;
|
||||
|
||||
r = _register(ohs[i]);
|
||||
WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
|
||||
r);
|
||||
|
@ -100,7 +100,6 @@ static struct omap_hwmod omap2420_l3_main_hwmod = {
|
||||
.masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters),
|
||||
.slaves = omap2420_l3_main_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -206,7 +205,6 @@ static struct omap_hwmod omap2420_l4_core_hwmod = {
|
||||
.masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters),
|
||||
.slaves = omap2420_l4_core_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -227,7 +225,6 @@ static struct omap_hwmod omap2420_l4_wkup_hwmod = {
|
||||
.masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters),
|
||||
.slaves = omap2420_l4_wkup_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -243,7 +240,6 @@ static struct omap_hwmod omap2420_mpu_hwmod = {
|
||||
.main_clk = "mpu_ck",
|
||||
.masters = omap2420_mpu_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap2420_mpu_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -271,7 +267,16 @@ static struct omap_hwmod omap2420_iva_hwmod = {
|
||||
.class = &iva_hwmod_class,
|
||||
.masters = omap2420_iva_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap2420_iva_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* always-on timers dev attribute */
|
||||
static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
|
||||
.timer_capability = OMAP_TIMER_ALWON,
|
||||
};
|
||||
|
||||
/* pwm timers dev attribute */
|
||||
static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
|
||||
.timer_capability = OMAP_TIMER_HAS_PWM,
|
||||
};
|
||||
|
||||
/* timer1 */
|
||||
@ -314,10 +319,10 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2420_timer1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* timer2 */
|
||||
@ -351,10 +356,10 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2420_timer2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* timer3 */
|
||||
@ -388,10 +393,10 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2420_timer3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* timer4 */
|
||||
@ -425,10 +430,10 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2420_timer4_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* timer5 */
|
||||
@ -462,10 +467,10 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2420_timer5_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
|
||||
@ -500,10 +505,10 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2420_timer6_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* timer7 */
|
||||
@ -537,10 +542,10 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2420_timer7_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* timer8 */
|
||||
@ -574,10 +579,10 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2420_timer8_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* timer9 */
|
||||
@ -611,10 +616,10 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap2420_timer9_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* timer10 */
|
||||
@ -648,10 +653,10 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap2420_timer10_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* timer11 */
|
||||
@ -685,10 +690,10 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap2420_timer11_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* timer12 */
|
||||
@ -722,10 +727,10 @@ static struct omap_hwmod omap2420_timer12_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap2420_timer12_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
|
||||
};
|
||||
|
||||
/* l4_wkup -> wd_timer2 */
|
||||
@ -766,7 +771,6 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = {
|
||||
},
|
||||
.slaves = omap2420_wd_timer2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
/* UART1 */
|
||||
@ -792,7 +796,6 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
|
||||
.slaves = omap2420_uart1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
|
||||
.class = &omap2_uart_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
/* UART2 */
|
||||
@ -818,7 +821,6 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
|
||||
.slaves = omap2420_uart2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
|
||||
.class = &omap2_uart_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
/* UART3 */
|
||||
@ -844,7 +846,6 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
|
||||
.slaves = omap2420_uart3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
|
||||
.class = &omap2_uart_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
/* dss */
|
||||
@ -898,7 +899,6 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves),
|
||||
.masters = omap2420_dss_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap2420_dss_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -938,7 +938,6 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
|
||||
},
|
||||
.slaves = omap2420_dss_dispc_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -975,7 +974,6 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
|
||||
},
|
||||
.slaves = omap2420_dss_rfbi_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -1013,7 +1011,6 @@ static struct omap_hwmod omap2420_dss_venc_hwmod = {
|
||||
},
|
||||
.slaves = omap2420_dss_venc_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -1064,7 +1061,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves),
|
||||
.class = &i2c_class,
|
||||
.dev_attr = &i2c_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
.flags = HWMOD_16BIT_REG,
|
||||
};
|
||||
|
||||
@ -1092,7 +1088,6 @@ static struct omap_hwmod omap2420_i2c2_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves),
|
||||
.class = &i2c_class,
|
||||
.dev_attr = &i2c_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
.flags = HWMOD_16BIT_REG,
|
||||
};
|
||||
|
||||
@ -1197,7 +1192,6 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
/* gpio2 */
|
||||
@ -1223,7 +1217,6 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
/* gpio3 */
|
||||
@ -1249,7 +1242,6 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
/* gpio4 */
|
||||
@ -1275,7 +1267,6 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
/* dma attributes */
|
||||
@ -1322,7 +1313,6 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
|
||||
.masters = omap2420_dma_system_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters),
|
||||
.dev_attr = &dma_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -1363,7 +1353,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
|
||||
},
|
||||
.slaves = omap2420_mailbox_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
/* mcspi1 */
|
||||
@ -1393,7 +1382,6 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
|
||||
.class = &omap2xxx_mcspi_class,
|
||||
.dev_attr = &omap_mcspi1_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
/* mcspi2 */
|
||||
@ -1423,7 +1411,6 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
|
||||
.class = &omap2xxx_mcspi_class,
|
||||
.dev_attr = &omap_mcspi2_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -1473,7 +1460,6 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
|
||||
},
|
||||
.slaves = omap2420_mcbsp1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
/* mcbsp2 */
|
||||
@ -1514,7 +1500,6 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
|
||||
},
|
||||
.slaves = omap2420_mcbsp2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
|
||||
};
|
||||
|
||||
static __initdata struct omap_hwmod *omap2420_hwmods[] = {
|
||||
|
@ -110,7 +110,6 @@ static struct omap_hwmod omap2430_l3_main_hwmod = {
|
||||
.masters_cnt = ARRAY_SIZE(omap2430_l3_main_masters),
|
||||
.slaves = omap2430_l3_main_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_l3_main_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -250,7 +249,6 @@ static struct omap_hwmod omap2430_l4_core_hwmod = {
|
||||
.masters_cnt = ARRAY_SIZE(omap2430_l4_core_masters),
|
||||
.slaves = omap2430_l4_core_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_l4_core_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -301,7 +299,6 @@ static struct omap_hwmod omap2430_l4_wkup_hwmod = {
|
||||
.masters_cnt = ARRAY_SIZE(omap2430_l4_wkup_masters),
|
||||
.slaves = omap2430_l4_wkup_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_l4_wkup_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -317,7 +314,6 @@ static struct omap_hwmod omap2430_mpu_hwmod = {
|
||||
.main_clk = "mpu_ck",
|
||||
.masters = omap2430_mpu_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap2430_mpu_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -345,7 +341,16 @@ static struct omap_hwmod omap2430_iva_hwmod = {
|
||||
.class = &iva_hwmod_class,
|
||||
.masters = omap2430_iva_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap2430_iva_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
};
|
||||
|
||||
/* always-on timers dev attribute */
|
||||
static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
|
||||
.timer_capability = OMAP_TIMER_ALWON,
|
||||
};
|
||||
|
||||
/* pwm timers dev attribute */
|
||||
static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
|
||||
.timer_capability = OMAP_TIMER_HAS_PWM,
|
||||
};
|
||||
|
||||
/* timer1 */
|
||||
@ -388,10 +393,10 @@ static struct omap_hwmod omap2430_timer1_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2430_timer1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
};
|
||||
|
||||
/* timer2 */
|
||||
@ -425,10 +430,10 @@ static struct omap_hwmod omap2430_timer2_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2430_timer2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
};
|
||||
|
||||
/* timer3 */
|
||||
@ -462,10 +467,10 @@ static struct omap_hwmod omap2430_timer3_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2430_timer3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
};
|
||||
|
||||
/* timer4 */
|
||||
@ -499,10 +504,10 @@ static struct omap_hwmod omap2430_timer4_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2430_timer4_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
};
|
||||
|
||||
/* timer5 */
|
||||
@ -536,10 +541,10 @@ static struct omap_hwmod omap2430_timer5_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2430_timer5_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
};
|
||||
|
||||
/* timer6 */
|
||||
@ -573,10 +578,10 @@ static struct omap_hwmod omap2430_timer6_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2430_timer6_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
};
|
||||
|
||||
/* timer7 */
|
||||
@ -610,10 +615,10 @@ static struct omap_hwmod omap2430_timer7_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2430_timer7_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
};
|
||||
|
||||
/* timer8 */
|
||||
@ -647,10 +652,10 @@ static struct omap_hwmod omap2430_timer8_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap2430_timer8_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
};
|
||||
|
||||
/* timer9 */
|
||||
@ -684,10 +689,10 @@ static struct omap_hwmod omap2430_timer9_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap2430_timer9_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
};
|
||||
|
||||
/* timer10 */
|
||||
@ -721,10 +726,10 @@ static struct omap_hwmod omap2430_timer10_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap2430_timer10_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
};
|
||||
|
||||
/* timer11 */
|
||||
@ -758,10 +763,10 @@ static struct omap_hwmod omap2430_timer11_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap2430_timer11_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
};
|
||||
|
||||
/* timer12 */
|
||||
@ -795,10 +800,10 @@ static struct omap_hwmod omap2430_timer12_hwmod = {
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap2430_timer12_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
};
|
||||
|
||||
/* l4_wkup -> wd_timer2 */
|
||||
@ -839,7 +844,6 @@ static struct omap_hwmod omap2430_wd_timer2_hwmod = {
|
||||
},
|
||||
.slaves = omap2430_wd_timer2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* UART1 */
|
||||
@ -865,7 +869,6 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
|
||||
.slaves = omap2430_uart1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
|
||||
.class = &omap2_uart_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* UART2 */
|
||||
@ -891,7 +894,6 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
|
||||
.slaves = omap2430_uart2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
|
||||
.class = &omap2_uart_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* UART3 */
|
||||
@ -917,7 +919,6 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
|
||||
.slaves = omap2430_uart3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
|
||||
.class = &omap2_uart_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* dss */
|
||||
@ -965,7 +966,6 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves),
|
||||
.masters = omap2430_dss_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap2430_dss_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -999,7 +999,6 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
|
||||
},
|
||||
.slaves = omap2430_dss_dispc_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -1030,7 +1029,6 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
|
||||
},
|
||||
.slaves = omap2430_dss_rfbi_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -1062,7 +1060,6 @@ static struct omap_hwmod omap2430_dss_venc_hwmod = {
|
||||
},
|
||||
.slaves = omap2430_dss_venc_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -1123,7 +1120,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves),
|
||||
.class = &i2c_class,
|
||||
.dev_attr = &i2c_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* I2C2 */
|
||||
@ -1151,7 +1147,6 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves),
|
||||
.class = &i2c_class,
|
||||
.dev_attr = &i2c_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* l4_wkup -> gpio1 */
|
||||
@ -1273,7 +1268,6 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* gpio2 */
|
||||
@ -1299,7 +1293,6 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* gpio3 */
|
||||
@ -1325,7 +1318,6 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* gpio4 */
|
||||
@ -1351,7 +1343,6 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* gpio5 */
|
||||
@ -1382,7 +1373,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* dma attributes */
|
||||
@ -1429,7 +1419,6 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
|
||||
.masters = omap2430_dma_system_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters),
|
||||
.dev_attr = &dma_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -1469,7 +1458,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
|
||||
},
|
||||
.slaves = omap2430_mailbox_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* mcspi1 */
|
||||
@ -1499,7 +1487,6 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
|
||||
.class = &omap2xxx_mcspi_class,
|
||||
.dev_attr = &omap_mcspi1_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* mcspi2 */
|
||||
@ -1529,7 +1516,6 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
|
||||
.class = &omap2xxx_mcspi_class,
|
||||
.dev_attr = &omap_mcspi2_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* mcspi3 */
|
||||
@ -1572,7 +1558,6 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
|
||||
.class = &omap2xxx_mcspi_class,
|
||||
.dev_attr = &omap_mcspi3_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -1628,7 +1613,6 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
|
||||
*/
|
||||
.flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
|
||||
| HWMOD_SWSUP_MSTANDBY,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
|
||||
};
|
||||
|
||||
/*
|
||||
@ -1689,7 +1673,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
|
||||
},
|
||||
.slaves = omap2430_mcbsp1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* mcbsp2 */
|
||||
@ -1731,7 +1714,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
|
||||
},
|
||||
.slaves = omap2430_mcbsp2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* mcbsp3 */
|
||||
@ -1783,7 +1765,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
|
||||
},
|
||||
.slaves = omap2430_mcbsp3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* mcbsp4 */
|
||||
@ -1841,7 +1822,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
|
||||
},
|
||||
.slaves = omap2430_mcbsp4_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* mcbsp5 */
|
||||
@ -1899,7 +1879,6 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
|
||||
},
|
||||
.slaves = omap2430_mcbsp5_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* MMC/SD/SDIO common */
|
||||
@ -1966,7 +1945,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
|
||||
.slaves = omap2430_mmc1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves),
|
||||
.class = &omap2430_mmc_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
/* MMC/SD/SDIO2 */
|
||||
@ -2010,7 +1988,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
|
||||
.slaves = omap2430_mmc2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves),
|
||||
.class = &omap2430_mmc_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
};
|
||||
|
||||
static __initdata struct omap_hwmod *omap2430_hwmods[] = {
|
||||
|
@ -156,7 +156,6 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod = {
|
||||
.masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
|
||||
.slaves = omap3xxx_l3_main_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -459,7 +458,6 @@ static struct omap_hwmod omap3xxx_l4_core_hwmod = {
|
||||
.class = &l4_hwmod_class,
|
||||
.slaves = omap3xxx_l4_core_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -474,7 +472,6 @@ static struct omap_hwmod omap3xxx_l4_per_hwmod = {
|
||||
.class = &l4_hwmod_class,
|
||||
.slaves = omap3xxx_l4_per_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -489,7 +486,6 @@ static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
|
||||
.class = &l4_hwmod_class,
|
||||
.slaves = omap3xxx_l4_wkup_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -505,7 +501,6 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
|
||||
.main_clk = "arm_fck",
|
||||
.masters = omap3xxx_mpu_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -533,7 +528,6 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
|
||||
.class = &iva_hwmod_class,
|
||||
.masters = omap3xxx_iva_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
};
|
||||
|
||||
/* timer class */
|
||||
@ -570,6 +564,21 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
|
||||
.rev = OMAP_TIMER_IP_VERSION_1,
|
||||
};
|
||||
|
||||
/* secure timers dev attribute */
|
||||
static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
|
||||
.timer_capability = OMAP_TIMER_SECURE,
|
||||
};
|
||||
|
||||
/* always-on timers dev attribute */
|
||||
static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
|
||||
.timer_capability = OMAP_TIMER_ALWON,
|
||||
};
|
||||
|
||||
/* pwm timers dev attribute */
|
||||
static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
|
||||
.timer_capability = OMAP_TIMER_HAS_PWM,
|
||||
};
|
||||
|
||||
/* timer1 */
|
||||
static struct omap_hwmod omap3xxx_timer1_hwmod;
|
||||
|
||||
@ -610,10 +619,10 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
|
||||
.idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap3xxx_timer1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
|
||||
.class = &omap3xxx_timer_1ms_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
};
|
||||
|
||||
/* timer2 */
|
||||
@ -656,10 +665,10 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
|
||||
.idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap3xxx_timer2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
|
||||
.class = &omap3xxx_timer_1ms_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
};
|
||||
|
||||
/* timer3 */
|
||||
@ -702,10 +711,10 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
|
||||
.idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap3xxx_timer3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
|
||||
.class = &omap3xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
};
|
||||
|
||||
/* timer4 */
|
||||
@ -748,10 +757,10 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
|
||||
.idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap3xxx_timer4_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
|
||||
.class = &omap3xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
};
|
||||
|
||||
/* timer5 */
|
||||
@ -794,10 +803,10 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
|
||||
.idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap3xxx_timer5_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
|
||||
.class = &omap3xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
};
|
||||
|
||||
/* timer6 */
|
||||
@ -840,10 +849,10 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
|
||||
.idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap3xxx_timer6_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
|
||||
.class = &omap3xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
};
|
||||
|
||||
/* timer7 */
|
||||
@ -886,10 +895,10 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
|
||||
.idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap3xxx_timer7_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
|
||||
.class = &omap3xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
};
|
||||
|
||||
/* timer8 */
|
||||
@ -932,10 +941,10 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
|
||||
.idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap3xxx_timer8_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
|
||||
.class = &omap3xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
};
|
||||
|
||||
/* timer9 */
|
||||
@ -978,10 +987,10 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
|
||||
.idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap3xxx_timer9_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
|
||||
.class = &omap3xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
};
|
||||
|
||||
/* timer10 */
|
||||
@ -1015,10 +1024,10 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
|
||||
.idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap3xxx_timer10_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
|
||||
.class = &omap3xxx_timer_1ms_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
};
|
||||
|
||||
/* timer11 */
|
||||
@ -1052,10 +1061,10 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
|
||||
.idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap3xxx_timer11_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
|
||||
.class = &omap3xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
};
|
||||
|
||||
/* timer12*/
|
||||
@ -1102,10 +1111,10 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
|
||||
.idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_secure_dev_attr,
|
||||
.slaves = omap3xxx_timer12_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
|
||||
.class = &omap3xxx_timer_hwmod_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
};
|
||||
|
||||
/* l4_wkup -> wd_timer2 */
|
||||
@ -1182,7 +1191,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
|
||||
},
|
||||
.slaves = omap3xxx_wd_timer2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
/*
|
||||
* XXX: Use software supervised mode, HW supervised smartidle seems to
|
||||
* block CORE power domain idle transitions. Maybe a HW bug in wdt2?
|
||||
@ -1213,7 +1221,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
|
||||
.slaves = omap3xxx_uart1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
|
||||
.class = &omap2_uart_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* UART2 */
|
||||
@ -1239,7 +1246,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
|
||||
.slaves = omap3xxx_uart2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
|
||||
.class = &omap2_uart_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* UART3 */
|
||||
@ -1265,7 +1271,6 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
|
||||
.slaves = omap3xxx_uart3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
|
||||
.class = &omap2_uart_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* UART4 */
|
||||
@ -1302,7 +1307,6 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
|
||||
.slaves = omap3xxx_uart4_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
|
||||
.class = &omap2_uart_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class i2c_class = {
|
||||
@ -1390,7 +1394,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
|
||||
.masters = omap3xxx_dss_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -1415,8 +1418,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
|
||||
.masters = omap3xxx_dss_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
|
||||
CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
|
||||
};
|
||||
|
||||
/* l4_core -> dss_dispc */
|
||||
@ -1454,9 +1455,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
|
||||
},
|
||||
.slaves = omap3xxx_dss_dispc_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
|
||||
CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
|
||||
CHIP_GE_OMAP3630ES1_1),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -1518,9 +1516,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
|
||||
},
|
||||
.slaves = omap3xxx_dss_dsi1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
|
||||
CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
|
||||
CHIP_GE_OMAP3630ES1_1),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -1558,9 +1553,6 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
|
||||
},
|
||||
.slaves = omap3xxx_dss_rfbi_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
|
||||
CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
|
||||
CHIP_GE_OMAP3630ES1_1),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -1599,9 +1591,6 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
|
||||
},
|
||||
.slaves = omap3xxx_dss_venc_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
|
||||
CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
|
||||
CHIP_GE_OMAP3630ES1_1),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -1637,7 +1626,6 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
|
||||
.class = &i2c_class,
|
||||
.dev_attr = &i2c1_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* I2C2 */
|
||||
@ -1672,7 +1660,6 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
|
||||
.class = &i2c_class,
|
||||
.dev_attr = &i2c2_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* I2C3 */
|
||||
@ -1718,7 +1705,6 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
|
||||
.class = &i2c_class,
|
||||
.dev_attr = &i2c3_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* l4_wkup -> gpio1 */
|
||||
@ -1880,7 +1866,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
|
||||
.class = &omap3xxx_gpio_hwmod_class,
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* gpio2 */
|
||||
@ -1912,7 +1897,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
|
||||
.class = &omap3xxx_gpio_hwmod_class,
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* gpio3 */
|
||||
@ -1944,7 +1928,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
|
||||
.class = &omap3xxx_gpio_hwmod_class,
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* gpio4 */
|
||||
@ -1976,7 +1959,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
|
||||
.class = &omap3xxx_gpio_hwmod_class,
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* gpio5 */
|
||||
@ -2013,7 +1995,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
|
||||
.class = &omap3xxx_gpio_hwmod_class,
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* gpio6 */
|
||||
@ -2050,7 +2031,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
|
||||
.class = &omap3xxx_gpio_hwmod_class,
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* dma_system -> L3 */
|
||||
@ -2134,7 +2114,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
|
||||
.masters = omap3xxx_dma_system_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
|
||||
.dev_attr = &dma_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
@ -2207,7 +2186,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
|
||||
},
|
||||
.slaves = omap3xxx_mcbsp1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* mcbsp2 */
|
||||
@ -2264,7 +2242,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
|
||||
.slaves = omap3xxx_mcbsp2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
|
||||
.dev_attr = &omap34xx_mcbsp2_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* mcbsp3 */
|
||||
@ -2321,7 +2298,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
|
||||
.slaves = omap3xxx_mcbsp3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
|
||||
.dev_attr = &omap34xx_mcbsp3_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* mcbsp4 */
|
||||
@ -2379,7 +2355,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
|
||||
},
|
||||
.slaves = omap3xxx_mcbsp4_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* mcbsp5 */
|
||||
@ -2437,7 +2412,6 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
|
||||
},
|
||||
.slaves = omap3xxx_mcbsp5_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
/* 'mcbsp sidetone' class */
|
||||
|
||||
@ -2498,7 +2472,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
|
||||
},
|
||||
.slaves = omap3xxx_mcbsp2_sidetone_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* mcbsp3_sidetone */
|
||||
@ -2547,7 +2520,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
|
||||
},
|
||||
.slaves = omap3xxx_mcbsp3_sidetone_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
|
||||
@ -2597,7 +2569,7 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
|
||||
.name = "sr1_hwmod",
|
||||
.class = &omap34xx_smartreflex_hwmod_class,
|
||||
.main_clk = "sr1_fck",
|
||||
.vdd_name = "mpu",
|
||||
.vdd_name = "mpu_iva",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
@ -2609,9 +2581,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
|
||||
},
|
||||
.slaves = omap3_sr1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
|
||||
CHIP_IS_OMAP3430ES3_0 |
|
||||
CHIP_IS_OMAP3430ES3_1),
|
||||
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
|
||||
};
|
||||
|
||||
@ -2619,7 +2588,7 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
|
||||
.name = "sr1_hwmod",
|
||||
.class = &omap36xx_smartreflex_hwmod_class,
|
||||
.main_clk = "sr1_fck",
|
||||
.vdd_name = "mpu",
|
||||
.vdd_name = "mpu_iva",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
@ -2631,7 +2600,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
|
||||
},
|
||||
.slaves = omap3_sr1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
|
||||
};
|
||||
|
||||
/* SR2 */
|
||||
@ -2655,9 +2623,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
|
||||
},
|
||||
.slaves = omap3_sr2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
|
||||
CHIP_IS_OMAP3430ES3_0 |
|
||||
CHIP_IS_OMAP3430ES3_1),
|
||||
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
|
||||
};
|
||||
|
||||
@ -2677,7 +2642,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
|
||||
},
|
||||
.slaves = omap3_sr2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -2745,7 +2709,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
|
||||
},
|
||||
.slaves = omap3xxx_mailbox_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* l4 core -> mcspi1 interface */
|
||||
@ -2843,7 +2806,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
|
||||
.class = &omap34xx_mcspi_class,
|
||||
.dev_attr = &omap_mcspi1_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* mcspi2 */
|
||||
@ -2873,7 +2835,6 @@ static struct omap_hwmod omap34xx_mcspi2 = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
|
||||
.class = &omap34xx_mcspi_class,
|
||||
.dev_attr = &omap_mcspi2_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* mcspi3 */
|
||||
@ -2916,7 +2877,6 @@ static struct omap_hwmod omap34xx_mcspi3 = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
|
||||
.class = &omap34xx_mcspi_class,
|
||||
.dev_attr = &omap_mcspi3_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* SPI4 */
|
||||
@ -2957,7 +2917,6 @@ static struct omap_hwmod omap34xx_mcspi4 = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
|
||||
.class = &omap34xx_mcspi_class,
|
||||
.dev_attr = &omap_mcspi4_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -3014,7 +2973,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
|
||||
*/
|
||||
.flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
|
||||
| HWMOD_SWSUP_MSTANDBY,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
|
||||
};
|
||||
|
||||
/* usb_otg_hs */
|
||||
@ -3042,7 +3000,6 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
|
||||
.slaves = am35xx_usbhsotg_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
|
||||
.class = &am35xx_usbotg_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
|
||||
};
|
||||
|
||||
/* MMC/SD/SDIO common */
|
||||
@ -3108,7 +3065,6 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
|
||||
.slaves = omap3xxx_mmc1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
|
||||
.class = &omap34xx_mmc_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* MMC/SD/SDIO2 */
|
||||
@ -3151,7 +3107,6 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
|
||||
.slaves = omap3xxx_mmc2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
|
||||
.class = &omap34xx_mmc_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
/* MMC/SD/SDIO3 */
|
||||
@ -3193,7 +3148,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
|
||||
.slaves = omap3xxx_mmc3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
|
||||
.class = &omap34xx_mmc_class,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
};
|
||||
|
||||
static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
|
||||
@ -3224,10 +3178,7 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
|
||||
&omap3xxx_uart1_hwmod,
|
||||
&omap3xxx_uart2_hwmod,
|
||||
&omap3xxx_uart3_hwmod,
|
||||
&omap3xxx_uart4_hwmod,
|
||||
/* dss class */
|
||||
&omap3430es1_dss_core_hwmod,
|
||||
&omap3xxx_dss_core_hwmod,
|
||||
&omap3xxx_dss_dispc_hwmod,
|
||||
&omap3xxx_dss_dsi1_hwmod,
|
||||
&omap3xxx_dss_rfbi_hwmod,
|
||||
@ -3239,9 +3190,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
|
||||
&omap3xxx_i2c3_hwmod,
|
||||
&omap34xx_sr1_hwmod,
|
||||
&omap34xx_sr2_hwmod,
|
||||
&omap36xx_sr1_hwmod,
|
||||
&omap36xx_sr2_hwmod,
|
||||
|
||||
|
||||
/* gpio class */
|
||||
&omap3xxx_gpio1_hwmod,
|
||||
@ -3272,16 +3220,96 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
|
||||
&omap34xx_mcspi3,
|
||||
&omap34xx_mcspi4,
|
||||
|
||||
/* usbotg class */
|
||||
&omap3xxx_usbhsotg_hwmod,
|
||||
|
||||
/* usbotg for am35x */
|
||||
&am35xx_usbhsotg_hwmod,
|
||||
|
||||
NULL,
|
||||
};
|
||||
|
||||
/* 3430ES1-only hwmods */
|
||||
static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
|
||||
&omap3430es1_dss_core_hwmod,
|
||||
NULL
|
||||
};
|
||||
|
||||
/* 3430ES2+-only hwmods */
|
||||
static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
|
||||
&omap3xxx_dss_core_hwmod,
|
||||
&omap3xxx_usbhsotg_hwmod,
|
||||
NULL
|
||||
};
|
||||
|
||||
/* 34xx-only hwmods (all ES revisions) */
|
||||
static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
|
||||
&omap34xx_sr1_hwmod,
|
||||
&omap34xx_sr2_hwmod,
|
||||
NULL
|
||||
};
|
||||
|
||||
/* 36xx-only hwmods (all ES revisions) */
|
||||
static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
|
||||
&omap3xxx_uart4_hwmod,
|
||||
&omap3xxx_dss_core_hwmod,
|
||||
&omap36xx_sr1_hwmod,
|
||||
&omap36xx_sr2_hwmod,
|
||||
&omap3xxx_usbhsotg_hwmod,
|
||||
NULL
|
||||
};
|
||||
|
||||
static __initdata struct omap_hwmod *am35xx_hwmods[] = {
|
||||
&omap3xxx_dss_core_hwmod, /* XXX ??? */
|
||||
&am35xx_usbhsotg_hwmod,
|
||||
NULL
|
||||
};
|
||||
|
||||
int __init omap3xxx_hwmod_init(void)
|
||||
{
|
||||
return omap_hwmod_register(omap3xxx_hwmods);
|
||||
int r;
|
||||
struct omap_hwmod **h = NULL;
|
||||
unsigned int rev;
|
||||
|
||||
/* Register hwmods common to all OMAP3 */
|
||||
r = omap_hwmod_register(omap3xxx_hwmods);
|
||||
if (!r)
|
||||
return r;
|
||||
|
||||
rev = omap_rev();
|
||||
|
||||
/*
|
||||
* Register hwmods common to individual OMAP3 families, all
|
||||
* silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
|
||||
* All possible revisions should be included in this conditional.
|
||||
*/
|
||||
if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
|
||||
rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
|
||||
rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
|
||||
h = omap34xx_hwmods;
|
||||
} else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
|
||||
h = am35xx_hwmods;
|
||||
} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
|
||||
rev == OMAP3630_REV_ES1_2) {
|
||||
h = omap36xx_hwmods;
|
||||
} else {
|
||||
WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
|
||||
return -EINVAL;
|
||||
};
|
||||
|
||||
r = omap_hwmod_register(h);
|
||||
if (!r)
|
||||
return r;
|
||||
|
||||
/*
|
||||
* Register hwmods specific to certain ES levels of a
|
||||
* particular family of silicon (e.g., 34xx ES1.0)
|
||||
*/
|
||||
h = NULL;
|
||||
if (rev == OMAP3430_REV_ES1_0) {
|
||||
h = omap3430es1_hwmods;
|
||||
} else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
|
||||
rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
|
||||
rev == OMAP3430_REV_ES3_1_2) {
|
||||
h = omap3430es2plus_hwmods;
|
||||
};
|
||||
|
||||
if (h)
|
||||
r = omap_hwmod_register(h);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
@ -29,6 +29,7 @@
|
||||
#include <plat/mcbsp.h>
|
||||
#include <plat/mmc.h>
|
||||
#include <plat/i2c.h>
|
||||
#include <plat/dmtimer.h>
|
||||
|
||||
#include "omap_hwmod_common_data.h"
|
||||
|
||||
@ -133,7 +134,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
|
||||
.slaves = omap44xx_dmm_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
|
||||
.mpu_irqs = omap44xx_dmm_irqs,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -189,7 +189,6 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_emif_fw_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -236,7 +235,6 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_l3_instr_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* l3_main_1 */
|
||||
@ -336,7 +334,6 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_l3_main_1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* l3_main_2 */
|
||||
@ -438,7 +435,6 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_l3_main_2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* l3_main_3 */
|
||||
@ -496,7 +492,6 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_l3_main_3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -559,7 +554,6 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_l4_abe_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* l4_cfg */
|
||||
@ -588,7 +582,6 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_l4_cfg_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* l4_per */
|
||||
@ -617,7 +610,6 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_l4_per_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* l4_wkup */
|
||||
@ -646,7 +638,6 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_l4_wkup_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -677,7 +668,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
|
||||
.clkdm_name = "mpuss_clkdm",
|
||||
.slaves = omap44xx_mpu_private_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -828,7 +818,6 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
|
||||
.masters = omap44xx_aess_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -856,7 +845,6 @@ static struct omap_hwmod omap44xx_bandgap_hwmod = {
|
||||
},
|
||||
.opt_clks = bandgap_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -917,7 +905,6 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_counter_32k_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -1005,7 +992,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
|
||||
.masters = omap44xx_dma_system_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -1098,7 +1084,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_dmic_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -1164,7 +1149,6 @@ static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
|
||||
.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
|
||||
},
|
||||
},
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_dsp_hwmod = {
|
||||
@ -1187,7 +1171,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
|
||||
.masters = omap44xx_dsp_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -1278,7 +1261,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
|
||||
.masters = omap44xx_dss_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -1381,7 +1363,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
|
||||
.opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
|
||||
.slaves = omap44xx_dss_dispc_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -1480,7 +1461,6 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
|
||||
.opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
|
||||
.slaves = omap44xx_dss_dsi1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* dss_dsi2 */
|
||||
@ -1558,7 +1538,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
|
||||
.opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
|
||||
.slaves = omap44xx_dss_dsi2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -1656,7 +1635,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
|
||||
.opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
|
||||
.slaves = omap44xx_dss_hdmi_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -1748,7 +1726,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
|
||||
.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
|
||||
.slaves = omap44xx_dss_rfbi_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -1817,7 +1794,6 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_dss_venc_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -1901,7 +1877,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.slaves = omap44xx_gpio1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* gpio2 */
|
||||
@ -1957,7 +1932,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.slaves = omap44xx_gpio2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* gpio3 */
|
||||
@ -2013,7 +1987,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.slaves = omap44xx_gpio3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* gpio4 */
|
||||
@ -2069,7 +2042,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.slaves = omap44xx_gpio4_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* gpio5 */
|
||||
@ -2125,7 +2097,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.slaves = omap44xx_gpio5_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* gpio6 */
|
||||
@ -2181,7 +2152,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
|
||||
.dev_attr = &gpio_dev_attr,
|
||||
.slaves = omap44xx_gpio6_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -2261,7 +2231,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
|
||||
.masters = omap44xx_hsi_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -2345,7 +2314,6 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
|
||||
.slaves = omap44xx_i2c1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
|
||||
.dev_attr = &i2c_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* i2c2 */
|
||||
@ -2402,7 +2370,6 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
|
||||
.slaves = omap44xx_i2c2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
|
||||
.dev_attr = &i2c_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* i2c3 */
|
||||
@ -2459,7 +2426,6 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
|
||||
.slaves = omap44xx_i2c3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
|
||||
.dev_attr = &i2c_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* i2c4 */
|
||||
@ -2516,7 +2482,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
|
||||
.slaves = omap44xx_i2c4_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
|
||||
.dev_attr = &i2c_dev_attr,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -2577,7 +2542,6 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
|
||||
.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
|
||||
},
|
||||
},
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* Pseudo hwmod for reset control purpose only */
|
||||
@ -2593,7 +2557,6 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
|
||||
.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
|
||||
},
|
||||
},
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_ipu_hwmod = {
|
||||
@ -2616,7 +2579,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
|
||||
.masters = omap44xx_ipu_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -2706,7 +2668,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
|
||||
.masters = omap44xx_iss_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -2781,7 +2742,6 @@ static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
|
||||
.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
|
||||
},
|
||||
},
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* Pseudo hwmod for reset control purpose only */
|
||||
@ -2797,7 +2757,6 @@ static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
|
||||
.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
|
||||
},
|
||||
},
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static struct omap_hwmod omap44xx_iva_hwmod = {
|
||||
@ -2820,7 +2779,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
|
||||
.masters = omap44xx_iva_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -2890,7 +2848,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_kbd_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -2956,7 +2913,6 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_mailbox_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -3051,7 +3007,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_mcbsp1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* mcbsp2 */
|
||||
@ -3127,7 +3082,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_mcbsp2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* mcbsp3 */
|
||||
@ -3203,7 +3157,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_mcbsp3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* mcbsp4 */
|
||||
@ -3258,7 +3211,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_mcbsp4_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -3353,7 +3305,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_mcpdm_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -3442,7 +3393,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
|
||||
.dev_attr = &mcspi1_dev_attr,
|
||||
.slaves = omap44xx_mcspi1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* mcspi2 */
|
||||
@ -3505,7 +3455,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
|
||||
.dev_attr = &mcspi2_dev_attr,
|
||||
.slaves = omap44xx_mcspi2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* mcspi3 */
|
||||
@ -3568,7 +3517,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
|
||||
.dev_attr = &mcspi3_dev_attr,
|
||||
.slaves = omap44xx_mcspi3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* mcspi4 */
|
||||
@ -3629,7 +3577,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
|
||||
.dev_attr = &mcspi4_dev_attr,
|
||||
.slaves = omap44xx_mcspi4_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -3718,7 +3665,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
|
||||
.masters = omap44xx_mmc1_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* mmc2 */
|
||||
@ -3779,7 +3725,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
|
||||
.masters = omap44xx_mmc2_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* mmc3 */
|
||||
@ -3834,7 +3779,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_mmc3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* mmc4 */
|
||||
@ -3890,7 +3834,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_mmc4_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* mmc5 */
|
||||
@ -3945,7 +3888,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_mmc5_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -3987,7 +3929,6 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
|
||||
},
|
||||
.masters = omap44xx_mpu_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -4063,7 +4004,6 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_smartreflex_core_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* smartreflex_iva */
|
||||
@ -4112,7 +4052,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_smartreflex_iva_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* smartreflex_mpu */
|
||||
@ -4161,7 +4100,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_smartreflex_mpu_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -4224,7 +4162,6 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_spinlock_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -4265,6 +4202,16 @@ static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
|
||||
.sysc = &omap44xx_timer_sysc,
|
||||
};
|
||||
|
||||
/* always-on timers dev attribute */
|
||||
static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
|
||||
.timer_capability = OMAP_TIMER_ALWON,
|
||||
};
|
||||
|
||||
/* pwm timers dev attribute */
|
||||
static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
|
||||
.timer_capability = OMAP_TIMER_HAS_PWM,
|
||||
};
|
||||
|
||||
/* timer1 */
|
||||
static struct omap_hwmod omap44xx_timer1_hwmod;
|
||||
static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
|
||||
@ -4308,9 +4255,9 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap44xx_timer1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* timer2 */
|
||||
@ -4356,9 +4303,9 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap44xx_timer2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* timer3 */
|
||||
@ -4404,9 +4351,9 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap44xx_timer3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* timer4 */
|
||||
@ -4452,9 +4399,9 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap44xx_timer4_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* timer5 */
|
||||
@ -4519,9 +4466,9 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap44xx_timer5_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* timer6 */
|
||||
@ -4587,9 +4534,9 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap44xx_timer6_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* timer7 */
|
||||
@ -4654,9 +4601,9 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.slaves = omap44xx_timer7_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* timer8 */
|
||||
@ -4721,9 +4668,9 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap44xx_timer8_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* timer9 */
|
||||
@ -4769,9 +4716,9 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap44xx_timer9_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* timer10 */
|
||||
@ -4817,9 +4764,9 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap44xx_timer10_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* timer11 */
|
||||
@ -4865,9 +4812,9 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
|
||||
.modulemode = MODULEMODE_SWCTRL,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.slaves = omap44xx_timer11_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -4944,7 +4891,6 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_uart1_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* uart2 */
|
||||
@ -4999,7 +4945,6 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_uart2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* uart3 */
|
||||
@ -5055,7 +5000,6 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_uart3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* uart4 */
|
||||
@ -5110,7 +5054,6 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_uart4_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -5195,7 +5138,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
|
||||
.masters = omap44xx_usb_otg_hs_masters,
|
||||
.masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/*
|
||||
@ -5266,7 +5208,6 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_wd_timer2_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
/* wd_timer3 */
|
||||
@ -5333,7 +5274,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
|
||||
},
|
||||
.slaves = omap44xx_wd_timer3_slaves,
|
||||
.slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
};
|
||||
|
||||
static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
|
||||
|
@ -1,25 +1,25 @@
|
||||
/*
|
||||
* OMAP4XXX L3 Interconnect error handling driver
|
||||
*
|
||||
* Copyright (C) 2011 Texas Corporation
|
||||
* Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
* Sricharan <r.sricharan@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
* OMAP4XXX L3 Interconnect error handling driver
|
||||
*
|
||||
* Copyright (C) 2011 Texas Corporation
|
||||
* Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
* Sricharan <r.sricharan@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_device.h>
|
||||
@ -55,12 +55,12 @@
|
||||
static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
|
||||
{
|
||||
|
||||
struct omap4_l3 *l3 = _l3;
|
||||
int inttype, i, j;
|
||||
struct omap4_l3 *l3 = _l3;
|
||||
int inttype, i, k;
|
||||
int err_src = 0;
|
||||
u32 std_err_main_addr, std_err_main, err_reg;
|
||||
u32 base, slave_addr, clear;
|
||||
char *source_name;
|
||||
u32 std_err_main, err_reg, clear, masterid;
|
||||
void __iomem *base, *l3_targ_base;
|
||||
char *target_name, *master_name = "UN IDENTIFIED";
|
||||
|
||||
/* Get the Type of interrupt */
|
||||
inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
|
||||
@ -70,43 +70,50 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
|
||||
* Read the regerr register of the clock domain
|
||||
* to determine the source
|
||||
*/
|
||||
base = (u32)l3->l3_base[i];
|
||||
err_reg = readl(base + l3_flagmux[i] + (inttype << 3));
|
||||
base = l3->l3_base[i];
|
||||
err_reg = __raw_readl(base + l3_flagmux[i] +
|
||||
+ L3_FLAGMUX_REGERR0 + (inttype << 3));
|
||||
|
||||
/* Get the corresponding error and analyse */
|
||||
if (err_reg) {
|
||||
/* Identify the source from control status register */
|
||||
for (j = 0; !(err_reg & (1 << j)); j++)
|
||||
;
|
||||
err_src = __ffs(err_reg);
|
||||
|
||||
err_src = j;
|
||||
/* Read the stderrlog_main_source from clk domain */
|
||||
std_err_main_addr = base + *(l3_targ[i] + err_src);
|
||||
std_err_main = readl(std_err_main_addr);
|
||||
l3_targ_base = base + *(l3_targ[i] + err_src);
|
||||
std_err_main = __raw_readl(l3_targ_base +
|
||||
L3_TARG_STDERRLOG_MAIN);
|
||||
masterid = __raw_readl(l3_targ_base +
|
||||
L3_TARG_STDERRLOG_MSTADDR);
|
||||
|
||||
switch (std_err_main & CUSTOM_ERROR) {
|
||||
case STANDARD_ERROR:
|
||||
source_name =
|
||||
l3_targ_stderrlog_main_name[i][err_src];
|
||||
|
||||
slave_addr = std_err_main_addr +
|
||||
L3_SLAVE_ADDRESS_OFFSET;
|
||||
WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n",
|
||||
source_name, readl(slave_addr));
|
||||
target_name =
|
||||
l3_targ_inst_name[i][err_src];
|
||||
WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
|
||||
target_name,
|
||||
__raw_readl(l3_targ_base +
|
||||
L3_TARG_STDERRLOG_SLVOFSLSB));
|
||||
/* clear the std error log*/
|
||||
clear = std_err_main | CLEAR_STDERR_LOG;
|
||||
writel(clear, std_err_main_addr);
|
||||
writel(clear, l3_targ_base +
|
||||
L3_TARG_STDERRLOG_MAIN);
|
||||
break;
|
||||
|
||||
case CUSTOM_ERROR:
|
||||
source_name =
|
||||
l3_targ_stderrlog_main_name[i][err_src];
|
||||
|
||||
WARN(true, "CUSTOM SRESP error with SOURCE:%s\n",
|
||||
source_name);
|
||||
target_name =
|
||||
l3_targ_inst_name[i][err_src];
|
||||
for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
|
||||
if (masterid == l3_masters[k].id)
|
||||
master_name =
|
||||
l3_masters[k].name;
|
||||
}
|
||||
WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
|
||||
master_name, target_name);
|
||||
/* clear the std error log*/
|
||||
clear = std_err_main | CLEAR_STDERR_LOG;
|
||||
writel(clear, std_err_main_addr);
|
||||
writel(clear, l3_targ_base +
|
||||
L3_TARG_STDERRLOG_MAIN);
|
||||
break;
|
||||
|
||||
default:
|
||||
@ -120,12 +127,11 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int __init omap4_l3_probe(struct platform_device *pdev)
|
||||
static int __devinit omap4_l3_probe(struct platform_device *pdev)
|
||||
{
|
||||
static struct omap4_l3 *l3;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
int irq;
|
||||
static struct omap4_l3 *l3;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
|
||||
if (!l3)
|
||||
@ -177,27 +183,25 @@ static int __init omap4_l3_probe(struct platform_device *pdev)
|
||||
/*
|
||||
* Setup interrupt Handlers
|
||||
*/
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
ret = request_irq(irq,
|
||||
l3->debug_irq = platform_get_irq(pdev, 0);
|
||||
ret = request_irq(l3->debug_irq,
|
||||
l3_interrupt_handler,
|
||||
IRQF_DISABLED, "l3-dbg-irq", l3);
|
||||
if (ret) {
|
||||
pr_crit("L3: request_irq failed to register for 0x%x\n",
|
||||
OMAP44XX_IRQ_L3_DBG);
|
||||
OMAP44XX_IRQ_L3_DBG);
|
||||
goto err3;
|
||||
}
|
||||
l3->debug_irq = irq;
|
||||
|
||||
irq = platform_get_irq(pdev, 1);
|
||||
ret = request_irq(irq,
|
||||
l3->app_irq = platform_get_irq(pdev, 1);
|
||||
ret = request_irq(l3->app_irq,
|
||||
l3_interrupt_handler,
|
||||
IRQF_DISABLED, "l3-app-irq", l3);
|
||||
if (ret) {
|
||||
pr_crit("L3: request_irq failed to register for 0x%x\n",
|
||||
OMAP44XX_IRQ_L3_APP);
|
||||
OMAP44XX_IRQ_L3_APP);
|
||||
goto err4;
|
||||
}
|
||||
l3->app_irq = irq;
|
||||
|
||||
return 0;
|
||||
|
||||
@ -214,9 +218,9 @@ static int __init omap4_l3_probe(struct platform_device *pdev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __exit omap4_l3_remove(struct platform_device *pdev)
|
||||
static int __devexit omap4_l3_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct omap4_l3 *l3 = platform_get_drvdata(pdev);
|
||||
struct omap4_l3 *l3 = platform_get_drvdata(pdev);
|
||||
|
||||
free_irq(l3->app_irq, l3);
|
||||
free_irq(l3->debug_irq, l3);
|
||||
@ -228,16 +232,29 @@ static int __exit omap4_l3_remove(struct platform_device *pdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF)
|
||||
static const struct of_device_id l3_noc_match[] = {
|
||||
{.compatible = "ti,omap4-l3-noc", },
|
||||
{},
|
||||
}
|
||||
MODULE_DEVICE_TABLE(of, l3_noc_match);
|
||||
#else
|
||||
#define l3_noc_match NULL
|
||||
#endif
|
||||
|
||||
static struct platform_driver omap4_l3_driver = {
|
||||
.remove = __exit_p(omap4_l3_remove),
|
||||
.probe = omap4_l3_probe,
|
||||
.remove = __devexit_p(omap4_l3_remove),
|
||||
.driver = {
|
||||
.name = "omap_l3_noc",
|
||||
.name = "omap_l3_noc",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = l3_noc_match,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init omap4_l3_init(void)
|
||||
{
|
||||
return platform_driver_probe(&omap4_l3_driver, omap4_l3_probe);
|
||||
return platform_driver_register(&omap4_l3_driver);
|
||||
}
|
||||
postcore_initcall_sync(omap4_l3_init);
|
||||
|
||||
|
@ -1,132 +1,162 @@
|
||||
/*
|
||||
* OMAP4XXX L3 Interconnect error handling driver header
|
||||
*
|
||||
* Copyright (C) 2011 Texas Corporation
|
||||
* Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
* sricharan <r.sricharan@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
/*
|
||||
* OMAP4XXX L3 Interconnect error handling driver header
|
||||
*
|
||||
* Copyright (C) 2011 Texas Corporation
|
||||
* Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
* sricharan <r.sricharan@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
|
||||
|
||||
/*
|
||||
* L3 register offsets
|
||||
*/
|
||||
#define L3_MODULES 3
|
||||
#define CLEAR_STDERR_LOG (1 << 31)
|
||||
#define CUSTOM_ERROR 0x2
|
||||
#define STANDARD_ERROR 0x0
|
||||
#define INBAND_ERROR 0x0
|
||||
#define EMIF_KERRLOG_OFFSET 0x10
|
||||
#define L3_SLAVE_ADDRESS_OFFSET 0x14
|
||||
#define LOGICAL_ADDR_ERRORLOG 0x4
|
||||
#define L3_APPLICATION_ERROR 0x0
|
||||
#define L3_DEBUG_ERROR 0x1
|
||||
|
||||
u32 l3_flagmux[L3_MODULES] = {
|
||||
0x50C,
|
||||
0x100C,
|
||||
0X020C
|
||||
/* L3 TARG register offsets */
|
||||
#define L3_TARG_STDERRLOG_MAIN 0x48
|
||||
#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
|
||||
#define L3_TARG_STDERRLOG_MSTADDR 0x68
|
||||
#define L3_FLAGMUX_REGERR0 0xc
|
||||
|
||||
#define NUM_OF_L3_MASTERS (sizeof(l3_masters)/sizeof(l3_masters[0]))
|
||||
|
||||
static u32 l3_flagmux[L3_MODULES] = {
|
||||
0x500,
|
||||
0x1000,
|
||||
0X0200
|
||||
};
|
||||
|
||||
/*
|
||||
* L3 Target standard Error register offsets
|
||||
*/
|
||||
u32 l3_targ_stderrlog_main_clk1[] = {
|
||||
0x148, /* DMM1 */
|
||||
0x248, /* DMM2 */
|
||||
0x348, /* ABE */
|
||||
0x448, /* L4CFG */
|
||||
0x648 /* CLK2 PWR DISC */
|
||||
/* L3 Target standard Error register offsets */
|
||||
static u32 l3_targ_inst_clk1[] = {
|
||||
0x100, /* DMM1 */
|
||||
0x200, /* DMM2 */
|
||||
0x300, /* ABE */
|
||||
0x400, /* L4CFG */
|
||||
0x600 /* CLK2 PWR DISC */
|
||||
};
|
||||
|
||||
u32 l3_targ_stderrlog_main_clk2[] = {
|
||||
0x548, /* CORTEX M3 */
|
||||
0x348, /* DSS */
|
||||
0x148, /* GPMC */
|
||||
0x448, /* ISS */
|
||||
0x748, /* IVAHD */
|
||||
0xD48, /* missing in TRM corresponds to AES1*/
|
||||
0x948, /* L4 PER0*/
|
||||
0x248, /* OCMRAM */
|
||||
0x148, /* missing in TRM corresponds to GPMC sERROR*/
|
||||
0x648, /* SGX */
|
||||
0x848, /* SL2 */
|
||||
0x1648, /* C2C */
|
||||
0x1148, /* missing in TRM corresponds PWR DISC CLK1*/
|
||||
0xF48, /* missing in TRM corrsponds to SHA1*/
|
||||
0xE48, /* missing in TRM corresponds to AES2*/
|
||||
0xC48, /* L4 PER3 */
|
||||
0xA48, /* L4 PER1*/
|
||||
0xB48 /* L4 PER2*/
|
||||
static u32 l3_targ_inst_clk2[] = {
|
||||
0x500, /* CORTEX M3 */
|
||||
0x300, /* DSS */
|
||||
0x100, /* GPMC */
|
||||
0x400, /* ISS */
|
||||
0x700, /* IVAHD */
|
||||
0xD00, /* missing in TRM corresponds to AES1*/
|
||||
0x900, /* L4 PER0*/
|
||||
0x200, /* OCMRAM */
|
||||
0x100, /* missing in TRM corresponds to GPMC sERROR*/
|
||||
0x600, /* SGX */
|
||||
0x800, /* SL2 */
|
||||
0x1600, /* C2C */
|
||||
0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
|
||||
0xF00, /* missing in TRM corrsponds to SHA1*/
|
||||
0xE00, /* missing in TRM corresponds to AES2*/
|
||||
0xC00, /* L4 PER3 */
|
||||
0xA00, /* L4 PER1*/
|
||||
0xB00 /* L4 PER2*/
|
||||
};
|
||||
|
||||
u32 l3_targ_stderrlog_main_clk3[] = {
|
||||
0x0148 /* EMUSS */
|
||||
static u32 l3_targ_inst_clk3[] = {
|
||||
0x0100 /* EMUSS */
|
||||
};
|
||||
|
||||
char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
|
||||
static struct l3_masters_data {
|
||||
u32 id;
|
||||
char name[10];
|
||||
} l3_masters[] = {
|
||||
{ 0x0 , "MPU"},
|
||||
{ 0x10, "CS_ADP"},
|
||||
{ 0x14, "xxx"},
|
||||
{ 0x20, "DSP"},
|
||||
{ 0x30, "IVAHD"},
|
||||
{ 0x40, "ISS"},
|
||||
{ 0x44, "DucatiM3"},
|
||||
{ 0x48, "FaceDetect"},
|
||||
{ 0x50, "SDMA_Rd"},
|
||||
{ 0x54, "SDMA_Wr"},
|
||||
{ 0x58, "xxx"},
|
||||
{ 0x5C, "xxx"},
|
||||
{ 0x60, "SGX"},
|
||||
{ 0x70, "DSS"},
|
||||
{ 0x80, "C2C"},
|
||||
{ 0x88, "xxx"},
|
||||
{ 0x8C, "xxx"},
|
||||
{ 0x90, "HSI"},
|
||||
{ 0xA0, "MMC1"},
|
||||
{ 0xA4, "MMC2"},
|
||||
{ 0xA8, "MMC6"},
|
||||
{ 0xB0, "UNIPRO1"},
|
||||
{ 0xC0, "USBHOSTHS"},
|
||||
{ 0xC4, "USBOTGHS"},
|
||||
{ 0xC8, "USBHOSTFS"}
|
||||
};
|
||||
|
||||
static char *l3_targ_inst_name[L3_MODULES][18] = {
|
||||
{
|
||||
"DMM1",
|
||||
"DMM2",
|
||||
"ABE",
|
||||
"L4CFG",
|
||||
"CLK2 PWR DISC",
|
||||
"DMM1",
|
||||
"DMM2",
|
||||
"ABE",
|
||||
"L4CFG",
|
||||
"CLK2 PWR DISC",
|
||||
},
|
||||
{
|
||||
"CORTEX M3" ,
|
||||
"DSS ",
|
||||
"GPMC ",
|
||||
"ISS ",
|
||||
"IVAHD ",
|
||||
"AES1",
|
||||
"L4 PER0",
|
||||
"OCMRAM ",
|
||||
"GPMC sERROR",
|
||||
"SGX ",
|
||||
"SL2 ",
|
||||
"C2C ",
|
||||
"PWR DISC CLK1",
|
||||
"SHA1",
|
||||
"AES2",
|
||||
"L4 PER3",
|
||||
"L4 PER1",
|
||||
"L4 PER2",
|
||||
"CORTEX M3" ,
|
||||
"DSS ",
|
||||
"GPMC ",
|
||||
"ISS ",
|
||||
"IVAHD ",
|
||||
"AES1",
|
||||
"L4 PER0",
|
||||
"OCMRAM ",
|
||||
"GPMC sERROR",
|
||||
"SGX ",
|
||||
"SL2 ",
|
||||
"C2C ",
|
||||
"PWR DISC CLK1",
|
||||
"SHA1",
|
||||
"AES2",
|
||||
"L4 PER3",
|
||||
"L4 PER1",
|
||||
"L4 PER2",
|
||||
},
|
||||
{
|
||||
"EMUSS",
|
||||
"EMUSS",
|
||||
},
|
||||
};
|
||||
|
||||
u32 *l3_targ[L3_MODULES] = {
|
||||
l3_targ_stderrlog_main_clk1,
|
||||
l3_targ_stderrlog_main_clk2,
|
||||
l3_targ_stderrlog_main_clk3,
|
||||
static u32 *l3_targ[L3_MODULES] = {
|
||||
l3_targ_inst_clk1,
|
||||
l3_targ_inst_clk2,
|
||||
l3_targ_inst_clk3,
|
||||
};
|
||||
|
||||
struct omap4_l3 {
|
||||
struct device *dev;
|
||||
struct clk *ick;
|
||||
struct device *dev;
|
||||
struct clk *ick;
|
||||
|
||||
/* memory base */
|
||||
void __iomem *l3_base[4];
|
||||
void __iomem *l3_base[L3_MODULES];
|
||||
|
||||
int debug_irq;
|
||||
int app_irq;
|
||||
int debug_irq;
|
||||
int app_irq;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
@ -1,26 +1,26 @@
|
||||
/*
|
||||
* OMAP3XXX L3 Interconnect Driver
|
||||
*
|
||||
* Copyright (C) 2011 Texas Corporation
|
||||
* Felipe Balbi <balbi@ti.com>
|
||||
* Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
* Sricharan <r.sricharan@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
/*
|
||||
* OMAP3XXX L3 Interconnect Driver
|
||||
*
|
||||
* Copyright (C) 2011 Texas Corporation
|
||||
* Felipe Balbi <balbi@ti.com>
|
||||
* Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
* Sricharan <r.sricharan@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/slab.h>
|
||||
@ -135,7 +135,7 @@ static char *omap3_l3_initiator_string(u8 initid)
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
/*
|
||||
* omap3_l3_block_irq - handles a register block's irq
|
||||
* @l3: struct omap3_l3 *
|
||||
* @base: register block base address
|
||||
@ -150,30 +150,29 @@ static char *omap3_l3_initiator_string(u8 initid)
|
||||
static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
|
||||
u64 error, int error_addr)
|
||||
{
|
||||
u8 code = omap3_l3_decode_error_code(error);
|
||||
u8 initid = omap3_l3_decode_initid(error);
|
||||
u8 multi = error & L3_ERROR_LOG_MULTI;
|
||||
u32 address = omap3_l3_decode_addr(error_addr);
|
||||
u8 code = omap3_l3_decode_error_code(error);
|
||||
u8 initid = omap3_l3_decode_initid(error);
|
||||
u8 multi = error & L3_ERROR_LOG_MULTI;
|
||||
u32 address = omap3_l3_decode_addr(error_addr);
|
||||
|
||||
WARN(true, "%s seen by %s %s at address %x\n",
|
||||
omap3_l3_code_string(code),
|
||||
omap3_l3_initiator_string(initid),
|
||||
multi ? "Multiple Errors" : "",
|
||||
address);
|
||||
omap3_l3_code_string(code),
|
||||
omap3_l3_initiator_string(initid),
|
||||
multi ? "Multiple Errors" : "", address);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
|
||||
{
|
||||
struct omap3_l3 *l3 = _l3;
|
||||
u64 status, clear;
|
||||
u64 error;
|
||||
u64 error_addr;
|
||||
u64 err_source = 0;
|
||||
void __iomem *base;
|
||||
int int_type;
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
struct omap3_l3 *l3 = _l3;
|
||||
u64 status, clear;
|
||||
u64 error;
|
||||
u64 error_addr;
|
||||
u64 err_source = 0;
|
||||
void __iomem *base;
|
||||
int int_type;
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
|
||||
int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
|
||||
if (!int_type) {
|
||||
@ -191,14 +190,12 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
|
||||
}
|
||||
|
||||
/* identify the error source */
|
||||
for (err_source = 0; !(status & (1 << err_source)); err_source++)
|
||||
;
|
||||
err_source = __ffs(status);
|
||||
|
||||
base = l3->rt + *(omap3_l3_bases[int_type] + err_source);
|
||||
base = l3->rt + omap3_l3_bases[int_type][err_source];
|
||||
error = omap3_l3_readll(base, L3_ERROR_LOG);
|
||||
if (error) {
|
||||
error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
|
||||
|
||||
ret |= omap3_l3_block_irq(l3, error, error_addr);
|
||||
}
|
||||
|
||||
@ -215,9 +212,9 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
|
||||
|
||||
static int __init omap3_l3_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct omap3_l3 *l3;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
struct omap3_l3 *l3;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
|
||||
if (!l3)
|
||||
|
@ -1,26 +1,26 @@
|
||||
/*
|
||||
* OMAP3XXX L3 Interconnect Driver header
|
||||
*
|
||||
* Copyright (C) 2011 Texas Corporation
|
||||
* Felipe Balbi <balbi@ti.com>
|
||||
* Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
* sricharan <r.sricharan@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
/*
|
||||
* OMAP3XXX L3 Interconnect Driver header
|
||||
*
|
||||
* Copyright (C) 2011 Texas Corporation
|
||||
* Felipe Balbi <balbi@ti.com>
|
||||
* Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
* sricharan <r.sricharan@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
|
||||
* USA
|
||||
*/
|
||||
#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
|
||||
#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
|
||||
|
||||
@ -40,7 +40,7 @@
|
||||
#define L3_SI_CONTROL 0x020
|
||||
#define L3_SI_FLAG_STATUS_0 0x510
|
||||
|
||||
const u64 shift = 1;
|
||||
static const u64 shift = 1;
|
||||
|
||||
#define L3_STATUS_0_MPUIA_BRST (shift << 0)
|
||||
#define L3_STATUS_0_MPUIA_RSP (shift << 1)
|
||||
@ -78,32 +78,32 @@ const u64 shift = 1;
|
||||
#define L3_STATUS_0_L4EMUTA_REQ (shift << 60)
|
||||
#define L3_STATUS_0_MAD2DTA_REQ (shift << 61)
|
||||
|
||||
#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \
|
||||
| L3_STATUS_0_MPUIA_RSP \
|
||||
| L3_STATUS_0_IVAIA_BRST \
|
||||
| L3_STATUS_0_IVAIA_RSP \
|
||||
| L3_STATUS_0_SGXIA_BRST \
|
||||
| L3_STATUS_0_SGXIA_RSP \
|
||||
| L3_STATUS_0_CAMIA_BRST \
|
||||
| L3_STATUS_0_CAMIA_RSP \
|
||||
| L3_STATUS_0_DISPIA_BRST \
|
||||
| L3_STATUS_0_DISPIA_RSP \
|
||||
| L3_STATUS_0_DMARDIA_BRST \
|
||||
| L3_STATUS_0_DMARDIA_RSP \
|
||||
| L3_STATUS_0_DMAWRIA_BRST \
|
||||
| L3_STATUS_0_DMAWRIA_RSP \
|
||||
| L3_STATUS_0_USBOTGIA_BRST \
|
||||
| L3_STATUS_0_USBOTGIA_RSP \
|
||||
| L3_STATUS_0_USBHOSTIA_BRST \
|
||||
| L3_STATUS_0_SMSTA_REQ \
|
||||
| L3_STATUS_0_GPMCTA_REQ \
|
||||
| L3_STATUS_0_OCMRAMTA_REQ \
|
||||
| L3_STATUS_0_OCMROMTA_REQ \
|
||||
| L3_STATUS_0_IVATA_REQ \
|
||||
| L3_STATUS_0_SGXTA_REQ \
|
||||
| L3_STATUS_0_L4CORETA_REQ \
|
||||
| L3_STATUS_0_L4PERTA_REQ \
|
||||
| L3_STATUS_0_L4EMUTA_REQ \
|
||||
#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \
|
||||
| L3_STATUS_0_MPUIA_RSP \
|
||||
| L3_STATUS_0_IVAIA_BRST \
|
||||
| L3_STATUS_0_IVAIA_RSP \
|
||||
| L3_STATUS_0_SGXIA_BRST \
|
||||
| L3_STATUS_0_SGXIA_RSP \
|
||||
| L3_STATUS_0_CAMIA_BRST \
|
||||
| L3_STATUS_0_CAMIA_RSP \
|
||||
| L3_STATUS_0_DISPIA_BRST \
|
||||
| L3_STATUS_0_DISPIA_RSP \
|
||||
| L3_STATUS_0_DMARDIA_BRST \
|
||||
| L3_STATUS_0_DMARDIA_RSP \
|
||||
| L3_STATUS_0_DMAWRIA_BRST \
|
||||
| L3_STATUS_0_DMAWRIA_RSP \
|
||||
| L3_STATUS_0_USBOTGIA_BRST \
|
||||
| L3_STATUS_0_USBOTGIA_RSP \
|
||||
| L3_STATUS_0_USBHOSTIA_BRST \
|
||||
| L3_STATUS_0_SMSTA_REQ \
|
||||
| L3_STATUS_0_GPMCTA_REQ \
|
||||
| L3_STATUS_0_OCMRAMTA_REQ \
|
||||
| L3_STATUS_0_OCMROMTA_REQ \
|
||||
| L3_STATUS_0_IVATA_REQ \
|
||||
| L3_STATUS_0_SGXTA_REQ \
|
||||
| L3_STATUS_0_L4CORETA_REQ \
|
||||
| L3_STATUS_0_L4PERTA_REQ \
|
||||
| L3_STATUS_0_L4EMUTA_REQ \
|
||||
| L3_STATUS_0_MAD2DTA_REQ)
|
||||
|
||||
#define L3_SI_FLAG_STATUS_1 0x530
|
||||
@ -137,19 +137,19 @@ const u64 shift = 1;
|
||||
|
||||
enum omap3_l3_initiator_id {
|
||||
/* LCD has 1 ID */
|
||||
OMAP_L3_LCD = 29,
|
||||
OMAP_L3_LCD = 29,
|
||||
/* SAD2D has 1 ID */
|
||||
OMAP_L3_SAD2D = 28,
|
||||
OMAP_L3_SAD2D = 28,
|
||||
/* MPU has 5 IDs */
|
||||
OMAP_L3_IA_MPU_SS_1 = 27,
|
||||
OMAP_L3_IA_MPU_SS_2 = 26,
|
||||
OMAP_L3_IA_MPU_SS_3 = 25,
|
||||
OMAP_L3_IA_MPU_SS_4 = 24,
|
||||
OMAP_L3_IA_MPU_SS_5 = 23,
|
||||
OMAP_L3_IA_MPU_SS_1 = 27,
|
||||
OMAP_L3_IA_MPU_SS_2 = 26,
|
||||
OMAP_L3_IA_MPU_SS_3 = 25,
|
||||
OMAP_L3_IA_MPU_SS_4 = 24,
|
||||
OMAP_L3_IA_MPU_SS_5 = 23,
|
||||
/* IVA2.2 SS has 3 IDs*/
|
||||
OMAP_L3_IA_IVA_SS_1 = 22,
|
||||
OMAP_L3_IA_IVA_SS_2 = 21,
|
||||
OMAP_L3_IA_IVA_SS_3 = 20,
|
||||
OMAP_L3_IA_IVA_SS_1 = 22,
|
||||
OMAP_L3_IA_IVA_SS_2 = 21,
|
||||
OMAP_L3_IA_IVA_SS_3 = 20,
|
||||
/* IVA 2.2 SS DMA has 6 IDS */
|
||||
OMAP_L3_IA_IVA_SS_DMA_1 = 19,
|
||||
OMAP_L3_IA_IVA_SS_DMA_2 = 18,
|
||||
@ -158,25 +158,25 @@ enum omap3_l3_initiator_id {
|
||||
OMAP_L3_IA_IVA_SS_DMA_5 = 15,
|
||||
OMAP_L3_IA_IVA_SS_DMA_6 = 14,
|
||||
/* SGX has 1 ID */
|
||||
OMAP_L3_IA_SGX = 13,
|
||||
OMAP_L3_IA_SGX = 13,
|
||||
/* CAM has 3 ID */
|
||||
OMAP_L3_IA_CAM_1 = 12,
|
||||
OMAP_L3_IA_CAM_2 = 11,
|
||||
OMAP_L3_IA_CAM_3 = 10,
|
||||
OMAP_L3_IA_CAM_1 = 12,
|
||||
OMAP_L3_IA_CAM_2 = 11,
|
||||
OMAP_L3_IA_CAM_3 = 10,
|
||||
/* DAP has 1 ID */
|
||||
OMAP_L3_IA_DAP = 9,
|
||||
OMAP_L3_IA_DAP = 9,
|
||||
/* SDMA WR has 2 IDs */
|
||||
OMAP_L3_SDMA_WR_1 = 8,
|
||||
OMAP_L3_SDMA_WR_2 = 7,
|
||||
OMAP_L3_SDMA_WR_1 = 8,
|
||||
OMAP_L3_SDMA_WR_2 = 7,
|
||||
/* SDMA RD has 4 IDs */
|
||||
OMAP_L3_SDMA_RD_1 = 6,
|
||||
OMAP_L3_SDMA_RD_2 = 5,
|
||||
OMAP_L3_SDMA_RD_3 = 4,
|
||||
OMAP_L3_SDMA_RD_4 = 3,
|
||||
OMAP_L3_SDMA_RD_1 = 6,
|
||||
OMAP_L3_SDMA_RD_2 = 5,
|
||||
OMAP_L3_SDMA_RD_3 = 4,
|
||||
OMAP_L3_SDMA_RD_4 = 3,
|
||||
/* HSUSB OTG has 1 ID */
|
||||
OMAP_L3_USBOTG = 2,
|
||||
OMAP_L3_USBOTG = 2,
|
||||
/* HSUSB HOST has 1 ID */
|
||||
OMAP_L3_USBHOST = 1,
|
||||
OMAP_L3_USBHOST = 1,
|
||||
};
|
||||
|
||||
enum omap3_l3_code {
|
||||
@ -192,21 +192,21 @@ enum omap3_l3_code {
|
||||
};
|
||||
|
||||
struct omap3_l3 {
|
||||
struct device *dev;
|
||||
struct clk *ick;
|
||||
struct device *dev;
|
||||
struct clk *ick;
|
||||
|
||||
/* memory base*/
|
||||
void __iomem *rt;
|
||||
void __iomem *rt;
|
||||
|
||||
int debug_irq;
|
||||
int app_irq;
|
||||
int debug_irq;
|
||||
int app_irq;
|
||||
|
||||
/* true when and inband functional error occurs */
|
||||
unsigned inband:1;
|
||||
unsigned inband:1;
|
||||
};
|
||||
|
||||
/* offsets for l3 agents in order with the Flag status register */
|
||||
unsigned int __iomem omap3_l3_app_bases[] = {
|
||||
static unsigned int omap3_l3_app_bases[] = {
|
||||
/* MPU IA */
|
||||
0x1400,
|
||||
0x1400,
|
||||
@ -305,7 +305,7 @@ unsigned int __iomem omap3_l3_app_bases[] = {
|
||||
0,
|
||||
};
|
||||
|
||||
unsigned int __iomem omap3_l3_debug_bases[] = {
|
||||
static unsigned int omap3_l3_debug_bases[] = {
|
||||
/* MPU DATA IA */
|
||||
0x1400,
|
||||
/* RESERVED */
|
||||
@ -321,7 +321,7 @@ unsigned int __iomem omap3_l3_debug_bases[] = {
|
||||
/* REST RESERVED */
|
||||
};
|
||||
|
||||
u32 *omap3_l3_bases[] = {
|
||||
static u32 *omap3_l3_bases[] = {
|
||||
omap3_l3_app_bases,
|
||||
omap3_l3_debug_bases,
|
||||
};
|
||||
|
@ -42,8 +42,11 @@
|
||||
|
||||
#define OMAP4_SRI2C_SLAVE_ADDR 0x12
|
||||
#define OMAP4_VDD_MPU_SR_VOLT_REG 0x55
|
||||
#define OMAP4_VDD_MPU_SR_CMD_REG 0x56
|
||||
#define OMAP4_VDD_IVA_SR_VOLT_REG 0x5B
|
||||
#define OMAP4_VDD_IVA_SR_CMD_REG 0x5C
|
||||
#define OMAP4_VDD_CORE_SR_VOLT_REG 0x61
|
||||
#define OMAP4_VDD_CORE_SR_CMD_REG 0x62
|
||||
|
||||
#define OMAP4_VP_CONFIG_ERROROFFSET 0x00
|
||||
#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
|
||||
@ -95,6 +98,8 @@ static unsigned long twl6030_vsel_to_uv(const u8 vsel)
|
||||
is_offset_valid = true;
|
||||
}
|
||||
|
||||
if (!vsel)
|
||||
return 0;
|
||||
/*
|
||||
* There is no specific formula for voltage to vsel
|
||||
* conversion above 1.3V. There are special hardcoded
|
||||
@ -106,9 +111,9 @@ static unsigned long twl6030_vsel_to_uv(const u8 vsel)
|
||||
return 1350000;
|
||||
|
||||
if (smps_offset & 0x8)
|
||||
return ((((vsel - 1) * 125) + 7000)) * 100;
|
||||
return ((((vsel - 1) * 1266) + 70900)) * 10;
|
||||
else
|
||||
return ((((vsel - 1) * 125) + 6000)) * 100;
|
||||
return ((((vsel - 1) * 1266) + 60770)) * 10;
|
||||
}
|
||||
|
||||
static u8 twl6030_uv_to_vsel(unsigned long uv)
|
||||
@ -127,6 +132,8 @@ static u8 twl6030_uv_to_vsel(unsigned long uv)
|
||||
is_offset_valid = true;
|
||||
}
|
||||
|
||||
if (!uv)
|
||||
return 0x00;
|
||||
/*
|
||||
* There is no specific formula for voltage to vsel
|
||||
* conversion above 1.3V. There are special hardcoded
|
||||
@ -134,16 +141,21 @@ static u8 twl6030_uv_to_vsel(unsigned long uv)
|
||||
* hardcoding only for 1.35 V which is used for 1GH OPP for
|
||||
* OMAP4430.
|
||||
*/
|
||||
if (uv == 1350000)
|
||||
if (uv > twl6030_vsel_to_uv(0x39)) {
|
||||
if (uv == 1350000)
|
||||
return 0x3A;
|
||||
pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
|
||||
__func__, uv, twl6030_vsel_to_uv(0x39));
|
||||
return 0x3A;
|
||||
}
|
||||
|
||||
if (smps_offset & 0x8)
|
||||
return DIV_ROUND_UP(uv - 700000, 12500) + 1;
|
||||
return DIV_ROUND_UP(uv - 709000, 12660) + 1;
|
||||
else
|
||||
return DIV_ROUND_UP(uv - 600000, 12500) + 1;
|
||||
return DIV_ROUND_UP(uv - 607700, 12660) + 1;
|
||||
}
|
||||
|
||||
static struct omap_volt_pmic_info omap3_mpu_volt_info = {
|
||||
static struct omap_voltdm_pmic omap3_mpu_pmic = {
|
||||
.slew_rate = 4000,
|
||||
.step_size = 12500,
|
||||
.on_volt = 1200000,
|
||||
@ -158,12 +170,13 @@ static struct omap_volt_pmic_info omap3_mpu_volt_info = {
|
||||
.vp_vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX,
|
||||
.vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
|
||||
.i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
|
||||
.pmic_reg = OMAP3_VDD_MPU_SR_CONTROL_REG,
|
||||
.volt_reg_addr = OMAP3_VDD_MPU_SR_CONTROL_REG,
|
||||
.i2c_high_speed = true,
|
||||
.vsel_to_uv = twl4030_vsel_to_uv,
|
||||
.uv_to_vsel = twl4030_uv_to_vsel,
|
||||
};
|
||||
|
||||
static struct omap_volt_pmic_info omap3_core_volt_info = {
|
||||
static struct omap_voltdm_pmic omap3_core_pmic = {
|
||||
.slew_rate = 4000,
|
||||
.step_size = 12500,
|
||||
.on_volt = 1200000,
|
||||
@ -178,18 +191,19 @@ static struct omap_volt_pmic_info omap3_core_volt_info = {
|
||||
.vp_vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX,
|
||||
.vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
|
||||
.i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
|
||||
.pmic_reg = OMAP3_VDD_CORE_SR_CONTROL_REG,
|
||||
.volt_reg_addr = OMAP3_VDD_CORE_SR_CONTROL_REG,
|
||||
.i2c_high_speed = true,
|
||||
.vsel_to_uv = twl4030_vsel_to_uv,
|
||||
.uv_to_vsel = twl4030_uv_to_vsel,
|
||||
};
|
||||
|
||||
static struct omap_volt_pmic_info omap4_mpu_volt_info = {
|
||||
static struct omap_voltdm_pmic omap4_mpu_pmic = {
|
||||
.slew_rate = 4000,
|
||||
.step_size = 12500,
|
||||
.on_volt = 1350000,
|
||||
.onlp_volt = 1350000,
|
||||
.ret_volt = 837500,
|
||||
.off_volt = 600000,
|
||||
.step_size = 12660,
|
||||
.on_volt = 1375000,
|
||||
.onlp_volt = 1375000,
|
||||
.ret_volt = 830000,
|
||||
.off_volt = 0,
|
||||
.volt_setup_time = 0,
|
||||
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
|
||||
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
|
||||
@ -198,18 +212,20 @@ static struct omap_volt_pmic_info omap4_mpu_volt_info = {
|
||||
.vp_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
|
||||
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
|
||||
.i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
|
||||
.pmic_reg = OMAP4_VDD_MPU_SR_VOLT_REG,
|
||||
.volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG,
|
||||
.cmd_reg_addr = OMAP4_VDD_MPU_SR_CMD_REG,
|
||||
.i2c_high_speed = true,
|
||||
.vsel_to_uv = twl6030_vsel_to_uv,
|
||||
.uv_to_vsel = twl6030_uv_to_vsel,
|
||||
};
|
||||
|
||||
static struct omap_volt_pmic_info omap4_iva_volt_info = {
|
||||
static struct omap_voltdm_pmic omap4_iva_pmic = {
|
||||
.slew_rate = 4000,
|
||||
.step_size = 12500,
|
||||
.on_volt = 1100000,
|
||||
.onlp_volt = 1100000,
|
||||
.ret_volt = 837500,
|
||||
.off_volt = 600000,
|
||||
.step_size = 12660,
|
||||
.on_volt = 1188000,
|
||||
.onlp_volt = 1188000,
|
||||
.ret_volt = 830000,
|
||||
.off_volt = 0,
|
||||
.volt_setup_time = 0,
|
||||
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
|
||||
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
|
||||
@ -218,18 +234,20 @@ static struct omap_volt_pmic_info omap4_iva_volt_info = {
|
||||
.vp_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
|
||||
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
|
||||
.i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
|
||||
.pmic_reg = OMAP4_VDD_IVA_SR_VOLT_REG,
|
||||
.volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG,
|
||||
.cmd_reg_addr = OMAP4_VDD_IVA_SR_CMD_REG,
|
||||
.i2c_high_speed = true,
|
||||
.vsel_to_uv = twl6030_vsel_to_uv,
|
||||
.uv_to_vsel = twl6030_uv_to_vsel,
|
||||
};
|
||||
|
||||
static struct omap_volt_pmic_info omap4_core_volt_info = {
|
||||
static struct omap_voltdm_pmic omap4_core_pmic = {
|
||||
.slew_rate = 4000,
|
||||
.step_size = 12500,
|
||||
.on_volt = 1100000,
|
||||
.onlp_volt = 1100000,
|
||||
.ret_volt = 837500,
|
||||
.off_volt = 600000,
|
||||
.step_size = 12660,
|
||||
.on_volt = 1200000,
|
||||
.onlp_volt = 1200000,
|
||||
.ret_volt = 830000,
|
||||
.off_volt = 0,
|
||||
.volt_setup_time = 0,
|
||||
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
|
||||
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
|
||||
@ -238,7 +256,8 @@ static struct omap_volt_pmic_info omap4_core_volt_info = {
|
||||
.vp_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
|
||||
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
|
||||
.i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
|
||||
.pmic_reg = OMAP4_VDD_CORE_SR_VOLT_REG,
|
||||
.volt_reg_addr = OMAP4_VDD_CORE_SR_VOLT_REG,
|
||||
.cmd_reg_addr = OMAP4_VDD_CORE_SR_CMD_REG,
|
||||
.vsel_to_uv = twl6030_vsel_to_uv,
|
||||
.uv_to_vsel = twl6030_uv_to_vsel,
|
||||
};
|
||||
@ -250,14 +269,14 @@ int __init omap4_twl_init(void)
|
||||
if (!cpu_is_omap44xx())
|
||||
return -ENODEV;
|
||||
|
||||
voltdm = omap_voltage_domain_lookup("mpu");
|
||||
omap_voltage_register_pmic(voltdm, &omap4_mpu_volt_info);
|
||||
voltdm = voltdm_lookup("mpu");
|
||||
omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic);
|
||||
|
||||
voltdm = omap_voltage_domain_lookup("iva");
|
||||
omap_voltage_register_pmic(voltdm, &omap4_iva_volt_info);
|
||||
voltdm = voltdm_lookup("iva");
|
||||
omap_voltage_register_pmic(voltdm, &omap4_iva_pmic);
|
||||
|
||||
voltdm = omap_voltage_domain_lookup("core");
|
||||
omap_voltage_register_pmic(voltdm, &omap4_core_volt_info);
|
||||
voltdm = voltdm_lookup("core");
|
||||
omap_voltage_register_pmic(voltdm, &omap4_core_pmic);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -270,10 +289,10 @@ int __init omap3_twl_init(void)
|
||||
return -ENODEV;
|
||||
|
||||
if (cpu_is_omap3630()) {
|
||||
omap3_mpu_volt_info.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
|
||||
omap3_mpu_volt_info.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
|
||||
omap3_core_volt_info.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
|
||||
omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
|
||||
omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
|
||||
omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
|
||||
omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
|
||||
omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -288,11 +307,11 @@ int __init omap3_twl_init(void)
|
||||
if (!twl_sr_enable_autoinit)
|
||||
omap3_twl_set_sr_bit(true);
|
||||
|
||||
voltdm = omap_voltage_domain_lookup("mpu");
|
||||
omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
|
||||
voltdm = voltdm_lookup("mpu_iva");
|
||||
omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
|
||||
|
||||
voltdm = omap_voltage_domain_lookup("core");
|
||||
omap_voltage_register_pmic(voltdm, &omap3_core_volt_info);
|
||||
voltdm = voltdm_lookup("core");
|
||||
omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -69,7 +69,7 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
|
||||
opp_def->hwmod_name, i);
|
||||
return -EINVAL;
|
||||
}
|
||||
dev = &oh->od->pdev.dev;
|
||||
dev = &oh->od->pdev->dev;
|
||||
|
||||
r = opp_add(dev, opp_def->freq, opp_def->u_volt);
|
||||
if (r) {
|
||||
|
@ -26,54 +26,21 @@
|
||||
|
||||
static struct omap_device_pm_latency *pm_lats;
|
||||
|
||||
static struct device *mpu_dev;
|
||||
static struct device *iva_dev;
|
||||
static struct device *l3_dev;
|
||||
static struct device *dsp_dev;
|
||||
|
||||
struct device *omap2_get_mpuss_device(void)
|
||||
{
|
||||
WARN_ON_ONCE(!mpu_dev);
|
||||
return mpu_dev;
|
||||
}
|
||||
|
||||
struct device *omap2_get_iva_device(void)
|
||||
{
|
||||
WARN_ON_ONCE(!iva_dev);
|
||||
return iva_dev;
|
||||
}
|
||||
|
||||
struct device *omap2_get_l3_device(void)
|
||||
{
|
||||
WARN_ON_ONCE(!l3_dev);
|
||||
return l3_dev;
|
||||
}
|
||||
|
||||
struct device *omap4_get_dsp_device(void)
|
||||
{
|
||||
WARN_ON_ONCE(!dsp_dev);
|
||||
return dsp_dev;
|
||||
}
|
||||
EXPORT_SYMBOL(omap4_get_dsp_device);
|
||||
|
||||
/* static int _init_omap_device(struct omap_hwmod *oh, void *user) */
|
||||
static int _init_omap_device(char *name, struct device **new_dev)
|
||||
static int _init_omap_device(char *name)
|
||||
{
|
||||
struct omap_hwmod *oh;
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
|
||||
oh = omap_hwmod_lookup(name);
|
||||
if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
|
||||
__func__, name))
|
||||
return -ENODEV;
|
||||
|
||||
od = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false);
|
||||
if (WARN(IS_ERR(od), "%s: could not build omap_device for %s\n",
|
||||
pdev = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false);
|
||||
if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n",
|
||||
__func__, name))
|
||||
return -ENODEV;
|
||||
|
||||
*new_dev = &od->pdev.dev;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -82,16 +49,16 @@ static int _init_omap_device(char *name, struct device **new_dev)
|
||||
*/
|
||||
static void omap2_init_processor_devices(void)
|
||||
{
|
||||
_init_omap_device("mpu", &mpu_dev);
|
||||
_init_omap_device("mpu");
|
||||
if (omap3_has_iva())
|
||||
_init_omap_device("iva", &iva_dev);
|
||||
_init_omap_device("iva");
|
||||
|
||||
if (cpu_is_omap44xx()) {
|
||||
_init_omap_device("l3_main_1", &l3_dev);
|
||||
_init_omap_device("dsp", &dsp_dev);
|
||||
_init_omap_device("iva", &iva_dev);
|
||||
_init_omap_device("l3_main_1");
|
||||
_init_omap_device("dsp");
|
||||
_init_omap_device("iva");
|
||||
} else {
|
||||
_init_omap_device("l3_main", &l3_dev);
|
||||
_init_omap_device("l3_main");
|
||||
}
|
||||
}
|
||||
|
||||
@ -136,8 +103,8 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
|
||||
|
||||
ret = pwrdm_set_next_pwrst(pwrdm, state);
|
||||
if (ret) {
|
||||
printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
|
||||
pwrdm->name);
|
||||
pr_err("%s: unable to set state of powerdomain: %s\n",
|
||||
__func__, pwrdm->name);
|
||||
goto err;
|
||||
}
|
||||
|
||||
@ -161,37 +128,44 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
|
||||
}
|
||||
|
||||
/*
|
||||
* This API is to be called during init to put the various voltage
|
||||
* This API is to be called during init to set the various voltage
|
||||
* domains to the voltage as per the opp table. Typically we boot up
|
||||
* at the nominal voltage. So this function finds out the rate of
|
||||
* the clock associated with the voltage domain, finds out the correct
|
||||
* opp entry and puts the voltage domain to the voltage specifies
|
||||
* opp entry and sets the voltage domain to the voltage specified
|
||||
* in the opp entry
|
||||
*/
|
||||
static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
|
||||
struct device *dev)
|
||||
const char *oh_name)
|
||||
{
|
||||
struct voltagedomain *voltdm;
|
||||
struct clk *clk;
|
||||
struct opp *opp;
|
||||
unsigned long freq, bootup_volt;
|
||||
struct device *dev;
|
||||
|
||||
if (!vdd_name || !clk_name || !dev) {
|
||||
printk(KERN_ERR "%s: Invalid parameters!\n", __func__);
|
||||
if (!vdd_name || !clk_name || !oh_name) {
|
||||
pr_err("%s: invalid parameters\n", __func__);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
voltdm = omap_voltage_domain_lookup(vdd_name);
|
||||
dev = omap_device_get_by_hwmod_name(oh_name);
|
||||
if (IS_ERR(dev)) {
|
||||
pr_err("%s: Unable to get dev pointer for hwmod %s\n",
|
||||
__func__, oh_name);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
voltdm = voltdm_lookup(vdd_name);
|
||||
if (IS_ERR(voltdm)) {
|
||||
printk(KERN_ERR "%s: Unable to get vdd pointer for vdd_%s\n",
|
||||
pr_err("%s: unable to get vdd pointer for vdd_%s\n",
|
||||
__func__, vdd_name);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
clk = clk_get(NULL, clk_name);
|
||||
if (IS_ERR(clk)) {
|
||||
printk(KERN_ERR "%s: unable to get clk %s\n",
|
||||
__func__, clk_name);
|
||||
pr_err("%s: unable to get clk %s\n", __func__, clk_name);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
@ -200,24 +174,23 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
|
||||
|
||||
opp = opp_find_freq_ceil(dev, &freq);
|
||||
if (IS_ERR(opp)) {
|
||||
printk(KERN_ERR "%s: unable to find boot up OPP for vdd_%s\n",
|
||||
pr_err("%s: unable to find boot up OPP for vdd_%s\n",
|
||||
__func__, vdd_name);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
bootup_volt = opp_get_voltage(opp);
|
||||
if (!bootup_volt) {
|
||||
printk(KERN_ERR "%s: unable to find voltage corresponding"
|
||||
pr_err("%s: unable to find voltage corresponding "
|
||||
"to the bootup OPP for vdd_%s\n", __func__, vdd_name);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
omap_voltage_scale_vdd(voltdm, bootup_volt);
|
||||
voltdm_scale(voltdm, bootup_volt);
|
||||
return 0;
|
||||
|
||||
exit:
|
||||
printk(KERN_ERR "%s: Unable to put vdd_%s to its init voltage\n\n",
|
||||
__func__, vdd_name);
|
||||
pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@ -226,8 +199,8 @@ static void __init omap3_init_voltages(void)
|
||||
if (!cpu_is_omap34xx())
|
||||
return;
|
||||
|
||||
omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev);
|
||||
omap2_set_init_voltage("core", "l3_ick", l3_dev);
|
||||
omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
|
||||
omap2_set_init_voltage("core", "l3_ick", "l3_main");
|
||||
}
|
||||
|
||||
static void __init omap4_init_voltages(void)
|
||||
@ -235,14 +208,15 @@ static void __init omap4_init_voltages(void)
|
||||
if (!cpu_is_omap44xx())
|
||||
return;
|
||||
|
||||
omap2_set_init_voltage("mpu", "dpll_mpu_ck", mpu_dev);
|
||||
omap2_set_init_voltage("core", "l3_div_ck", l3_dev);
|
||||
omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", iva_dev);
|
||||
omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu");
|
||||
omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1");
|
||||
omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
|
||||
}
|
||||
|
||||
static int __init omap2_common_pm_init(void)
|
||||
{
|
||||
omap2_init_processor_devices();
|
||||
if (!of_have_populated_dt())
|
||||
omap2_init_processor_devices();
|
||||
omap_pm_if_init();
|
||||
|
||||
return 0;
|
||||
|
@ -53,8 +53,6 @@
|
||||
#include "powerdomain.h"
|
||||
#include "clockdomain.h"
|
||||
|
||||
static int omap2_pm_debug;
|
||||
|
||||
#ifdef CONFIG_SUSPEND
|
||||
static suspend_state_t suspend_state = PM_SUSPEND_ON;
|
||||
static inline bool is_suspending(void)
|
||||
@ -96,7 +94,6 @@ static int omap2_fclks_active(void)
|
||||
static void omap2_enter_full_retention(void)
|
||||
{
|
||||
u32 l;
|
||||
struct timespec ts_preidle, ts_postidle, ts_idle;
|
||||
|
||||
/* There is 1 reference hold for all children of the oscillator
|
||||
* clock, the following will remove it. If no one else uses the
|
||||
@ -124,10 +121,6 @@ static void omap2_enter_full_retention(void)
|
||||
|
||||
omap2_gpio_prepare_for_idle(0);
|
||||
|
||||
if (omap2_pm_debug) {
|
||||
getnstimeofday(&ts_preidle);
|
||||
}
|
||||
|
||||
/* One last check for pending IRQs to avoid extra latency due
|
||||
* to sleeping unnecessarily. */
|
||||
if (omap_irq_pending())
|
||||
@ -155,13 +148,6 @@ static void omap2_enter_full_retention(void)
|
||||
console_unlock();
|
||||
|
||||
no_sleep:
|
||||
if (omap2_pm_debug) {
|
||||
unsigned long long tmp;
|
||||
|
||||
getnstimeofday(&ts_postidle);
|
||||
ts_idle = timespec_sub(ts_postidle, ts_preidle);
|
||||
tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
|
||||
}
|
||||
omap2_gpio_resume_after_idle();
|
||||
|
||||
clk_enable(osc_ck);
|
||||
@ -219,7 +205,6 @@ static int omap2_allow_mpu_retention(void)
|
||||
static void omap2_enter_mpu_retention(void)
|
||||
{
|
||||
int only_idle = 0;
|
||||
struct timespec ts_preidle, ts_postidle, ts_idle;
|
||||
|
||||
/* Putting MPU into the WFI state while a transfer is active
|
||||
* seems to cause the I2C block to timeout. Why? Good question. */
|
||||
@ -246,19 +231,7 @@ static void omap2_enter_mpu_retention(void)
|
||||
only_idle = 1;
|
||||
}
|
||||
|
||||
if (omap2_pm_debug) {
|
||||
getnstimeofday(&ts_preidle);
|
||||
}
|
||||
|
||||
omap2_sram_idle();
|
||||
|
||||
if (omap2_pm_debug) {
|
||||
unsigned long long tmp;
|
||||
|
||||
getnstimeofday(&ts_postidle);
|
||||
ts_idle = timespec_sub(ts_postidle, ts_preidle);
|
||||
tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
|
||||
}
|
||||
}
|
||||
|
||||
static int omap2_can_sleep(void)
|
||||
|
@ -55,7 +55,7 @@
|
||||
static suspend_state_t suspend_state = PM_SUSPEND_ON;
|
||||
static inline bool is_suspending(void)
|
||||
{
|
||||
return (suspend_state != PM_SUSPEND_ON);
|
||||
return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
|
||||
}
|
||||
#else
|
||||
static inline bool is_suspending(void)
|
||||
|
@ -1,9 +1,8 @@
|
||||
/*
|
||||
* linux/arch/arm/mach-omap2/powerdomain-common.c
|
||||
* Contains common powerdomain framework functions
|
||||
* Common powerdomain framework functions
|
||||
*
|
||||
* Copyright (C) 2010 Texas Instruments, Inc.
|
||||
* Copyright (C) 2010 Nokia Corporation
|
||||
* Copyright (C) 2010-2011 Texas Instruments, Inc.
|
||||
* Copyright (C) 2010 Nokia Corporation
|
||||
*
|
||||
* Derived from mach-omap2/powerdomain.c written by Paul Walmsley
|
||||
*
|
||||
|
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* OMAP powerdomain control
|
||||
*
|
||||
* Copyright (C) 2007-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2011 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley
|
||||
@ -77,13 +77,11 @@ static struct powerdomain *_pwrdm_lookup(const char *name)
|
||||
static int _pwrdm_register(struct powerdomain *pwrdm)
|
||||
{
|
||||
int i;
|
||||
struct voltagedomain *voltdm;
|
||||
|
||||
if (!pwrdm || !pwrdm->name)
|
||||
return -EINVAL;
|
||||
|
||||
if (!omap_chip_is(pwrdm->omap_chip))
|
||||
return -EINVAL;
|
||||
|
||||
if (cpu_is_omap44xx() &&
|
||||
pwrdm->prcm_partition == OMAP4430_INVALID_PRCM_PARTITION) {
|
||||
pr_err("powerdomain: %s: missing OMAP4 PRCM partition ID\n",
|
||||
@ -94,6 +92,16 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
|
||||
if (_pwrdm_lookup(pwrdm->name))
|
||||
return -EEXIST;
|
||||
|
||||
voltdm = voltdm_lookup(pwrdm->voltdm.name);
|
||||
if (!voltdm) {
|
||||
pr_err("powerdomain: %s: voltagedomain %s does not exist\n",
|
||||
pwrdm->name, pwrdm->voltdm.name);
|
||||
return -EINVAL;
|
||||
}
|
||||
pwrdm->voltdm.ptr = voltdm;
|
||||
INIT_LIST_HEAD(&pwrdm->voltdm_node);
|
||||
voltdm_add_pwrdm(voltdm, pwrdm);
|
||||
|
||||
list_add(&pwrdm->node, &pwrdm_list);
|
||||
|
||||
/* Initialize the powerdomain's state counter */
|
||||
@ -194,36 +202,76 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
|
||||
/* Public functions */
|
||||
|
||||
/**
|
||||
* pwrdm_init - set up the powerdomain layer
|
||||
* @pwrdms: array of struct powerdomain pointers to register
|
||||
* @custom_funcs: func pointers for arch specific implementations
|
||||
* pwrdm_register_platform_funcs - register powerdomain implementation fns
|
||||
* @po: func pointers for arch specific implementations
|
||||
*
|
||||
* Loop through the array of powerdomains @pwrdms, registering all
|
||||
* that are available on the current CPU. Also, program all
|
||||
* powerdomain target state as ON; this is to prevent domains from
|
||||
* hitting low power states (if bootloader has target states set to
|
||||
* something other than ON) and potentially even losing context while
|
||||
* PM is not fully initialized. The PM late init code can then program
|
||||
* the desired target state for all the power domains. No return
|
||||
* value.
|
||||
* Register the list of function pointers used to implement the
|
||||
* powerdomain functions on different OMAP SoCs. Should be called
|
||||
* before any other pwrdm_register*() function. Returns -EINVAL if
|
||||
* @po is null, -EEXIST if platform functions have already been
|
||||
* registered, or 0 upon success.
|
||||
*/
|
||||
void pwrdm_init(struct powerdomain **pwrdms, struct pwrdm_ops *custom_funcs)
|
||||
int pwrdm_register_platform_funcs(struct pwrdm_ops *po)
|
||||
{
|
||||
if (!po)
|
||||
return -EINVAL;
|
||||
|
||||
if (arch_pwrdm)
|
||||
return -EEXIST;
|
||||
|
||||
arch_pwrdm = po;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* pwrdm_register_pwrdms - register SoC powerdomains
|
||||
* @ps: pointer to an array of struct powerdomain to register
|
||||
*
|
||||
* Register the powerdomains available on a particular OMAP SoC. Must
|
||||
* be called after pwrdm_register_platform_funcs(). May be called
|
||||
* multiple times. Returns -EACCES if called before
|
||||
* pwrdm_register_platform_funcs(); -EINVAL if the argument @ps is
|
||||
* null; or 0 upon success.
|
||||
*/
|
||||
int pwrdm_register_pwrdms(struct powerdomain **ps)
|
||||
{
|
||||
struct powerdomain **p = NULL;
|
||||
|
||||
if (!arch_pwrdm)
|
||||
return -EEXIST;
|
||||
|
||||
if (!ps)
|
||||
return -EINVAL;
|
||||
|
||||
for (p = ps; *p; p++)
|
||||
_pwrdm_register(*p);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* pwrdm_complete_init - set up the powerdomain layer
|
||||
*
|
||||
* Do whatever is necessary to initialize registered powerdomains and
|
||||
* powerdomain code. Currently, this programs the next power state
|
||||
* for each powerdomain to ON. This prevents powerdomains from
|
||||
* unexpectedly losing context or entering high wakeup latency modes
|
||||
* with non-power-management-enabled kernels. Must be called after
|
||||
* pwrdm_register_pwrdms(). Returns -EACCES if called before
|
||||
* pwrdm_register_pwrdms(), or 0 upon success.
|
||||
*/
|
||||
int pwrdm_complete_init(void)
|
||||
{
|
||||
struct powerdomain *temp_p;
|
||||
|
||||
if (!custom_funcs)
|
||||
WARN(1, "powerdomain: No custom pwrdm functions registered\n");
|
||||
else
|
||||
arch_pwrdm = custom_funcs;
|
||||
|
||||
if (pwrdms) {
|
||||
for (p = pwrdms; *p; p++)
|
||||
_pwrdm_register(*p);
|
||||
}
|
||||
if (list_empty(&pwrdm_list))
|
||||
return -EACCES;
|
||||
|
||||
list_for_each_entry(temp_p, &pwrdm_list, node)
|
||||
pwrdm_set_next_pwrst(temp_p, PWRDM_POWER_ON);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -389,6 +437,18 @@ int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* pwrdm_get_voltdm - return a ptr to the voltdm that this pwrdm resides in
|
||||
* @pwrdm: struct powerdomain *
|
||||
*
|
||||
* Return a pointer to the struct voltageomain that the specified powerdomain
|
||||
* @pwrdm exists in.
|
||||
*/
|
||||
struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm)
|
||||
{
|
||||
return pwrdm->voltdm.ptr;
|
||||
}
|
||||
|
||||
/**
|
||||
* pwrdm_get_mem_bank_count - get number of memory banks in this powerdomain
|
||||
* @pwrdm: struct powerdomain *
|
||||
|
@ -24,6 +24,8 @@
|
||||
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include "voltage.h"
|
||||
|
||||
/* Powerdomain basic power states */
|
||||
#define PWRDM_POWER_OFF 0x0
|
||||
#define PWRDM_POWER_RET 0x1
|
||||
@ -78,7 +80,7 @@ struct powerdomain;
|
||||
/**
|
||||
* struct powerdomain - OMAP powerdomain
|
||||
* @name: Powerdomain name
|
||||
* @omap_chip: represents the OMAP chip types containing this pwrdm
|
||||
* @voltdm: voltagedomain containing this powerdomain
|
||||
* @prcm_offs: the address offset from CM_BASE/PRM_BASE
|
||||
* @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
|
||||
* @pwrsts: Possible powerdomain power states
|
||||
@ -89,6 +91,7 @@ struct powerdomain;
|
||||
* @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
|
||||
* @pwrdm_clkdms: Clockdomains in this powerdomain
|
||||
* @node: list_head linking all powerdomains
|
||||
* @voltdm_node: list_head linking all powerdomains in a voltagedomain
|
||||
* @state:
|
||||
* @state_counter:
|
||||
* @timer:
|
||||
@ -98,7 +101,10 @@ struct powerdomain;
|
||||
*/
|
||||
struct powerdomain {
|
||||
const char *name;
|
||||
const struct omap_chip_id omap_chip;
|
||||
union {
|
||||
const char *name;
|
||||
struct voltagedomain *ptr;
|
||||
} voltdm;
|
||||
const s16 prcm_offs;
|
||||
const u8 pwrsts;
|
||||
const u8 pwrsts_logic_ret;
|
||||
@ -109,6 +115,7 @@ struct powerdomain {
|
||||
const u8 prcm_partition;
|
||||
struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
|
||||
struct list_head node;
|
||||
struct list_head voltdm_node;
|
||||
int state;
|
||||
unsigned state_counter[PWRDM_MAX_PWRSTS];
|
||||
unsigned ret_logic_off_counter;
|
||||
@ -162,7 +169,9 @@ struct pwrdm_ops {
|
||||
int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
|
||||
};
|
||||
|
||||
void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs);
|
||||
int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
|
||||
int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
|
||||
int pwrdm_complete_init(void);
|
||||
|
||||
struct powerdomain *pwrdm_lookup(const char *name);
|
||||
|
||||
@ -176,6 +185,7 @@ int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
|
||||
int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
|
||||
int (*fn)(struct powerdomain *pwrdm,
|
||||
struct clockdomain *clkdm));
|
||||
struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
|
||||
|
||||
int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
|
||||
|
||||
@ -210,7 +220,8 @@ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
|
||||
u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
|
||||
bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
|
||||
|
||||
extern void omap2xxx_powerdomains_init(void);
|
||||
extern void omap242x_powerdomains_init(void);
|
||||
extern void omap243x_powerdomains_init(void);
|
||||
extern void omap3xxx_powerdomains_init(void);
|
||||
extern void omap44xx_powerdomains_init(void);
|
||||
|
||||
|
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* OMAP2 and OMAP3 powerdomain control
|
||||
*
|
||||
* Copyright (C) 2009-2010 Texas Instruments, Inc.
|
||||
* Copyright (C) 2009-2011 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2009 Nokia Corporation
|
||||
*
|
||||
* Derived from mach-omap2/powerdomain.c written by Paul Walmsley
|
||||
|
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* OMAP2/3 common powerdomain definitions
|
||||
*
|
||||
* Copyright (C) 2007-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2011 Nokia Corporation
|
||||
*
|
||||
* Paul Walmsley, Jouni Högander
|
||||
@ -11,20 +11,6 @@
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* To Do List
|
||||
* -> Move the Sleep/Wakeup dependencies from Power Domain framework to
|
||||
* Clock Domain Framework
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file contains all of the powerdomains that have some element
|
||||
* of software control for the OMAP24xx and OMAP34xx chips.
|
||||
*
|
||||
* This is not an exhaustive listing of powerdomains on the chips; only
|
||||
* powerdomains that can be controlled in software.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The names for the DSP/IVA2 powerdomains are confusing.
|
||||
*
|
||||
@ -59,8 +45,6 @@
|
||||
struct powerdomain gfx_omap2_pwrdm = {
|
||||
.name = "gfx_pwrdm",
|
||||
.prcm_offs = GFX_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
|
||||
CHIP_IS_OMAP3430ES1),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_RET,
|
||||
.banks = 1,
|
||||
@ -70,11 +54,12 @@ struct powerdomain gfx_omap2_pwrdm = {
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* MEMONSTATE */
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
struct powerdomain wkup_omap2_pwrdm = {
|
||||
.name = "wkup_pwrdm",
|
||||
.prcm_offs = WKUP_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.voltdm = { .name = "wakeup" },
|
||||
};
|
||||
|
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* OMAP2XXX powerdomain definitions
|
||||
*
|
||||
* Copyright (C) 2007-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2011 Nokia Corporation
|
||||
*
|
||||
* Paul Walmsley, Jouni Högander
|
||||
@ -28,7 +28,6 @@
|
||||
static struct powerdomain dsp_pwrdm = {
|
||||
.name = "dsp_pwrdm",
|
||||
.prcm_offs = OMAP24XX_DSP_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_RET,
|
||||
.banks = 1,
|
||||
@ -38,12 +37,12 @@ static struct powerdomain dsp_pwrdm = {
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON,
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain mpu_24xx_pwrdm = {
|
||||
.name = "mpu_pwrdm",
|
||||
.prcm_offs = MPU_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 1,
|
||||
@ -53,12 +52,12 @@ static struct powerdomain mpu_24xx_pwrdm = {
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON,
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain core_24xx_pwrdm = {
|
||||
.name = "core_pwrdm",
|
||||
.prcm_offs = CORE_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.banks = 3,
|
||||
.pwrsts_mem_ret = {
|
||||
@ -71,6 +70,7 @@ static struct powerdomain core_24xx_pwrdm = {
|
||||
[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
|
||||
[2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
|
||||
@ -78,14 +78,11 @@ static struct powerdomain core_24xx_pwrdm = {
|
||||
* 2430-specific powerdomains
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SOC_OMAP2430
|
||||
|
||||
/* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */
|
||||
|
||||
static struct powerdomain mdm_pwrdm = {
|
||||
.name = "mdm_pwrdm",
|
||||
.prcm_offs = OMAP2430_MDM_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_RET,
|
||||
.banks = 1,
|
||||
@ -95,29 +92,44 @@ static struct powerdomain mdm_pwrdm = {
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* MEMONSTATE */
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
#endif /* CONFIG_SOC_OMAP2430 */
|
||||
|
||||
/* As powerdomains are added or removed above, this list must also be changed */
|
||||
static struct powerdomain *powerdomains_omap2xxx[] __initdata = {
|
||||
/*
|
||||
*
|
||||
*/
|
||||
|
||||
static struct powerdomain *powerdomains_omap24xx[] __initdata = {
|
||||
&wkup_omap2_pwrdm,
|
||||
&gfx_omap2_pwrdm,
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2
|
||||
&dsp_pwrdm,
|
||||
&mpu_24xx_pwrdm,
|
||||
&core_24xx_pwrdm,
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_OMAP2430
|
||||
&mdm_pwrdm,
|
||||
#endif
|
||||
NULL
|
||||
};
|
||||
|
||||
void __init omap2xxx_powerdomains_init(void)
|
||||
static struct powerdomain *powerdomains_omap2430[] __initdata = {
|
||||
&mdm_pwrdm,
|
||||
NULL
|
||||
};
|
||||
|
||||
void __init omap242x_powerdomains_init(void)
|
||||
{
|
||||
pwrdm_init(powerdomains_omap2xxx, &omap2_pwrdm_operations);
|
||||
if (!cpu_is_omap2420())
|
||||
return;
|
||||
|
||||
pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
|
||||
pwrdm_register_pwrdms(powerdomains_omap24xx);
|
||||
pwrdm_complete_init();
|
||||
}
|
||||
|
||||
void __init omap243x_powerdomains_init(void)
|
||||
{
|
||||
if (!cpu_is_omap2430())
|
||||
return;
|
||||
|
||||
pwrdm_register_platform_funcs(&omap2_pwrdm_operations);
|
||||
pwrdm_register_pwrdms(powerdomains_omap24xx);
|
||||
pwrdm_register_pwrdms(powerdomains_omap2430);
|
||||
pwrdm_complete_init();
|
||||
}
|
||||
|
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* OMAP3 powerdomain definitions
|
||||
*
|
||||
* Copyright (C) 2007-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2011 Nokia Corporation
|
||||
*
|
||||
* Paul Walmsley, Jouni Högander
|
||||
@ -14,6 +14,8 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include "powerdomain.h"
|
||||
#include "powerdomains2xxx_3xxx_data.h"
|
||||
|
||||
@ -27,8 +29,6 @@
|
||||
* 34XX-specific powerdomains, dependencies
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
|
||||
/*
|
||||
* Powerdomains
|
||||
*/
|
||||
@ -36,7 +36,6 @@
|
||||
static struct powerdomain iva2_pwrdm = {
|
||||
.name = "iva2_pwrdm",
|
||||
.prcm_offs = OMAP3430_IVA2_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 4,
|
||||
@ -52,12 +51,12 @@ static struct powerdomain iva2_pwrdm = {
|
||||
[2] = PWRSTS_OFF_ON,
|
||||
[3] = PWRSTS_ON,
|
||||
},
|
||||
.voltdm = { .name = "mpu_iva" },
|
||||
};
|
||||
|
||||
static struct powerdomain mpu_3xxx_pwrdm = {
|
||||
.name = "mpu_pwrdm",
|
||||
.prcm_offs = MPU_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.flags = PWRDM_HAS_MPU_QUIRK,
|
||||
@ -68,6 +67,7 @@ static struct powerdomain mpu_3xxx_pwrdm = {
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_OFF_ON,
|
||||
},
|
||||
.voltdm = { .name = "mpu_iva" },
|
||||
};
|
||||
|
||||
/*
|
||||
@ -83,10 +83,6 @@ static struct powerdomain mpu_3xxx_pwrdm = {
|
||||
static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
|
||||
.name = "core_pwrdm",
|
||||
.prcm_offs = CORE_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
|
||||
CHIP_IS_OMAP3430ES2 |
|
||||
CHIP_IS_OMAP3430ES3_0 |
|
||||
CHIP_IS_OMAP3630ES1),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 2,
|
||||
@ -98,13 +94,12 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
|
||||
[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
|
||||
[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain core_3xxx_es3_1_pwrdm = {
|
||||
.name = "core_pwrdm",
|
||||
.prcm_offs = CORE_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 |
|
||||
CHIP_GE_OMAP3630ES1_1),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
/*
|
||||
@ -121,11 +116,11 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = {
|
||||
[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
|
||||
[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain dss_pwrdm = {
|
||||
.name = "dss_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.prcm_offs = OMAP3430_DSS_MOD,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_RET,
|
||||
@ -136,6 +131,7 @@ static struct powerdomain dss_pwrdm = {
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* MEMONSTATE */
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
/*
|
||||
@ -146,7 +142,6 @@ static struct powerdomain dss_pwrdm = {
|
||||
static struct powerdomain sgx_pwrdm = {
|
||||
.name = "sgx_pwrdm",
|
||||
.prcm_offs = OMAP3430ES2_SGX_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
|
||||
/* XXX This is accurate for 3430 SGX, but what about GFX? */
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_RET,
|
||||
@ -157,11 +152,11 @@ static struct powerdomain sgx_pwrdm = {
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* MEMONSTATE */
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain cam_pwrdm = {
|
||||
.name = "cam_pwrdm",
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.prcm_offs = OMAP3430_CAM_MOD,
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_RET,
|
||||
@ -172,12 +167,12 @@ static struct powerdomain cam_pwrdm = {
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* MEMONSTATE */
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain per_pwrdm = {
|
||||
.name = "per_pwrdm",
|
||||
.prcm_offs = OMAP3430_PER_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 1,
|
||||
@ -187,26 +182,26 @@ static struct powerdomain per_pwrdm = {
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* MEMONSTATE */
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain emu_pwrdm = {
|
||||
.name = "emu_pwrdm",
|
||||
.prcm_offs = OMAP3430_EMU_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain neon_pwrdm = {
|
||||
.name = "neon_pwrdm",
|
||||
.prcm_offs = OMAP3430_NEON_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_RET,
|
||||
.voltdm = { .name = "mpu_iva" },
|
||||
};
|
||||
|
||||
static struct powerdomain usbhost_pwrdm = {
|
||||
.name = "usbhost_pwrdm",
|
||||
.prcm_offs = OMAP3430ES2_USBHOST_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_RET,
|
||||
/*
|
||||
@ -223,65 +218,103 @@ static struct powerdomain usbhost_pwrdm = {
|
||||
.pwrsts_mem_on = {
|
||||
[0] = PWRSTS_ON, /* MEMONSTATE */
|
||||
},
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain dpll1_pwrdm = {
|
||||
.name = "dpll1_pwrdm",
|
||||
.prcm_offs = MPU_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.voltdm = { .name = "mpu_iva" },
|
||||
};
|
||||
|
||||
static struct powerdomain dpll2_pwrdm = {
|
||||
.name = "dpll2_pwrdm",
|
||||
.prcm_offs = OMAP3430_IVA2_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.voltdm = { .name = "mpu_iva" },
|
||||
};
|
||||
|
||||
static struct powerdomain dpll3_pwrdm = {
|
||||
.name = "dpll3_pwrdm",
|
||||
.prcm_offs = PLL_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain dpll4_pwrdm = {
|
||||
.name = "dpll4_pwrdm",
|
||||
.prcm_offs = PLL_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
static struct powerdomain dpll5_pwrdm = {
|
||||
.name = "dpll5_pwrdm",
|
||||
.prcm_offs = PLL_MOD,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
|
||||
.voltdm = { .name = "core" },
|
||||
};
|
||||
|
||||
/* As powerdomains are added or removed above, this list must also be changed */
|
||||
static struct powerdomain *powerdomains_omap3xxx[] __initdata = {
|
||||
|
||||
static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
|
||||
&wkup_omap2_pwrdm,
|
||||
&gfx_omap2_pwrdm,
|
||||
&iva2_pwrdm,
|
||||
&mpu_3xxx_pwrdm,
|
||||
&neon_pwrdm,
|
||||
&core_3xxx_pre_es3_1_pwrdm,
|
||||
&core_3xxx_es3_1_pwrdm,
|
||||
&cam_pwrdm,
|
||||
&dss_pwrdm,
|
||||
&per_pwrdm,
|
||||
&emu_pwrdm,
|
||||
&sgx_pwrdm,
|
||||
&usbhost_pwrdm,
|
||||
&dpll1_pwrdm,
|
||||
&dpll2_pwrdm,
|
||||
&dpll3_pwrdm,
|
||||
&dpll4_pwrdm,
|
||||
&dpll5_pwrdm,
|
||||
#endif
|
||||
NULL
|
||||
};
|
||||
|
||||
static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
|
||||
&gfx_omap2_pwrdm,
|
||||
&core_3xxx_pre_es3_1_pwrdm,
|
||||
NULL
|
||||
};
|
||||
|
||||
/* also includes 3630ES1.0 */
|
||||
static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
|
||||
&core_3xxx_pre_es3_1_pwrdm,
|
||||
&sgx_pwrdm,
|
||||
&usbhost_pwrdm,
|
||||
&dpll5_pwrdm,
|
||||
NULL
|
||||
};
|
||||
|
||||
/* also includes 3630ES1.1+ */
|
||||
static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
|
||||
&core_3xxx_es3_1_pwrdm,
|
||||
&sgx_pwrdm,
|
||||
&usbhost_pwrdm,
|
||||
&dpll5_pwrdm,
|
||||
NULL
|
||||
};
|
||||
|
||||
void __init omap3xxx_powerdomains_init(void)
|
||||
{
|
||||
pwrdm_init(powerdomains_omap3xxx, &omap3_pwrdm_operations);
|
||||
unsigned int rev;
|
||||
|
||||
if (!cpu_is_omap34xx())
|
||||
return;
|
||||
|
||||
pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
|
||||
pwrdm_register_pwrdms(powerdomains_omap3430_common);
|
||||
|
||||
rev = omap_rev();
|
||||
|
||||
if (rev == OMAP3430_REV_ES1_0)
|
||||
pwrdm_register_pwrdms(powerdomains_omap3430es1);
|
||||
else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
|
||||
rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0)
|
||||
pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
|
||||
else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 ||
|
||||
rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1 ||
|
||||
rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2)
|
||||
pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
|
||||
else
|
||||
WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
|
||||
|
||||
pwrdm_complete_init();
|
||||
}
|
||||
|
@ -33,9 +33,9 @@
|
||||
/* core_44xx_pwrdm: CORE power domain */
|
||||
static struct powerdomain core_44xx_pwrdm = {
|
||||
.name = "core_pwrdm",
|
||||
.voltdm = { .name = "core" },
|
||||
.prcm_offs = OMAP4430_PRM_CORE_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 5,
|
||||
@ -59,9 +59,9 @@ static struct powerdomain core_44xx_pwrdm = {
|
||||
/* gfx_44xx_pwrdm: 3D accelerator power domain */
|
||||
static struct powerdomain gfx_44xx_pwrdm = {
|
||||
.name = "gfx_pwrdm",
|
||||
.voltdm = { .name = "core" },
|
||||
.prcm_offs = OMAP4430_PRM_GFX_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
@ -76,9 +76,9 @@ static struct powerdomain gfx_44xx_pwrdm = {
|
||||
/* abe_44xx_pwrdm: Audio back end power domain */
|
||||
static struct powerdomain abe_44xx_pwrdm = {
|
||||
.name = "abe_pwrdm",
|
||||
.voltdm = { .name = "iva" },
|
||||
.prcm_offs = OMAP4430_PRM_ABE_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF,
|
||||
.banks = 2,
|
||||
@ -96,9 +96,9 @@ static struct powerdomain abe_44xx_pwrdm = {
|
||||
/* dss_44xx_pwrdm: Display subsystem power domain */
|
||||
static struct powerdomain dss_44xx_pwrdm = {
|
||||
.name = "dss_pwrdm",
|
||||
.voltdm = { .name = "core" },
|
||||
.prcm_offs = OMAP4430_PRM_DSS_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF,
|
||||
.banks = 1,
|
||||
@ -114,9 +114,9 @@ static struct powerdomain dss_44xx_pwrdm = {
|
||||
/* tesla_44xx_pwrdm: Tesla processor power domain */
|
||||
static struct powerdomain tesla_44xx_pwrdm = {
|
||||
.name = "tesla_pwrdm",
|
||||
.voltdm = { .name = "iva" },
|
||||
.prcm_offs = OMAP4430_PRM_TESLA_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 3,
|
||||
@ -136,9 +136,9 @@ static struct powerdomain tesla_44xx_pwrdm = {
|
||||
/* wkup_44xx_pwrdm: Wake-up power domain */
|
||||
static struct powerdomain wkup_44xx_pwrdm = {
|
||||
.name = "wkup_pwrdm",
|
||||
.voltdm = { .name = "wakeup" },
|
||||
.prcm_offs = OMAP4430_PRM_WKUP_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
@ -152,9 +152,9 @@ static struct powerdomain wkup_44xx_pwrdm = {
|
||||
/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
|
||||
static struct powerdomain cpu0_44xx_pwrdm = {
|
||||
.name = "cpu0_pwrdm",
|
||||
.voltdm = { .name = "mpu" },
|
||||
.prcm_offs = OMAP4430_PRCM_MPU_CPU0_INST,
|
||||
.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 1,
|
||||
@ -169,9 +169,9 @@ static struct powerdomain cpu0_44xx_pwrdm = {
|
||||
/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
|
||||
static struct powerdomain cpu1_44xx_pwrdm = {
|
||||
.name = "cpu1_pwrdm",
|
||||
.voltdm = { .name = "mpu" },
|
||||
.prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST,
|
||||
.prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 1,
|
||||
@ -186,9 +186,9 @@ static struct powerdomain cpu1_44xx_pwrdm = {
|
||||
/* emu_44xx_pwrdm: Emulation power domain */
|
||||
static struct powerdomain emu_44xx_pwrdm = {
|
||||
.name = "emu_pwrdm",
|
||||
.voltdm = { .name = "wakeup" },
|
||||
.prcm_offs = OMAP4430_PRM_EMU_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
@ -202,9 +202,9 @@ static struct powerdomain emu_44xx_pwrdm = {
|
||||
/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
|
||||
static struct powerdomain mpu_44xx_pwrdm = {
|
||||
.name = "mpu_pwrdm",
|
||||
.voltdm = { .name = "mpu" },
|
||||
.prcm_offs = OMAP4430_PRM_MPU_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 3,
|
||||
@ -223,9 +223,9 @@ static struct powerdomain mpu_44xx_pwrdm = {
|
||||
/* ivahd_44xx_pwrdm: IVA-HD power domain */
|
||||
static struct powerdomain ivahd_44xx_pwrdm = {
|
||||
.name = "ivahd_pwrdm",
|
||||
.voltdm = { .name = "iva" },
|
||||
.prcm_offs = OMAP4430_PRM_IVAHD_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_OFF_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF,
|
||||
.banks = 4,
|
||||
@ -247,9 +247,9 @@ static struct powerdomain ivahd_44xx_pwrdm = {
|
||||
/* cam_44xx_pwrdm: Camera subsystem power domain */
|
||||
static struct powerdomain cam_44xx_pwrdm = {
|
||||
.name = "cam_pwrdm",
|
||||
.voltdm = { .name = "core" },
|
||||
.prcm_offs = OMAP4430_PRM_CAM_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.banks = 1,
|
||||
.pwrsts_mem_ret = {
|
||||
@ -264,9 +264,9 @@ static struct powerdomain cam_44xx_pwrdm = {
|
||||
/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
|
||||
static struct powerdomain l3init_44xx_pwrdm = {
|
||||
.name = "l3init_pwrdm",
|
||||
.voltdm = { .name = "core" },
|
||||
.prcm_offs = OMAP4430_PRM_L3INIT_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 1,
|
||||
@ -282,9 +282,9 @@ static struct powerdomain l3init_44xx_pwrdm = {
|
||||
/* l4per_44xx_pwrdm: Target peripherals power domain */
|
||||
static struct powerdomain l4per_44xx_pwrdm = {
|
||||
.name = "l4per_pwrdm",
|
||||
.voltdm = { .name = "core" },
|
||||
.prcm_offs = OMAP4430_PRM_L4PER_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
.pwrsts_logic_ret = PWRSTS_OFF_RET,
|
||||
.banks = 2,
|
||||
@ -305,18 +305,18 @@ static struct powerdomain l4per_44xx_pwrdm = {
|
||||
*/
|
||||
static struct powerdomain always_on_core_44xx_pwrdm = {
|
||||
.name = "always_on_core_pwrdm",
|
||||
.voltdm = { .name = "core" },
|
||||
.prcm_offs = OMAP4430_PRM_ALWAYS_ON_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_ON,
|
||||
};
|
||||
|
||||
/* cefuse_44xx_pwrdm: Customer efuse controller power domain */
|
||||
static struct powerdomain cefuse_44xx_pwrdm = {
|
||||
.name = "cefuse_pwrdm",
|
||||
.voltdm = { .name = "core" },
|
||||
.prcm_offs = OMAP4430_PRM_CEFUSE_INST,
|
||||
.prcm_partition = OMAP4430_PRM_PARTITION,
|
||||
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
|
||||
};
|
||||
@ -352,5 +352,7 @@ static struct powerdomain *powerdomains_omap44xx[] __initdata = {
|
||||
|
||||
void __init omap44xx_powerdomains_init(void)
|
||||
{
|
||||
pwrdm_init(powerdomains_omap44xx, &omap4_pwrdm_operations);
|
||||
pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
|
||||
pwrdm_register_pwrdms(powerdomains_omap44xx);
|
||||
pwrdm_complete_init();
|
||||
}
|
||||
|
@ -20,6 +20,8 @@
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/prcm.h>
|
||||
|
||||
#include "vp.h"
|
||||
|
||||
#include "prm2xxx_3xxx.h"
|
||||
#include "cm2xxx_3xxx.h"
|
||||
#include "prm-regbits-24xx.h"
|
||||
@ -156,3 +158,57 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
|
||||
|
||||
return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
|
||||
}
|
||||
|
||||
/* PRM VP */
|
||||
|
||||
/*
|
||||
* struct omap3_vp - OMAP3 VP register access description.
|
||||
* @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
|
||||
*/
|
||||
struct omap3_vp {
|
||||
u32 tranxdone_status;
|
||||
};
|
||||
|
||||
static struct omap3_vp omap3_vp[] = {
|
||||
[OMAP3_VP_VDD_MPU_ID] = {
|
||||
.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
|
||||
},
|
||||
[OMAP3_VP_VDD_CORE_ID] = {
|
||||
.tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
|
||||
|
||||
u32 omap3_prm_vp_check_txdone(u8 vp_id)
|
||||
{
|
||||
struct omap3_vp *vp = &omap3_vp[vp_id];
|
||||
u32 irqstatus;
|
||||
|
||||
irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
|
||||
OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
||||
return irqstatus & vp->tranxdone_status;
|
||||
}
|
||||
|
||||
void omap3_prm_vp_clear_txdone(u8 vp_id)
|
||||
{
|
||||
struct omap3_vp *vp = &omap3_vp[vp_id];
|
||||
|
||||
omap2_prm_write_mod_reg(vp->tranxdone_status,
|
||||
OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
||||
}
|
||||
|
||||
u32 omap3_prm_vcvp_read(u8 offset)
|
||||
{
|
||||
return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
|
||||
}
|
||||
|
||||
void omap3_prm_vcvp_write(u32 val, u8 offset)
|
||||
{
|
||||
omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
|
||||
}
|
||||
|
||||
u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
|
||||
{
|
||||
return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
|
||||
}
|
||||
|
@ -303,7 +303,19 @@ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
|
||||
extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
|
||||
extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
|
||||
|
||||
/* OMAP3-specific VP functions */
|
||||
u32 omap3_prm_vp_check_txdone(u8 vp_id);
|
||||
void omap3_prm_vp_clear_txdone(u8 vp_id);
|
||||
|
||||
/*
|
||||
* OMAP3 access functions for voltage controller (VC) and
|
||||
* voltage proccessor (VP) in the PRM.
|
||||
*/
|
||||
extern u32 omap3_prm_vcvp_read(u8 offset);
|
||||
extern void omap3_prm_vcvp_write(u32 val, u8 offset);
|
||||
extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
|
||||
#endif /* CONFIG_ARCH_OMAP4 */
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
@ -21,8 +21,11 @@
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/prcm.h>
|
||||
|
||||
#include "vp.h"
|
||||
#include "prm44xx.h"
|
||||
#include "prm-regbits-44xx.h"
|
||||
#include "prcm44xx.h"
|
||||
#include "prminst44xx.h"
|
||||
|
||||
/* PRM low-level functions */
|
||||
|
||||
@ -50,3 +53,71 @@ u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
|
||||
|
||||
return v;
|
||||
}
|
||||
|
||||
/* PRM VP */
|
||||
|
||||
/*
|
||||
* struct omap4_vp - OMAP4 VP register access description.
|
||||
* @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
|
||||
* @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
|
||||
*/
|
||||
struct omap4_vp {
|
||||
u32 irqstatus_mpu;
|
||||
u32 tranxdone_status;
|
||||
};
|
||||
|
||||
static struct omap4_vp omap4_vp[] = {
|
||||
[OMAP4_VP_VDD_MPU_ID] = {
|
||||
.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
|
||||
.tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
|
||||
},
|
||||
[OMAP4_VP_VDD_IVA_ID] = {
|
||||
.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
|
||||
.tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
|
||||
},
|
||||
[OMAP4_VP_VDD_CORE_ID] = {
|
||||
.irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
|
||||
.tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
|
||||
},
|
||||
};
|
||||
|
||||
u32 omap4_prm_vp_check_txdone(u8 vp_id)
|
||||
{
|
||||
struct omap4_vp *vp = &omap4_vp[vp_id];
|
||||
u32 irqstatus;
|
||||
|
||||
irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
|
||||
OMAP4430_PRM_OCP_SOCKET_INST,
|
||||
vp->irqstatus_mpu);
|
||||
return irqstatus & vp->tranxdone_status;
|
||||
}
|
||||
|
||||
void omap4_prm_vp_clear_txdone(u8 vp_id)
|
||||
{
|
||||
struct omap4_vp *vp = &omap4_vp[vp_id];
|
||||
|
||||
omap4_prminst_write_inst_reg(vp->tranxdone_status,
|
||||
OMAP4430_PRM_PARTITION,
|
||||
OMAP4430_PRM_OCP_SOCKET_INST,
|
||||
vp->irqstatus_mpu);
|
||||
};
|
||||
|
||||
u32 omap4_prm_vcvp_read(u8 offset)
|
||||
{
|
||||
return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
|
||||
OMAP4430_PRM_DEVICE_INST, offset);
|
||||
}
|
||||
|
||||
void omap4_prm_vcvp_write(u32 val, u8 offset)
|
||||
{
|
||||
omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
|
||||
OMAP4430_PRM_DEVICE_INST, offset);
|
||||
}
|
||||
|
||||
u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
|
||||
{
|
||||
return omap4_prminst_rmw_inst_reg_bits(mask, bits,
|
||||
OMAP4430_PRM_PARTITION,
|
||||
OMAP4430_PRM_DEVICE_INST,
|
||||
offset);
|
||||
}
|
||||
|
@ -751,6 +751,18 @@ extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
|
||||
extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
|
||||
extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
|
||||
|
||||
/* OMAP4-specific VP functions */
|
||||
u32 omap4_prm_vp_check_txdone(u8 vp_id);
|
||||
void omap4_prm_vp_clear_txdone(u8 vp_id);
|
||||
|
||||
/*
|
||||
* OMAP4 access functions for voltage controller (VC) and
|
||||
* voltage proccessor (VP) in the PRM.
|
||||
*/
|
||||
extern u32 omap4_prm_vcvp_read(u8 offset);
|
||||
extern void omap4_prm_vcvp_write(u32 val, u8 offset);
|
||||
extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
|
||||
|
||||
# endif
|
||||
|
||||
#endif
|
||||
|
@ -107,28 +107,6 @@ struct omap_uart_state {
|
||||
static LIST_HEAD(uart_list);
|
||||
static u8 num_uarts;
|
||||
|
||||
static int uart_idle_hwmod(struct omap_device *od)
|
||||
{
|
||||
omap_hwmod_idle(od->hwmods[0]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int uart_enable_hwmod(struct omap_device *od)
|
||||
{
|
||||
omap_hwmod_enable(od->hwmods[0]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct omap_device_pm_latency omap_uart_latency[] = {
|
||||
{
|
||||
.deactivate_func = uart_idle_hwmod,
|
||||
.activate_func = uart_enable_hwmod,
|
||||
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
|
||||
},
|
||||
};
|
||||
|
||||
static inline unsigned int __serial_read_reg(struct uart_port *up,
|
||||
int offset)
|
||||
{
|
||||
@ -711,7 +689,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
|
||||
{
|
||||
struct omap_uart_state *uart;
|
||||
struct omap_hwmod *oh;
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
void *pdata = NULL;
|
||||
u32 pdata_size = 0;
|
||||
char *name;
|
||||
@ -799,20 +777,19 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
|
||||
if (WARN_ON(!oh))
|
||||
return;
|
||||
|
||||
od = omap_device_build(name, uart->num, oh, pdata, pdata_size,
|
||||
omap_uart_latency,
|
||||
ARRAY_SIZE(omap_uart_latency), false);
|
||||
WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
|
||||
pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
|
||||
NULL, 0, false);
|
||||
WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
|
||||
name, oh->name);
|
||||
|
||||
omap_device_disable_idle_on_suspend(od);
|
||||
omap_device_disable_idle_on_suspend(pdev);
|
||||
oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
|
||||
|
||||
uart->irq = oh->mpu_irqs[0].irq;
|
||||
uart->regshift = 2;
|
||||
uart->mapbase = oh->slaves[0]->addr->pa_start;
|
||||
uart->membase = omap_hwmod_get_mpu_rt_va(oh);
|
||||
uart->pdev = &od->pdev;
|
||||
uart->pdev = pdev;
|
||||
|
||||
oh->dev_attr = uart;
|
||||
|
||||
@ -846,8 +823,8 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
|
||||
|
||||
if ((cpu_is_omap34xx() && uart->padconf) ||
|
||||
(uart->wk_en && uart->wk_mask)) {
|
||||
device_init_wakeup(&od->pdev.dev, true);
|
||||
DEV_CREATE_FILE(&od->pdev.dev, &dev_attr_sleep_timeout);
|
||||
device_init_wakeup(&pdev->dev, true);
|
||||
DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout);
|
||||
}
|
||||
|
||||
/* Enable the MDR1 errata for OMAP3 */
|
||||
|
@ -15,7 +15,7 @@
|
||||
|
||||
static int sr_class3_enable(struct voltagedomain *voltdm)
|
||||
{
|
||||
unsigned long volt = omap_voltage_get_nom_volt(voltdm);
|
||||
unsigned long volt = voltdm_get_voltage(voltdm);
|
||||
|
||||
if (!volt) {
|
||||
pr_warning("%s: Curr voltage unknown. Cannot enable sr_%s\n",
|
||||
@ -32,7 +32,7 @@ static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
|
||||
omap_vp_disable(voltdm);
|
||||
sr_disable(voltdm);
|
||||
if (is_volt_reset)
|
||||
omap_voltage_reset(voltdm);
|
||||
voltdm_reset(voltdm);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -62,6 +62,7 @@ static LIST_HEAD(sr_list);
|
||||
|
||||
static struct omap_sr_class_data *sr_class;
|
||||
static struct omap_sr_pmic_data *sr_pmic_data;
|
||||
static struct dentry *sr_dbg_dir;
|
||||
|
||||
static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
|
||||
{
|
||||
@ -826,9 +827,10 @@ static int __init omap_sr_probe(struct platform_device *pdev)
|
||||
struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
|
||||
struct omap_sr_data *pdata = pdev->dev.platform_data;
|
||||
struct resource *mem, *irq;
|
||||
struct dentry *vdd_dbg_dir, *nvalue_dir;
|
||||
struct dentry *nvalue_dir;
|
||||
struct omap_volt_data *volt_data;
|
||||
int i, ret = 0;
|
||||
char *name;
|
||||
|
||||
if (!sr_info) {
|
||||
dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
|
||||
@ -899,18 +901,25 @@ static int __init omap_sr_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
|
||||
|
||||
/*
|
||||
* If the voltage domain debugfs directory is not created, do
|
||||
* not try to create rest of the debugfs entries.
|
||||
*/
|
||||
vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm);
|
||||
if (!vdd_dbg_dir) {
|
||||
ret = -EINVAL;
|
||||
goto err_iounmap;
|
||||
if (!sr_dbg_dir) {
|
||||
sr_dbg_dir = debugfs_create_dir("smartreflex", NULL);
|
||||
if (!sr_dbg_dir) {
|
||||
ret = PTR_ERR(sr_dbg_dir);
|
||||
pr_err("%s:sr debugfs dir creation failed(%d)\n",
|
||||
__func__, ret);
|
||||
goto err_iounmap;
|
||||
}
|
||||
}
|
||||
|
||||
sr_info->dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
|
||||
name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
|
||||
if (!name) {
|
||||
dev_err(&pdev->dev, "%s: Unable to alloc debugfs name\n",
|
||||
__func__);
|
||||
ret = -ENOMEM;
|
||||
goto err_iounmap;
|
||||
}
|
||||
sr_info->dbg_dir = debugfs_create_dir(name, sr_dbg_dir);
|
||||
kfree(name);
|
||||
if (IS_ERR(sr_info->dbg_dir)) {
|
||||
dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
|
||||
__func__);
|
||||
|
@ -31,14 +31,6 @@
|
||||
|
||||
static bool sr_enable_on_init;
|
||||
|
||||
static struct omap_device_pm_latency omap_sr_latency[] = {
|
||||
{
|
||||
.deactivate_func = omap_device_idle_hwmods,
|
||||
.activate_func = omap_device_enable_hwmods,
|
||||
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST
|
||||
},
|
||||
};
|
||||
|
||||
/* Read EFUSE values from control registers for OMAP3430 */
|
||||
static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
|
||||
struct omap_sr_data *sr_data)
|
||||
@ -80,7 +72,7 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
|
||||
static int sr_dev_init(struct omap_hwmod *oh, void *user)
|
||||
{
|
||||
struct omap_sr_data *sr_data;
|
||||
struct omap_device *od;
|
||||
struct platform_device *pdev;
|
||||
struct omap_volt_data *volt_data;
|
||||
char *name = "smartreflex";
|
||||
static int i;
|
||||
@ -102,7 +94,7 @@ static int sr_dev_init(struct omap_hwmod *oh, void *user)
|
||||
sr_data->senn_mod = 0x1;
|
||||
sr_data->senp_mod = 0x1;
|
||||
|
||||
sr_data->voltdm = omap_voltage_domain_lookup(oh->vdd_name);
|
||||
sr_data->voltdm = voltdm_lookup(oh->vdd_name);
|
||||
if (IS_ERR(sr_data->voltdm)) {
|
||||
pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
|
||||
__func__, oh->vdd_name);
|
||||
@ -120,10 +112,9 @@ static int sr_dev_init(struct omap_hwmod *oh, void *user)
|
||||
|
||||
sr_data->enable_on_init = sr_enable_on_init;
|
||||
|
||||
od = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data),
|
||||
omap_sr_latency,
|
||||
ARRAY_SIZE(omap_sr_latency), 0);
|
||||
if (IS_ERR(od))
|
||||
pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data),
|
||||
NULL, 0, 0);
|
||||
if (IS_ERR(pdev))
|
||||
pr_warning("%s: Could not build omap_device for %s: %s.\n\n",
|
||||
__func__, name, oh->name);
|
||||
exit:
|
||||
|
@ -35,6 +35,7 @@
|
||||
#include <linux/irq.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <asm/mach/time.h>
|
||||
#include <plat/dmtimer.h>
|
||||
@ -42,6 +43,10 @@
|
||||
#include <asm/sched_clock.h>
|
||||
#include <plat/common.h>
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/omap_device.h>
|
||||
#include <plat/omap-pm.h>
|
||||
|
||||
#include "powerdomain.h"
|
||||
|
||||
/* Parent clocks, eventually these will come from the clock framework */
|
||||
|
||||
@ -67,7 +72,7 @@
|
||||
/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
|
||||
#define MAX_GPTIMER_ID 12
|
||||
|
||||
u32 sys_timer_reserved;
|
||||
static u32 sys_timer_reserved;
|
||||
|
||||
/* Clockevent code */
|
||||
|
||||
@ -78,7 +83,7 @@ static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *evt = &clockevent_gpt;
|
||||
|
||||
__omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
|
||||
__omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
|
||||
|
||||
evt->event_handler(evt);
|
||||
return IRQ_HANDLED;
|
||||
@ -93,7 +98,7 @@ static struct irqaction omap2_gp_timer_irq = {
|
||||
static int omap2_gp_timer_set_next_event(unsigned long cycles,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
__omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
|
||||
__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
|
||||
0xffffffff - cycles, 1);
|
||||
|
||||
return 0;
|
||||
@ -104,16 +109,16 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
|
||||
{
|
||||
u32 period;
|
||||
|
||||
__omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
|
||||
__omap_dm_timer_stop(&clkev, 1, clkev.rate);
|
||||
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
period = clkev.rate / HZ;
|
||||
period -= 1;
|
||||
/* Looks like we need to first set the load value separately */
|
||||
__omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
|
||||
__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
|
||||
0xffffffff - period, 1);
|
||||
__omap_dm_timer_load_start(clkev.io_base,
|
||||
__omap_dm_timer_load_start(&clkev,
|
||||
OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
|
||||
0xffffffff - period, 1);
|
||||
break;
|
||||
@ -189,7 +194,8 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
|
||||
clk_put(src);
|
||||
}
|
||||
}
|
||||
__omap_dm_timer_reset(timer->io_base, 1, 1);
|
||||
__omap_dm_timer_init_regs(timer);
|
||||
__omap_dm_timer_reset(timer, 1, 1);
|
||||
timer->posted = 1;
|
||||
|
||||
timer->rate = clk_get_rate(timer->fclk);
|
||||
@ -210,7 +216,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
|
||||
omap2_gp_timer_irq.dev_id = (void *)&clkev;
|
||||
setup_irq(clkev.irq, &omap2_gp_timer_irq);
|
||||
|
||||
__omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
|
||||
__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
|
||||
|
||||
clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
|
||||
clockevent_gpt.shift);
|
||||
@ -251,7 +257,7 @@ static struct omap_dm_timer clksrc;
|
||||
static DEFINE_CLOCK_DATA(cd);
|
||||
static cycle_t clocksource_read_cycles(struct clocksource *cs)
|
||||
{
|
||||
return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1);
|
||||
return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
|
||||
}
|
||||
|
||||
static struct clocksource clocksource_gpt = {
|
||||
@ -266,7 +272,7 @@ static void notrace dmtimer_update_sched_clock(void)
|
||||
{
|
||||
u32 cyc;
|
||||
|
||||
cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
|
||||
cyc = __omap_dm_timer_read_counter(&clksrc, 1);
|
||||
|
||||
update_sched_clock(&cd, cyc, (u32)~0);
|
||||
}
|
||||
@ -276,7 +282,7 @@ unsigned long long notrace sched_clock(void)
|
||||
u32 cyc = 0;
|
||||
|
||||
if (clksrc.reserved)
|
||||
cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
|
||||
cyc = __omap_dm_timer_read_counter(&clksrc, 1);
|
||||
|
||||
return cyc_to_sched_clock(&cd, cyc, (u32)~0);
|
||||
}
|
||||
@ -293,7 +299,7 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
|
||||
pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
|
||||
gptimer_id, clksrc.rate);
|
||||
|
||||
__omap_dm_timer_load_start(clksrc.io_base,
|
||||
__omap_dm_timer_load_start(&clksrc,
|
||||
OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
|
||||
init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
|
||||
|
||||
@ -341,3 +347,167 @@ static void __init omap4_timer_init(void)
|
||||
}
|
||||
OMAP_SYS_TIMER(4)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* omap2_dm_timer_set_src - change the timer input clock source
|
||||
* @pdev: timer platform device pointer
|
||||
* @source: array index of parent clock source
|
||||
*/
|
||||
static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
|
||||
{
|
||||
int ret;
|
||||
struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
|
||||
struct clk *fclk, *parent;
|
||||
char *parent_name = NULL;
|
||||
|
||||
fclk = clk_get(&pdev->dev, "fck");
|
||||
if (IS_ERR_OR_NULL(fclk)) {
|
||||
dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
|
||||
__func__, __LINE__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (source) {
|
||||
case OMAP_TIMER_SRC_SYS_CLK:
|
||||
parent_name = "sys_ck";
|
||||
break;
|
||||
|
||||
case OMAP_TIMER_SRC_32_KHZ:
|
||||
parent_name = "32k_ck";
|
||||
break;
|
||||
|
||||
case OMAP_TIMER_SRC_EXT_CLK:
|
||||
if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
|
||||
parent_name = "alt_ck";
|
||||
break;
|
||||
}
|
||||
dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
|
||||
__func__, __LINE__);
|
||||
clk_put(fclk);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
parent = clk_get(&pdev->dev, parent_name);
|
||||
if (IS_ERR_OR_NULL(parent)) {
|
||||
dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
|
||||
__func__, __LINE__, parent_name);
|
||||
clk_put(fclk);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = clk_set_parent(fclk, parent);
|
||||
if (IS_ERR_VALUE(ret)) {
|
||||
dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
|
||||
__func__, parent_name);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
clk_put(parent);
|
||||
clk_put(fclk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct omap_device_pm_latency omap2_dmtimer_latency[] = {
|
||||
{
|
||||
.deactivate_func = omap_device_idle_hwmods,
|
||||
.activate_func = omap_device_enable_hwmods,
|
||||
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
|
||||
},
|
||||
};
|
||||
|
||||
/**
|
||||
* omap_timer_init - build and register timer device with an
|
||||
* associated timer hwmod
|
||||
* @oh: timer hwmod pointer to be used to build timer device
|
||||
* @user: parameter that can be passed from calling hwmod API
|
||||
*
|
||||
* Called by omap_hwmod_for_each_by_class to register each of the timer
|
||||
* devices present in the system. The number of timer devices is known
|
||||
* by parsing through the hwmod database for a given class name. At the
|
||||
* end of function call memory is allocated for timer device and it is
|
||||
* registered to the framework ready to be proved by the driver.
|
||||
*/
|
||||
static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
|
||||
{
|
||||
int id;
|
||||
int ret = 0;
|
||||
char *name = "omap_timer";
|
||||
struct dmtimer_platform_data *pdata;
|
||||
struct platform_device *pdev;
|
||||
struct omap_timer_capability_dev_attr *timer_dev_attr;
|
||||
struct powerdomain *pwrdm;
|
||||
|
||||
pr_debug("%s: %s\n", __func__, oh->name);
|
||||
|
||||
/* on secure device, do not register secure timer */
|
||||
timer_dev_attr = oh->dev_attr;
|
||||
if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
|
||||
if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
|
||||
return ret;
|
||||
|
||||
pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
|
||||
if (!pdata) {
|
||||
pr_err("%s: No memory for [%s]\n", __func__, oh->name);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/*
|
||||
* Extract the IDs from name field in hwmod database
|
||||
* and use the same for constructing ids' for the
|
||||
* timer devices. In a way, we are avoiding usage of
|
||||
* static variable witin the function to do the same.
|
||||
* CAUTION: We have to be careful and make sure the
|
||||
* name in hwmod database does not change in which case
|
||||
* we might either make corresponding change here or
|
||||
* switch back static variable mechanism.
|
||||
*/
|
||||
sscanf(oh->name, "timer%2d", &id);
|
||||
|
||||
pdata->set_timer_src = omap2_dm_timer_set_src;
|
||||
pdata->timer_ip_version = oh->class->rev;
|
||||
|
||||
/* Mark clocksource and clockevent timers as reserved */
|
||||
if ((sys_timer_reserved >> (id - 1)) & 0x1)
|
||||
pdata->reserved = 1;
|
||||
|
||||
pwrdm = omap_hwmod_get_pwrdm(oh);
|
||||
pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
|
||||
#ifdef CONFIG_PM
|
||||
pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
|
||||
#endif
|
||||
pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
|
||||
omap2_dmtimer_latency,
|
||||
ARRAY_SIZE(omap2_dmtimer_latency),
|
||||
0);
|
||||
|
||||
if (IS_ERR(pdev)) {
|
||||
pr_err("%s: Can't build omap_device for %s: %s.\n",
|
||||
__func__, name, oh->name);
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
kfree(pdata);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* omap2_dm_timer_init - top level regular device initialization
|
||||
*
|
||||
* Uses dedicated hwmod api to parse through hwmod database for
|
||||
* given class name and then build and register the timer device.
|
||||
*/
|
||||
static int __init omap2_dm_timer_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
|
||||
if (unlikely(ret)) {
|
||||
pr_err("%s: device registration failed.\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(omap2_dm_timer_init);
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user