forked from luck/tmp_suning_uos_patched
Fourth batch of cleanup for 4.1:
- 1 issues revealed by the kbuild test robot fixed - move of some functions and macros into relevant files to be able to streamline the at91 specific header afterwards -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJVIZVaAAoJEAf03oE53VmQxIgH/09GE+V7GQODUcfMk2wV4RVB c8H7wWmtIt7KAmoAYs/SYhVlxT7phmjL4PGsO0bS6HGaQMzUZyZjeVPuVVUVkvC+ nn1Y//2YFF5sGIAV0NtFs1h8T/yOCEe0PCXnmFbGMuvvIacYQ5BxaO5/IzNPD6JV k2LNzLtAiCtgOGZari0flVr1bVXilBCqq5gDc94Z0x3NphDzLwq713LmwBFfbt7K +D8L06IA9SbOM/9S4a/XmDoRf4Mm7lSmLz78hkMzedo75h2Y4UNcywSJT9Oq9o6d nfCm4YxNtURVIFz+hZ7AzwIJJ+9T6a0qEuWMTiOeXSxgd4r4mnmAG+q92OJsJMY= =vb0O -----END PGP SIGNATURE----- Merge tag 'at91-cleanup4_bis' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/multiplatform Pull "Fourth batch of cleanup for 4.1" from Nicolas Ferre: - 1 issues revealed by the kbuild test robot fixed - move of some functions and macros into relevant files to be able to streamline the at91 specific header afterwards * tag 'at91-cleanup4_bis' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: ARM: at91/pm: move AT91_MEMCTRL_* to pm.h ARM: at91/pm: move the standby functions to pm.c ARM: at91: fix pm_suspend.S compilation when ARMv6 is selected
This commit is contained in:
Arnd Bergmann
commit
89522f0f8b
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@ -17,6 +17,9 @@ obj-$(CONFIG_SOC_SAMA5) += sama5.o
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obj-$(CONFIG_PM) += pm.o
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obj-$(CONFIG_PM) += pm_suspend.o
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ifeq ($(CONFIG_CPU_V7),y)
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AFLAGS_pm_suspend.o := -march=armv7-a
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endif
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ifeq ($(CONFIG_PM_DEBUG),y)
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CFLAGS_pm.o += -DDEBUG
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endif
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@ -21,10 +21,6 @@ extern void __iomem *at91_ramc_base[];
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.extern at91_ramc_base
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#endif
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#define AT91_MEMCTRL_MC 0
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#define AT91_MEMCTRL_SDRAMC 1
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#define AT91_MEMCTRL_DDRSDR 2
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#include <soc/at91/at91rm9200_sdramc.h>
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#include <soc/at91/at91sam9_ddrsdr.h>
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#include <soc/at91/at91sam9_sdramc.h>
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@ -222,6 +222,95 @@ static void at91_pm_set_standby(void (*at91_standby)(void))
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at91_cpuidle_device.dev.platform_data = at91_standby;
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}
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/*
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* The AT91RM9200 goes into self-refresh mode with this command, and will
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* terminate self-refresh automatically on the next SDRAM access.
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*
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* Self-refresh mode is exited as soon as a memory access is made, but we don't
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* know for sure when that happens. However, we need to restore the low-power
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* mode if it was enabled before going idle. Restoring low-power mode while
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* still in self-refresh is "not recommended", but seems to work.
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*/
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static void at91rm9200_standby(void)
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{
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u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
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asm volatile(
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"b 1f\n\t"
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".align 5\n\t"
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"1: mcr p15, 0, %0, c7, c10, 4\n\t"
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" str %0, [%1, %2]\n\t"
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" str %3, [%1, %4]\n\t"
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" mcr p15, 0, %0, c7, c0, 4\n\t"
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" str %5, [%1, %2]"
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:
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: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
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"r" (1), "r" (AT91RM9200_SDRAMC_SRR),
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"r" (lpr));
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}
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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* remember.
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*/
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static void at91_ddr_standby(void)
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{
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/* Those two values allow us to delay self-refresh activation
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* to the maximum. */
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u32 lpr0, lpr1 = 0;
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u32 saved_lpr0, saved_lpr1 = 0;
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if (at91_ramc_base[1]) {
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saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
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lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
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lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
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}
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saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
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lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
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lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
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/* self-refresh mode now */
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at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
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if (at91_ramc_base[1])
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at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
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cpu_do_idle();
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at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
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if (at91_ramc_base[1])
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at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
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}
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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* remember.
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*/
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static void at91sam9_sdram_standby(void)
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{
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u32 lpr0, lpr1 = 0;
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u32 saved_lpr0, saved_lpr1 = 0;
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if (at91_ramc_base[1]) {
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saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
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lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
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lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
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}
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saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
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lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
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lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
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/* self-refresh mode now */
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at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
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if (at91_ramc_base[1])
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at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
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cpu_do_idle();
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at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
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if (at91_ramc_base[1])
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at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
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}
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static const struct of_device_id ramc_ids[] __initconst = {
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{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
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{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
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@ -15,6 +15,10 @@
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#include <mach/at91_ramc.h>
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#define AT91_MEMCTRL_MC 0
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#define AT91_MEMCTRL_SDRAMC 1
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#define AT91_MEMCTRL_DDRSDR 2
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#define AT91_PM_MEMTYPE_MASK 0x0f
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#define AT91_PM_MODE_OFFSET 4
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@ -23,96 +27,4 @@
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#define AT91_PM_SLOW_CLOCK 0x01
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/*
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* The AT91RM9200 goes into self-refresh mode with this command, and will
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* terminate self-refresh automatically on the next SDRAM access.
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*
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* Self-refresh mode is exited as soon as a memory access is made, but we don't
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* know for sure when that happens. However, we need to restore the low-power
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* mode if it was enabled before going idle. Restoring low-power mode while
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* still in self-refresh is "not recommended", but seems to work.
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*/
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#ifndef __ASSEMBLY__
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static inline void at91rm9200_standby(void)
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{
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u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
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asm volatile(
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"b 1f\n\t"
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".align 5\n\t"
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"1: mcr p15, 0, %0, c7, c10, 4\n\t"
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" str %0, [%1, %2]\n\t"
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" str %3, [%1, %4]\n\t"
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" mcr p15, 0, %0, c7, c0, 4\n\t"
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" str %5, [%1, %2]"
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:
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: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
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"r" (1), "r" (AT91RM9200_SDRAMC_SRR),
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"r" (lpr));
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}
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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* remember.
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*/
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static inline void at91_ddr_standby(void)
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{
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/* Those two values allow us to delay self-refresh activation
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* to the maximum. */
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u32 lpr0, lpr1 = 0;
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u32 saved_lpr0, saved_lpr1 = 0;
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if (at91_ramc_base[1]) {
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saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
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lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
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lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
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}
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saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
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lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
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lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
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/* self-refresh mode now */
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at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
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if (at91_ramc_base[1])
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at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
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cpu_do_idle();
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at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
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if (at91_ramc_base[1])
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at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
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}
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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* remember.
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*/
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static inline void at91sam9_sdram_standby(void)
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{
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u32 lpr0, lpr1 = 0;
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u32 saved_lpr0, saved_lpr1 = 0;
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if (at91_ramc_base[1]) {
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saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
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lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
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lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
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}
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saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
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lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
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lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
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/* self-refresh mode now */
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at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
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if (at91_ramc_base[1])
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at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
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cpu_do_idle();
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at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
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if (at91_ramc_base[1])
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at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
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}
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#endif
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#endif
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