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clk: tegra30: Don't wait for PLL_U lock bit

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The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Tuomas Tynkkynen 2013-08-28 18:18:47 +03:00 committed by Mike Turquette
parent 5b0dde99e8
commit 89ac8567b9
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/tegra/clk-tegra30.c
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@ -971,7 +971,7 @@ static void __init tegra30_pll_init(void)
/* PLLU */ /* PLLU */
clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0, clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON |
TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, TEGRA_PLL_SET_LFCON,
pll_u_freq_table, pll_u_freq_table,
NULL); NULL);
clk_register_clkdev(clk, "pll_u", NULL); clk_register_clkdev(clk, "pll_u", NULL);