forked from luck/tmp_suning_uos_patched
ARM: OMAP1: Move plat/irqs.h to mach/irqs.h
This is now omap1 specific files. Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
parent
ec2c0825ca
commit
8afc5e088e
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@ -18,6 +18,7 @@
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#include <plat/board-ams-delta.h>
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#include <mach/irqs.h>
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#include <mach/ams-delta-fiq.h>
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#include "iomap.h"
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@ -27,7 +27,8 @@
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#include <plat/dma.h>
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#include <plat/tc.h>
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#include <plat/irqs.h>
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#include <mach/irqs.h>
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#define OMAP1_DMA_BASE (0xfffed800)
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#define OMAP1_LOGICAL_DMA_CH_COUNT 17
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@ -14,8 +14,6 @@
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#ifndef __AMS_DELTA_FIQ_H
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#define __AMS_DELTA_FIQ_H
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#include <plat/irqs.h>
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/*
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* Interrupt number used for passing control from FIQ to IRQ.
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* IRQ12, described as reserved, has been selected.
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@ -1,5 +1,268 @@
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/*
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* arch/arm/mach-omap1/include/mach/irqs.h
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* arch/arm/plat-omap/include/mach/irqs.h
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*
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* Copyright (C) Greg Lonnon 2001
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* Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
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*
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
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* are different.
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*/
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#include <plat/irqs.h>
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#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
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#define __ASM_ARCH_OMAP15XX_IRQS_H
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/*
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* IRQ numbers for interrupt handler 1
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*
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* NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
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*
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*/
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#define INT_CAMERA 1
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#define INT_FIQ 3
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#define INT_RTDX 6
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#define INT_DSP_MMU_ABORT 7
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#define INT_HOST 8
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#define INT_ABORT 9
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#define INT_BRIDGE_PRIV 13
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#define INT_GPIO_BANK1 14
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#define INT_UART3 15
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#define INT_TIMER3 16
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#define INT_DMA_CH0_6 19
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#define INT_DMA_CH1_7 20
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#define INT_DMA_CH2_8 21
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#define INT_DMA_CH3 22
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#define INT_DMA_CH4 23
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#define INT_DMA_CH5 24
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#define INT_TIMER1 26
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#define INT_WD_TIMER 27
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#define INT_BRIDGE_PUB 28
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#define INT_TIMER2 30
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#define INT_LCD_CTRL 31
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/*
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* OMAP-1510 specific IRQ numbers for interrupt handler 1
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*/
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#define INT_1510_IH2_IRQ 0
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#define INT_1510_RES2 2
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#define INT_1510_SPI_TX 4
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#define INT_1510_SPI_RX 5
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#define INT_1510_DSP_MAILBOX1 10
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#define INT_1510_DSP_MAILBOX2 11
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#define INT_1510_RES12 12
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#define INT_1510_LB_MMU 17
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#define INT_1510_RES18 18
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#define INT_1510_LOCAL_BUS 29
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/*
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* OMAP-1610 specific IRQ numbers for interrupt handler 1
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*/
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#define INT_1610_IH2_IRQ INT_1510_IH2_IRQ
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#define INT_1610_IH2_FIQ 2
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#define INT_1610_McBSP2_TX 4
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#define INT_1610_McBSP2_RX 5
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#define INT_1610_DSP_MAILBOX1 10
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#define INT_1610_DSP_MAILBOX2 11
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#define INT_1610_LCD_LINE 12
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#define INT_1610_GPTIMER1 17
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#define INT_1610_GPTIMER2 18
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#define INT_1610_SSR_FIFO_0 29
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/*
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* OMAP-7xx specific IRQ numbers for interrupt handler 1
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*/
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#define INT_7XX_IH2_FIQ 0
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#define INT_7XX_IH2_IRQ 1
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#define INT_7XX_USB_NON_ISO 2
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#define INT_7XX_USB_ISO 3
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#define INT_7XX_ICR 4
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#define INT_7XX_EAC 5
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#define INT_7XX_GPIO_BANK1 6
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#define INT_7XX_GPIO_BANK2 7
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#define INT_7XX_GPIO_BANK3 8
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#define INT_7XX_McBSP2TX 10
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#define INT_7XX_McBSP2RX 11
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#define INT_7XX_McBSP2RX_OVF 12
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#define INT_7XX_LCD_LINE 14
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#define INT_7XX_GSM_PROTECT 15
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#define INT_7XX_TIMER3 16
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#define INT_7XX_GPIO_BANK5 17
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#define INT_7XX_GPIO_BANK6 18
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#define INT_7XX_SPGIO_WR 29
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/*
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* IRQ numbers for interrupt handler 2
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*
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* NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
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*/
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#define IH2_BASE 32
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#define INT_KEYBOARD (1 + IH2_BASE)
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#define INT_uWireTX (2 + IH2_BASE)
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#define INT_uWireRX (3 + IH2_BASE)
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#define INT_I2C (4 + IH2_BASE)
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#define INT_MPUIO (5 + IH2_BASE)
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#define INT_USB_HHC_1 (6 + IH2_BASE)
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#define INT_McBSP3TX (10 + IH2_BASE)
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#define INT_McBSP3RX (11 + IH2_BASE)
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#define INT_McBSP1TX (12 + IH2_BASE)
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#define INT_McBSP1RX (13 + IH2_BASE)
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#define INT_UART1 (14 + IH2_BASE)
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#define INT_UART2 (15 + IH2_BASE)
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#define INT_BT_MCSI1TX (16 + IH2_BASE)
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#define INT_BT_MCSI1RX (17 + IH2_BASE)
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#define INT_SOSSI_MATCH (19 + IH2_BASE)
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#define INT_USB_W2FC (20 + IH2_BASE)
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#define INT_1WIRE (21 + IH2_BASE)
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#define INT_OS_TIMER (22 + IH2_BASE)
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#define INT_MMC (23 + IH2_BASE)
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#define INT_GAUGE_32K (24 + IH2_BASE)
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#define INT_RTC_TIMER (25 + IH2_BASE)
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#define INT_RTC_ALARM (26 + IH2_BASE)
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#define INT_MEM_STICK (27 + IH2_BASE)
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/*
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* OMAP-1510 specific IRQ numbers for interrupt handler 2
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*/
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#define INT_1510_DSP_MMU (28 + IH2_BASE)
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#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
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/*
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* OMAP-1610 specific IRQ numbers for interrupt handler 2
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*/
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#define INT_1610_FAC (0 + IH2_BASE)
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#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
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#define INT_1610_USB_OTG (8 + IH2_BASE)
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#define INT_1610_SoSSI (9 + IH2_BASE)
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#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
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#define INT_1610_DSP_MMU (28 + IH2_BASE)
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#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
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#define INT_1610_STI (32 + IH2_BASE)
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#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
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#define INT_1610_GPTIMER3 (34 + IH2_BASE)
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#define INT_1610_GPTIMER4 (35 + IH2_BASE)
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#define INT_1610_GPTIMER5 (36 + IH2_BASE)
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#define INT_1610_GPTIMER6 (37 + IH2_BASE)
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#define INT_1610_GPTIMER7 (38 + IH2_BASE)
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#define INT_1610_GPTIMER8 (39 + IH2_BASE)
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#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
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#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
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#define INT_1610_MMC2 (42 + IH2_BASE)
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#define INT_1610_CF (43 + IH2_BASE)
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#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
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#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
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#define INT_1610_SPI (49 + IH2_BASE)
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#define INT_1610_DMA_CH6 (53 + IH2_BASE)
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#define INT_1610_DMA_CH7 (54 + IH2_BASE)
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#define INT_1610_DMA_CH8 (55 + IH2_BASE)
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#define INT_1610_DMA_CH9 (56 + IH2_BASE)
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#define INT_1610_DMA_CH10 (57 + IH2_BASE)
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#define INT_1610_DMA_CH11 (58 + IH2_BASE)
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#define INT_1610_DMA_CH12 (59 + IH2_BASE)
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#define INT_1610_DMA_CH13 (60 + IH2_BASE)
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#define INT_1610_DMA_CH14 (61 + IH2_BASE)
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#define INT_1610_DMA_CH15 (62 + IH2_BASE)
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#define INT_1610_NAND (63 + IH2_BASE)
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#define INT_1610_SHA1MD5 (91 + IH2_BASE)
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/*
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* OMAP-7xx specific IRQ numbers for interrupt handler 2
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*/
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#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
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#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
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#define INT_7XX_CFCD (2 + IH2_BASE)
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#define INT_7XX_CFIREQ (3 + IH2_BASE)
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#define INT_7XX_I2C (4 + IH2_BASE)
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#define INT_7XX_PCC (5 + IH2_BASE)
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#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
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#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
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#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
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#define INT_7XX_VLYNQ (9 + IH2_BASE)
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#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
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#define INT_7XX_McBSP1TX (11 + IH2_BASE)
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#define INT_7XX_McBSP1RX (12 + IH2_BASE)
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#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
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#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
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#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
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#define INT_7XX_MCSI (16 + IH2_BASE)
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#define INT_7XX_uWireTX (17 + IH2_BASE)
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#define INT_7XX_uWireRX (18 + IH2_BASE)
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#define INT_7XX_SMC_CD (19 + IH2_BASE)
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#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
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#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
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#define INT_7XX_TIMER32K (22 + IH2_BASE)
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#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
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#define INT_7XX_UPLD (24 + IH2_BASE)
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#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
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#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
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#define INT_7XX_USB_GENI (29 + IH2_BASE)
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#define INT_7XX_USB_OTG (30 + IH2_BASE)
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#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
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#define INT_7XX_RNG (32 + IH2_BASE)
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#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
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#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
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#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
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#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
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#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
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#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
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#define INT_7XX_MPUIO (39 + IH2_BASE)
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#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
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#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
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#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
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#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
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#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
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#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
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#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
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#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
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#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
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#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
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#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
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#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
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#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
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#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
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#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
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#define INT_7XX_NAND (63 + IH2_BASE)
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/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
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* 16 MPUIO lines */
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#define OMAP_MAX_GPIO_LINES 192
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#define IH_GPIO_BASE (128 + IH2_BASE)
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#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
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#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
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/* External FPGA handles interrupts on Innovator boards */
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#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
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#ifdef CONFIG_MACH_OMAP_INNOVATOR
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#define OMAP_FPGA_NR_IRQS 24
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#else
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#define OMAP_FPGA_NR_IRQS 0
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#endif
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#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
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#define NR_IRQS OMAP_FPGA_IRQ_END
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#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
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#include <mach/hardware.h>
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#ifdef CONFIG_FIQ
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#define FIQ_START 1024
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#endif
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#endif
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@ -1,268 +0,0 @@
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/*
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* arch/arm/plat-omap/include/mach/irqs.h
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*
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* Copyright (C) Greg Lonnon 2001
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* Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
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*
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
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||||
* NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
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* are different.
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*/
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#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
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#define __ASM_ARCH_OMAP15XX_IRQS_H
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/*
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* IRQ numbers for interrupt handler 1
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*
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* NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
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*
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*/
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#define INT_CAMERA 1
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#define INT_FIQ 3
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#define INT_RTDX 6
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#define INT_DSP_MMU_ABORT 7
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#define INT_HOST 8
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#define INT_ABORT 9
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#define INT_BRIDGE_PRIV 13
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#define INT_GPIO_BANK1 14
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#define INT_UART3 15
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#define INT_TIMER3 16
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#define INT_DMA_CH0_6 19
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#define INT_DMA_CH1_7 20
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#define INT_DMA_CH2_8 21
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#define INT_DMA_CH3 22
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#define INT_DMA_CH4 23
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#define INT_DMA_CH5 24
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#define INT_TIMER1 26
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#define INT_WD_TIMER 27
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#define INT_BRIDGE_PUB 28
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#define INT_TIMER2 30
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#define INT_LCD_CTRL 31
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/*
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* OMAP-1510 specific IRQ numbers for interrupt handler 1
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*/
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#define INT_1510_IH2_IRQ 0
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#define INT_1510_RES2 2
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#define INT_1510_SPI_TX 4
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#define INT_1510_SPI_RX 5
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#define INT_1510_DSP_MAILBOX1 10
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#define INT_1510_DSP_MAILBOX2 11
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#define INT_1510_RES12 12
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#define INT_1510_LB_MMU 17
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#define INT_1510_RES18 18
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#define INT_1510_LOCAL_BUS 29
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/*
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* OMAP-1610 specific IRQ numbers for interrupt handler 1
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*/
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#define INT_1610_IH2_IRQ INT_1510_IH2_IRQ
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#define INT_1610_IH2_FIQ 2
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#define INT_1610_McBSP2_TX 4
|
||||
#define INT_1610_McBSP2_RX 5
|
||||
#define INT_1610_DSP_MAILBOX1 10
|
||||
#define INT_1610_DSP_MAILBOX2 11
|
||||
#define INT_1610_LCD_LINE 12
|
||||
#define INT_1610_GPTIMER1 17
|
||||
#define INT_1610_GPTIMER2 18
|
||||
#define INT_1610_SSR_FIFO_0 29
|
||||
|
||||
/*
|
||||
* OMAP-7xx specific IRQ numbers for interrupt handler 1
|
||||
*/
|
||||
#define INT_7XX_IH2_FIQ 0
|
||||
#define INT_7XX_IH2_IRQ 1
|
||||
#define INT_7XX_USB_NON_ISO 2
|
||||
#define INT_7XX_USB_ISO 3
|
||||
#define INT_7XX_ICR 4
|
||||
#define INT_7XX_EAC 5
|
||||
#define INT_7XX_GPIO_BANK1 6
|
||||
#define INT_7XX_GPIO_BANK2 7
|
||||
#define INT_7XX_GPIO_BANK3 8
|
||||
#define INT_7XX_McBSP2TX 10
|
||||
#define INT_7XX_McBSP2RX 11
|
||||
#define INT_7XX_McBSP2RX_OVF 12
|
||||
#define INT_7XX_LCD_LINE 14
|
||||
#define INT_7XX_GSM_PROTECT 15
|
||||
#define INT_7XX_TIMER3 16
|
||||
#define INT_7XX_GPIO_BANK5 17
|
||||
#define INT_7XX_GPIO_BANK6 18
|
||||
#define INT_7XX_SPGIO_WR 29
|
||||
|
||||
/*
|
||||
* IRQ numbers for interrupt handler 2
|
||||
*
|
||||
* NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
|
||||
*/
|
||||
#define IH2_BASE 32
|
||||
|
||||
#define INT_KEYBOARD (1 + IH2_BASE)
|
||||
#define INT_uWireTX (2 + IH2_BASE)
|
||||
#define INT_uWireRX (3 + IH2_BASE)
|
||||
#define INT_I2C (4 + IH2_BASE)
|
||||
#define INT_MPUIO (5 + IH2_BASE)
|
||||
#define INT_USB_HHC_1 (6 + IH2_BASE)
|
||||
#define INT_McBSP3TX (10 + IH2_BASE)
|
||||
#define INT_McBSP3RX (11 + IH2_BASE)
|
||||
#define INT_McBSP1TX (12 + IH2_BASE)
|
||||
#define INT_McBSP1RX (13 + IH2_BASE)
|
||||
#define INT_UART1 (14 + IH2_BASE)
|
||||
#define INT_UART2 (15 + IH2_BASE)
|
||||
#define INT_BT_MCSI1TX (16 + IH2_BASE)
|
||||
#define INT_BT_MCSI1RX (17 + IH2_BASE)
|
||||
#define INT_SOSSI_MATCH (19 + IH2_BASE)
|
||||
#define INT_USB_W2FC (20 + IH2_BASE)
|
||||
#define INT_1WIRE (21 + IH2_BASE)
|
||||
#define INT_OS_TIMER (22 + IH2_BASE)
|
||||
#define INT_MMC (23 + IH2_BASE)
|
||||
#define INT_GAUGE_32K (24 + IH2_BASE)
|
||||
#define INT_RTC_TIMER (25 + IH2_BASE)
|
||||
#define INT_RTC_ALARM (26 + IH2_BASE)
|
||||
#define INT_MEM_STICK (27 + IH2_BASE)
|
||||
|
||||
/*
|
||||
* OMAP-1510 specific IRQ numbers for interrupt handler 2
|
||||
*/
|
||||
#define INT_1510_DSP_MMU (28 + IH2_BASE)
|
||||
#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
|
||||
|
||||
/*
|
||||
* OMAP-1610 specific IRQ numbers for interrupt handler 2
|
||||
*/
|
||||
#define INT_1610_FAC (0 + IH2_BASE)
|
||||
#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
|
||||
#define INT_1610_USB_OTG (8 + IH2_BASE)
|
||||
#define INT_1610_SoSSI (9 + IH2_BASE)
|
||||
#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
|
||||
#define INT_1610_DSP_MMU (28 + IH2_BASE)
|
||||
#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
|
||||
#define INT_1610_STI (32 + IH2_BASE)
|
||||
#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
|
||||
#define INT_1610_GPTIMER3 (34 + IH2_BASE)
|
||||
#define INT_1610_GPTIMER4 (35 + IH2_BASE)
|
||||
#define INT_1610_GPTIMER5 (36 + IH2_BASE)
|
||||
#define INT_1610_GPTIMER6 (37 + IH2_BASE)
|
||||
#define INT_1610_GPTIMER7 (38 + IH2_BASE)
|
||||
#define INT_1610_GPTIMER8 (39 + IH2_BASE)
|
||||
#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
|
||||
#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
|
||||
#define INT_1610_MMC2 (42 + IH2_BASE)
|
||||
#define INT_1610_CF (43 + IH2_BASE)
|
||||
#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
|
||||
#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
|
||||
#define INT_1610_SPI (49 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH6 (53 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH7 (54 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH8 (55 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH9 (56 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH10 (57 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH11 (58 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH12 (59 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH13 (60 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH14 (61 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH15 (62 + IH2_BASE)
|
||||
#define INT_1610_NAND (63 + IH2_BASE)
|
||||
#define INT_1610_SHA1MD5 (91 + IH2_BASE)
|
||||
|
||||
/*
|
||||
* OMAP-7xx specific IRQ numbers for interrupt handler 2
|
||||
*/
|
||||
#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
|
||||
#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
|
||||
#define INT_7XX_CFCD (2 + IH2_BASE)
|
||||
#define INT_7XX_CFIREQ (3 + IH2_BASE)
|
||||
#define INT_7XX_I2C (4 + IH2_BASE)
|
||||
#define INT_7XX_PCC (5 + IH2_BASE)
|
||||
#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
|
||||
#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
|
||||
#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
|
||||
#define INT_7XX_VLYNQ (9 + IH2_BASE)
|
||||
#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
|
||||
#define INT_7XX_McBSP1TX (11 + IH2_BASE)
|
||||
#define INT_7XX_McBSP1RX (12 + IH2_BASE)
|
||||
#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
|
||||
#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
|
||||
#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
|
||||
#define INT_7XX_MCSI (16 + IH2_BASE)
|
||||
#define INT_7XX_uWireTX (17 + IH2_BASE)
|
||||
#define INT_7XX_uWireRX (18 + IH2_BASE)
|
||||
#define INT_7XX_SMC_CD (19 + IH2_BASE)
|
||||
#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
|
||||
#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
|
||||
#define INT_7XX_TIMER32K (22 + IH2_BASE)
|
||||
#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
|
||||
#define INT_7XX_UPLD (24 + IH2_BASE)
|
||||
#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
|
||||
#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
|
||||
#define INT_7XX_USB_GENI (29 + IH2_BASE)
|
||||
#define INT_7XX_USB_OTG (30 + IH2_BASE)
|
||||
#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
|
||||
#define INT_7XX_RNG (32 + IH2_BASE)
|
||||
#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
|
||||
#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
|
||||
#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
|
||||
#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
|
||||
#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
|
||||
#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
|
||||
#define INT_7XX_MPUIO (39 + IH2_BASE)
|
||||
#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
|
||||
#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
|
||||
#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
|
||||
#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
|
||||
#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
|
||||
#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
|
||||
#define INT_7XX_NAND (63 + IH2_BASE)
|
||||
|
||||
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
|
||||
* 16 MPUIO lines */
|
||||
#define OMAP_MAX_GPIO_LINES 192
|
||||
#define IH_GPIO_BASE (128 + IH2_BASE)
|
||||
#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
|
||||
#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
|
||||
|
||||
/* External FPGA handles interrupts on Innovator boards */
|
||||
#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
|
||||
#ifdef CONFIG_MACH_OMAP_INNOVATOR
|
||||
#define OMAP_FPGA_NR_IRQS 24
|
||||
#else
|
||||
#define OMAP_FPGA_NR_IRQS 0
|
||||
#endif
|
||||
#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
|
||||
|
||||
#define NR_IRQS OMAP_FPGA_IRQ_END
|
||||
|
||||
#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#ifdef CONFIG_FIQ
|
||||
#define FIQ_START 1024
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user