forked from luck/tmp_suning_uos_patched
mmc: sdhci-pxav3: Get optional core clock
Besides the I/O clock, some PXAv3 SDHCI IP also requires a core clock to be enabled. Add an optional core clock to the corresponding driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -59,6 +59,7 @@
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#define SDCE_MISC_INT_EN (1<<1)
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struct sdhci_pxa {
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struct clk *clk_core;
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struct clk *clk_io;
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u8 power_mode;
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};
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@ -320,6 +321,10 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
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pltfm_host->clk = pxa->clk_io;
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clk_prepare_enable(pxa->clk_io);
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pxa->clk_core = devm_clk_get(dev, "core");
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if (!IS_ERR(pxa->clk_core))
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clk_prepare_enable(pxa->clk_core);
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/* enable 1/8V DDR capable */
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host->mmc->caps |= MMC_CAP_1_8V_DDR;
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@ -392,6 +397,8 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
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err_of_parse:
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err_cd_req:
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clk_disable_unprepare(pxa->clk_io);
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if (!IS_ERR(pxa->clk_core))
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clk_disable_unprepare(pxa->clk_core);
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err_clk_get:
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err_mbus_win:
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sdhci_pltfm_free(pdev);
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@ -409,6 +416,8 @@ static int sdhci_pxav3_remove(struct platform_device *pdev)
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pm_runtime_disable(&pdev->dev);
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clk_disable_unprepare(pxa->clk_io);
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if (!IS_ERR(pxa->clk_core))
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clk_disable_unprepare(pxa->clk_core);
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sdhci_pltfm_free(pdev);
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@ -456,6 +465,8 @@ static int sdhci_pxav3_runtime_suspend(struct device *dev)
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spin_unlock_irqrestore(&host->lock, flags);
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clk_disable_unprepare(pxa->clk_io);
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if (!IS_ERR(pxa->clk_core))
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clk_disable_unprepare(pxa->clk_core);
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return 0;
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}
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@ -468,6 +479,8 @@ static int sdhci_pxav3_runtime_resume(struct device *dev)
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unsigned long flags;
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clk_prepare_enable(pxa->clk_io);
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if (!IS_ERR(pxa->clk_core))
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clk_prepare_enable(pxa->clk_core);
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spin_lock_irqsave(&host->lock, flags);
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host->runtime_suspended = false;
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