forked from luck/tmp_suning_uos_patched
dma: mmp_pdma: factor out DRCMR register calculation
The exact same calculation is done twice, so let's factor it out to a macro. Signed-off-by: Daniel Mack <zonque@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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@ -47,6 +47,8 @@
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#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
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#define DCSR_EORINTR (1 << 9) /* The end of Receive */
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#define DRCMR(n) ((((n) < 64) ? 0x0100 : 0x1100) + \
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(((n) & 0x3f) << 2))
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#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
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#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
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@ -143,8 +145,7 @@ static void enable_chan(struct mmp_pdma_phy *phy)
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if (!phy->vchan)
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return;
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reg = phy->vchan->drcmr;
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reg = (((reg) < 64) ? 0x0100 : 0x1100) + (((reg) & 0x3f) << 2);
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reg = DRCMR(phy->vchan->drcmr);
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writel(DRCMR_MAPVLD | phy->idx, phy->base + reg);
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reg = (phy->idx << 2) + DCSR;
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@ -258,8 +259,7 @@ static void mmp_pdma_free_phy(struct mmp_pdma_chan *pchan)
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return;
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/* clear the channel mapping in DRCMR */
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reg = pchan->phy->vchan->drcmr;
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reg = ((reg < 64) ? 0x0100 : 0x1100) + ((reg & 0x3f) << 2);
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reg = DRCMR(pchan->phy->vchan->drcmr);
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writel(0, pchan->phy->base + reg);
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spin_lock_irqsave(&pdev->phy_lock, flags);
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