forked from luck/tmp_suning_uos_patched
pasemi_mac: jumbo frame support
First cut at jumbo frame support. To support large MTU, one or several separate channels must be allocated to calculate the TCP/UDP checksum separately, since the mac lacks enough buffers to hold a whole packet while it's being calculated. Furthermore, it seems that a single function channel is not quite enough to feed one of the 10Gig links, so allocate two channels for XAUI interfaces. Signed-off-by: Olof Johansson <olof@lixom.net> Acked-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
Olof Johansson
parent
dda56df08a
commit
8d636d8bc5
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@ -59,11 +59,12 @@
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/* Must be a power of two */
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#define RX_RING_SIZE 2048
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#define TX_RING_SIZE 4096
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#define CS_RING_SIZE (TX_RING_SIZE*2)
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#define LRO_MAX_AGGR 64
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#define PE_MIN_MTU 64
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#define PE_MAX_MTU 1500
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#define PE_MAX_MTU 9000
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#define PE_DEF_MTU ETH_DATA_LEN
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#define DEFAULT_MSG_ENABLE \
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@ -81,6 +82,7 @@
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#define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)])
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#define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)])
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#define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)])
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#define CS_DESC(cs, num) ((cs)->chan.ring_virt[(num) & (CS_RING_SIZE-1)])
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#define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
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& ((ring)->size - 1))
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@ -322,6 +324,103 @@ static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac,
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return (nfrags + 3) & ~1;
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}
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static struct pasemi_mac_csring *pasemi_mac_setup_csring(struct pasemi_mac *mac)
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{
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struct pasemi_mac_csring *ring;
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u32 val;
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unsigned int cfg;
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int chno;
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ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_csring),
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offsetof(struct pasemi_mac_csring, chan));
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if (!ring) {
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dev_err(&mac->pdev->dev, "Can't allocate checksum channel\n");
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goto out_chan;
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}
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chno = ring->chan.chno;
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ring->size = CS_RING_SIZE;
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ring->next_to_fill = 0;
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/* Allocate descriptors */
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if (pasemi_dma_alloc_ring(&ring->chan, CS_RING_SIZE))
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goto out_ring_desc;
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write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
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PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
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val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
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val |= PAS_DMA_TXCHAN_BASEU_SIZ(CS_RING_SIZE >> 3);
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write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
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ring->events[0] = pasemi_dma_alloc_flag();
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ring->events[1] = pasemi_dma_alloc_flag();
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if (ring->events[0] < 0 || ring->events[1] < 0)
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goto out_flags;
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pasemi_dma_clear_flag(ring->events[0]);
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pasemi_dma_clear_flag(ring->events[1]);
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ring->fun = pasemi_dma_alloc_fun();
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if (ring->fun < 0)
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goto out_fun;
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cfg = PAS_DMA_TXCHAN_CFG_TY_FUNC | PAS_DMA_TXCHAN_CFG_UP |
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PAS_DMA_TXCHAN_CFG_TATTR(ring->fun) |
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PAS_DMA_TXCHAN_CFG_LPSQ | PAS_DMA_TXCHAN_CFG_LPDQ;
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if (translation_enabled())
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cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
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write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
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/* enable channel */
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pasemi_dma_start_chan(&ring->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
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PAS_DMA_TXCHAN_TCMDSTA_DB |
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PAS_DMA_TXCHAN_TCMDSTA_DE |
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PAS_DMA_TXCHAN_TCMDSTA_DA);
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return ring;
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out_fun:
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out_flags:
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if (ring->events[0] >= 0)
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pasemi_dma_free_flag(ring->events[0]);
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if (ring->events[1] >= 0)
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pasemi_dma_free_flag(ring->events[1]);
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pasemi_dma_free_ring(&ring->chan);
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out_ring_desc:
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pasemi_dma_free_chan(&ring->chan);
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out_chan:
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return NULL;
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}
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static void pasemi_mac_setup_csrings(struct pasemi_mac *mac)
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{
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int i;
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mac->cs[0] = pasemi_mac_setup_csring(mac);
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if (mac->type == MAC_TYPE_XAUI)
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mac->cs[1] = pasemi_mac_setup_csring(mac);
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else
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mac->cs[1] = 0;
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for (i = 0; i < MAX_CS; i++)
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if (mac->cs[i])
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mac->num_cs++;
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}
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static void pasemi_mac_free_csring(struct pasemi_mac_csring *csring)
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{
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pasemi_dma_stop_chan(&csring->chan);
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pasemi_dma_free_flag(csring->events[0]);
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pasemi_dma_free_flag(csring->events[1]);
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pasemi_dma_free_ring(&csring->chan);
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pasemi_dma_free_chan(&csring->chan);
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}
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static int pasemi_mac_setup_rx_resources(const struct net_device *dev)
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{
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struct pasemi_mac_rxring *ring;
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@ -445,7 +544,7 @@ pasemi_mac_setup_tx_resources(const struct net_device *dev)
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cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE |
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PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
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PAS_DMA_TXCHAN_CFG_UP |
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PAS_DMA_TXCHAN_CFG_WT(2);
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PAS_DMA_TXCHAN_CFG_WT(4);
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if (translation_enabled())
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cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
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@ -810,13 +909,21 @@ static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring)
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u64 mactx = TX_DESC(txring, i);
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struct sk_buff *skb;
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skb = TX_DESC_INFO(txring, i+1).skb;
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nr_frags = TX_DESC_INFO(txring, i).dma;
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if ((mactx & XCT_MACTX_E) ||
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(*chan->status & PAS_STATUS_ERROR))
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pasemi_mac_tx_error(mac, mactx);
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/* Skip over control descriptors */
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if (!(mactx & XCT_MACTX_LLEN_M)) {
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TX_DESC(txring, i) = 0;
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TX_DESC(txring, i+1) = 0;
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buf_count = 2;
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continue;
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}
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skb = TX_DESC_INFO(txring, i+1).skb;
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nr_frags = TX_DESC_INFO(txring, i).dma;
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if (unlikely(mactx & XCT_MACTX_O))
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/* Not yet transmitted */
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break;
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@ -1058,6 +1165,12 @@ static int pasemi_mac_open(struct net_device *dev)
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if (!mac->tx)
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goto out_tx_ring;
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if (dev->mtu > 1500) {
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pasemi_mac_setup_csrings(mac);
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if (!mac->num_cs)
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goto out_tx_ring;
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}
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/* 0x3ff with 33MHz clock is about 31us */
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write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG,
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PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff));
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@ -1241,7 +1354,7 @@ static int pasemi_mac_close(struct net_device *dev)
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{
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struct pasemi_mac *mac = netdev_priv(dev);
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unsigned int sta;
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int rxch, txch;
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int rxch, txch, i;
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rxch = rx_ring(mac)->chan.chno;
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txch = tx_ring(mac)->chan.chno;
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@ -1286,6 +1399,9 @@ static int pasemi_mac_close(struct net_device *dev)
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free_irq(mac->tx->chan.irq, mac->tx);
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free_irq(mac->rx->chan.irq, mac->rx);
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for (i = 0; i < mac->num_cs; i++)
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pasemi_mac_free_csring(mac->cs[i]);
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/* Free resources */
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pasemi_mac_free_rx_resources(mac);
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pasemi_mac_free_tx_resources(mac);
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@ -1293,36 +1409,114 @@ static int pasemi_mac_close(struct net_device *dev)
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return 0;
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}
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static void pasemi_mac_queue_csdesc(const struct sk_buff *skb,
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const dma_addr_t *map,
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const unsigned int *map_size,
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struct pasemi_mac_txring *txring,
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struct pasemi_mac_csring *csring)
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{
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u64 fund;
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dma_addr_t cs_dest;
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const int nh_off = skb_network_offset(skb);
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const int nh_len = skb_network_header_len(skb);
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const int nfrags = skb_shinfo(skb)->nr_frags;
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int cs_size, i, fill, hdr, cpyhdr, evt;
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dma_addr_t csdma;
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fund = XCT_FUN_ST | XCT_FUN_RR_8BRES |
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XCT_FUN_O | XCT_FUN_FUN(csring->fun) |
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XCT_FUN_CRM_SIG | XCT_FUN_LLEN(skb->len - nh_off) |
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XCT_FUN_SHL(nh_len >> 2) | XCT_FUN_SE;
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switch (ip_hdr(skb)->protocol) {
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case IPPROTO_TCP:
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fund |= XCT_FUN_SIG_TCP4;
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/* TCP checksum is 16 bytes into the header */
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cs_dest = map[0] + skb_transport_offset(skb) + 16;
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break;
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case IPPROTO_UDP:
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fund |= XCT_FUN_SIG_UDP4;
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/* UDP checksum is 6 bytes into the header */
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cs_dest = map[0] + skb_transport_offset(skb) + 6;
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break;
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default:
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BUG();
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}
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/* Do the checksum offloaded */
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fill = csring->next_to_fill;
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hdr = fill;
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CS_DESC(csring, fill++) = fund;
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/* Room for 8BRES. Checksum result is really 2 bytes into it */
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csdma = csring->chan.ring_dma + (fill & (CS_RING_SIZE-1)) * 8 + 2;
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CS_DESC(csring, fill++) = 0;
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CS_DESC(csring, fill) = XCT_PTR_LEN(map_size[0]-nh_off) | XCT_PTR_ADDR(map[0]+nh_off);
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for (i = 1; i <= nfrags; i++)
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CS_DESC(csring, fill+i) = XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
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fill += i;
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if (fill & 1)
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fill++;
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/* Copy the result into the TCP packet */
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cpyhdr = fill;
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CS_DESC(csring, fill++) = XCT_FUN_O | XCT_FUN_FUN(csring->fun) |
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XCT_FUN_LLEN(2) | XCT_FUN_SE;
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CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(cs_dest) | XCT_PTR_T;
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CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(csdma);
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fill++;
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evt = !csring->last_event;
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csring->last_event = evt;
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/* Event handshaking with MAC TX */
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CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
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CTRL_CMD_ETYPE_SET | CTRL_CMD_REG(csring->events[evt]);
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CS_DESC(csring, fill++) = 0;
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CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
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CTRL_CMD_ETYPE_WCLR | CTRL_CMD_REG(csring->events[!evt]);
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CS_DESC(csring, fill++) = 0;
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csring->next_to_fill = fill & (CS_RING_SIZE-1);
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cs_size = fill - hdr;
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write_dma_reg(PAS_DMA_TXCHAN_INCR(csring->chan.chno), (cs_size) >> 1);
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/* TX-side event handshaking */
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fill = txring->next_to_fill;
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TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
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CTRL_CMD_ETYPE_WSET | CTRL_CMD_REG(csring->events[evt]);
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TX_DESC(txring, fill++) = 0;
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TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
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CTRL_CMD_ETYPE_CLR | CTRL_CMD_REG(csring->events[!evt]);
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TX_DESC(txring, fill++) = 0;
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txring->next_to_fill = fill;
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write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), 2);
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return;
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}
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static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
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{
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struct pasemi_mac *mac = netdev_priv(dev);
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struct pasemi_mac_txring *txring;
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u64 dflags, mactx;
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struct pasemi_mac * const mac = netdev_priv(dev);
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struct pasemi_mac_txring * const txring = tx_ring(mac);
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struct pasemi_mac_csring *csring;
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u64 dflags = 0;
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u64 mactx;
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dma_addr_t map[MAX_SKB_FRAGS+1];
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unsigned int map_size[MAX_SKB_FRAGS+1];
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unsigned long flags;
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int i, nfrags;
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int fill;
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const int nh_off = skb_network_offset(skb);
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const int nh_len = skb_network_header_len(skb);
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prefetch(&txring->ring_info);
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dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD;
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if (skb->ip_summed == CHECKSUM_PARTIAL) {
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const unsigned char *nh = skb_network_header(skb);
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switch (ip_hdr(skb)->protocol) {
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case IPPROTO_TCP:
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dflags |= XCT_MACTX_CSUM_TCP;
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dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
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dflags |= XCT_MACTX_IPO(nh - skb->data);
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break;
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case IPPROTO_UDP:
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dflags |= XCT_MACTX_CSUM_UDP;
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dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
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dflags |= XCT_MACTX_IPO(nh - skb->data);
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break;
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}
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}
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nfrags = skb_shinfo(skb)->nr_frags;
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map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb),
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@ -1344,24 +1538,46 @@ static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
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}
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}
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if (skb->ip_summed == CHECKSUM_PARTIAL && skb->len <= 1540) {
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switch (ip_hdr(skb)->protocol) {
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case IPPROTO_TCP:
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dflags |= XCT_MACTX_CSUM_TCP;
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dflags |= XCT_MACTX_IPH(nh_len >> 2);
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dflags |= XCT_MACTX_IPO(nh_off);
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break;
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case IPPROTO_UDP:
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dflags |= XCT_MACTX_CSUM_UDP;
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dflags |= XCT_MACTX_IPH(nh_len >> 2);
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dflags |= XCT_MACTX_IPO(nh_off);
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break;
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default:
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WARN_ON(1);
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}
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}
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mactx = dflags | XCT_MACTX_LLEN(skb->len);
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txring = tx_ring(mac);
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spin_lock_irqsave(&txring->lock, flags);
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fill = txring->next_to_fill;
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/* Avoid stepping on the same cache line that the DMA controller
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* is currently about to send, so leave at least 8 words available.
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* Total free space needed is mactx + fragments + 8
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*/
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if (RING_AVAIL(txring) < nfrags + 10) {
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if (RING_AVAIL(txring) < nfrags + 14) {
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/* no room -- stop the queue and wait for tx intr */
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netif_stop_queue(dev);
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goto out_err;
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}
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/* Queue up checksum + event descriptors, if needed */
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if (mac->num_cs && skb->ip_summed == CHECKSUM_PARTIAL && skb->len > 1540) {
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csring = mac->cs[mac->last_cs];
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mac->last_cs = (mac->last_cs + 1) % mac->num_cs;
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pasemi_mac_queue_csdesc(skb, map, map_size, txring, csring);
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}
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fill = txring->next_to_fill;
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TX_DESC(txring, fill) = mactx;
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TX_DESC_INFO(txring, fill).dma = nfrags;
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fill++;
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@ -1439,8 +1655,9 @@ static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu)
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{
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struct pasemi_mac *mac = netdev_priv(dev);
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unsigned int reg;
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unsigned int rcmdsta;
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unsigned int rcmdsta = 0;
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int running;
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int ret = 0;
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if (new_mtu < PE_MIN_MTU || new_mtu > PE_MAX_MTU)
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return -EINVAL;
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@ -1462,6 +1679,16 @@ static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu)
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pasemi_mac_pause_rxint(mac);
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pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
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pasemi_mac_free_rx_buffers(mac);
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}
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/* Setup checksum channels if large MTU and none already allocated */
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if (new_mtu > 1500 && !mac->num_cs) {
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pasemi_mac_setup_csrings(mac);
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if (!mac->num_cs) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
/* Change maxf, i.e. what size frames are accepted.
|
||||
|
|
@ -1476,6 +1703,7 @@ static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu)
|
|||
/* MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
|
||||
mac->bufsz = new_mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128;
|
||||
|
||||
out:
|
||||
if (running) {
|
||||
write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
|
||||
rcmdsta | PAS_DMA_RXINT_RCMDSTA_EN);
|
||||
|
|
@ -1488,7 +1716,7 @@ static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu)
|
|||
pasemi_mac_intf_enable(mac);
|
||||
}
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __devinit
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
#include <linux/phy.h>
|
||||
|
||||
#define MAX_LRO_DESCRIPTORS 8
|
||||
#define MAX_CS 2
|
||||
|
||||
struct pasemi_mac_txring {
|
||||
struct pasemi_dmachan chan; /* Must be first */
|
||||
|
|
@ -51,6 +52,15 @@ struct pasemi_mac_rxring {
|
|||
struct pasemi_mac *mac; /* Needed in intr handler */
|
||||
};
|
||||
|
||||
struct pasemi_mac_csring {
|
||||
struct pasemi_dmachan chan;
|
||||
unsigned int size;
|
||||
unsigned int next_to_fill;
|
||||
int events[2];
|
||||
int last_event;
|
||||
int fun;
|
||||
};
|
||||
|
||||
struct pasemi_mac {
|
||||
struct net_device *netdev;
|
||||
struct pci_dev *pdev;
|
||||
|
|
@ -60,10 +70,12 @@ struct pasemi_mac {
|
|||
struct napi_struct napi;
|
||||
|
||||
int bufsz; /* RX ring buffer size */
|
||||
int last_cs;
|
||||
int num_cs;
|
||||
u32 dma_if;
|
||||
u8 type;
|
||||
#define MAC_TYPE_GMAC 1
|
||||
#define MAC_TYPE_XAUI 2
|
||||
u32 dma_if;
|
||||
|
||||
u8 mac_addr[6];
|
||||
|
||||
|
|
@ -74,6 +86,7 @@ struct pasemi_mac {
|
|||
|
||||
struct pasemi_mac_txring *tx;
|
||||
struct pasemi_mac_rxring *rx;
|
||||
struct pasemi_mac_csring *cs[MAX_CS];
|
||||
char tx_irq_name[10]; /* "eth%d tx" */
|
||||
char rx_irq_name[10]; /* "eth%d rx" */
|
||||
int link;
|
||||
|
|
|
|||
|
|
@ -128,11 +128,16 @@ enum {
|
|||
#define PAS_DMA_TXCHAN_TCMDSTA_DA 0x00000100
|
||||
#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
|
||||
#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */
|
||||
#define PAS_DMA_TXCHAN_CFG_TY_COPY 0x00000001 /* Type = copy only */
|
||||
#define PAS_DMA_TXCHAN_CFG_TY_FUNC 0x00000002 /* Type = function */
|
||||
#define PAS_DMA_TXCHAN_CFG_TY_XOR 0x00000003 /* Type = xor only */
|
||||
#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c
|
||||
#define PAS_DMA_TXCHAN_CFG_TATTR_S 2
|
||||
#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
|
||||
PAS_DMA_TXCHAN_CFG_TATTR_M)
|
||||
#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0
|
||||
#define PAS_DMA_TXCHAN_CFG_LPDQ 0x00000800
|
||||
#define PAS_DMA_TXCHAN_CFG_LPSQ 0x00000400
|
||||
#define PAS_DMA_TXCHAN_CFG_WT_M 0x000003c0
|
||||
#define PAS_DMA_TXCHAN_CFG_WT_S 6
|
||||
#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
|
||||
PAS_DMA_TXCHAN_CFG_WT_M)
|
||||
|
|
@ -399,11 +404,62 @@ enum {
|
|||
XCT_COPY_LLEN_M)
|
||||
#define XCT_COPY_SE 0x0000000000000001ull
|
||||
|
||||
/* Function descriptor fields */
|
||||
#define XCT_FUN_T 0x8000000000000000ull
|
||||
#define XCT_FUN_ST 0x4000000000000000ull
|
||||
#define XCT_FUN_RR_M 0x3000000000000000ull
|
||||
#define XCT_FUN_RR_NORES 0x0000000000000000ull
|
||||
#define XCT_FUN_RR_8BRES 0x1000000000000000ull
|
||||
#define XCT_FUN_RR_24BRES 0x2000000000000000ull
|
||||
#define XCT_FUN_RR_40BRES 0x3000000000000000ull
|
||||
#define XCT_FUN_I 0x0800000000000000ull
|
||||
#define XCT_FUN_O 0x0400000000000000ull
|
||||
#define XCT_FUN_E 0x0200000000000000ull
|
||||
#define XCT_FUN_FUN_M 0x01c0000000000000ull
|
||||
#define XCT_FUN_FUN_S 54
|
||||
#define XCT_FUN_FUN(x) ((((long)(x)) << XCT_FUN_FUN_S) & XCT_FUN_FUN_M)
|
||||
#define XCT_FUN_CRM_M 0x0038000000000000ull
|
||||
#define XCT_FUN_CRM_NOP 0x0000000000000000ull
|
||||
#define XCT_FUN_CRM_SIG 0x0008000000000000ull
|
||||
#define XCT_FUN_LLEN_M 0x0007ffff00000000ull
|
||||
#define XCT_FUN_LLEN_S 32
|
||||
#define XCT_FUN_LLEN(x) ((((long)(x)) << XCT_FUN_LLEN_S) & XCT_FUN_LLEN_M)
|
||||
#define XCT_FUN_SHL_M 0x00000000f8000000ull
|
||||
#define XCT_FUN_SHL_S 27
|
||||
#define XCT_FUN_SHL(x) ((((long)(x)) << XCT_FUN_SHL_S) & XCT_FUN_SHL_M)
|
||||
#define XCT_FUN_CHL_M 0x0000000007c00000ull
|
||||
#define XCT_FUN_HSZ_M 0x00000000003c0000ull
|
||||
#define XCT_FUN_ALG_M 0x0000000000038000ull
|
||||
#define XCT_FUN_HP 0x0000000000004000ull
|
||||
#define XCT_FUN_BCM_M 0x0000000000003800ull
|
||||
#define XCT_FUN_BCP_M 0x0000000000000600ull
|
||||
#define XCT_FUN_SIG_M 0x00000000000001f0ull
|
||||
#define XCT_FUN_SIG_TCP4 0x0000000000000140ull
|
||||
#define XCT_FUN_SIG_TCP6 0x0000000000000150ull
|
||||
#define XCT_FUN_SIG_UDP4 0x0000000000000160ull
|
||||
#define XCT_FUN_SIG_UDP6 0x0000000000000170ull
|
||||
#define XCT_FUN_A 0x0000000000000008ull
|
||||
#define XCT_FUN_C 0x0000000000000004ull
|
||||
#define XCT_FUN_AL2 0x0000000000000002ull
|
||||
#define XCT_FUN_SE 0x0000000000000001ull
|
||||
|
||||
/* Function descriptor 8byte result fields */
|
||||
#define XCT_FUNRES_8B_CS_M 0x0000ffff00000000ull
|
||||
#define XCT_FUNRES_8B_CS_S 32
|
||||
#define XCT_FUNRES_8B_CRC_M 0x00000000ffffffffull
|
||||
#define XCT_FUNRES_8B_CRC_S 0
|
||||
|
||||
/* Control descriptor fields */
|
||||
#define CTRL_CMD_T 0x8000000000000000ull
|
||||
#define CTRL_CMD_META_EVT 0x2000000000000000ull
|
||||
#define CTRL_CMD_O 0x0400000000000000ull
|
||||
#define CTRL_CMD_REG_M 0x000000000000000full
|
||||
#define CTRL_CMD_ETYPE_M 0x0038000000000000ull
|
||||
#define CTRL_CMD_ETYPE_EXT 0x0000000000000000ull
|
||||
#define CTRL_CMD_ETYPE_WSET 0x0020000000000000ull
|
||||
#define CTRL_CMD_ETYPE_WCLR 0x0028000000000000ull
|
||||
#define CTRL_CMD_ETYPE_SET 0x0030000000000000ull
|
||||
#define CTRL_CMD_ETYPE_CLR 0x0038000000000000ull
|
||||
#define CTRL_CMD_REG_M 0x000000000000007full
|
||||
#define CTRL_CMD_REG_S 0
|
||||
#define CTRL_CMD_REG(x) ((((long)(x)) << CTRL_CMD_REG_S) & \
|
||||
CTRL_CMD_REG_M)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user