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net: dsa: mediatek: add adjust link support for user ports

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Manually adjust the port settings of user ports once PHY polling has
completed. This patch extends the adjust_link callback to configure the
per port PMCR register, applying the proper values polled from the PHY.
Without this patch flow control was not always getting setup properly.

Signed-off-by: Shashidhar Lakkavalli <shashidhar.lakkavalli@openmesh.com>
Signed-off-by: Muciri Gatimu <muciri@openmesh.com>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
John Crispin 2017-08-07 16:20:49 +02:00 committed by David S. Miller
parent e718fe450e
commit 8e6f1521ec
2 changed files with 39 additions and 0 deletions
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38
drivers/net/dsa/mt7530.c
View File

@ -625,6 +625,44 @@ static void mt7530_adjust_link(struct dsa_switch *ds, int port,
* all finished. * all finished.
*/ */
mt7623_pad_clk_setup(ds); mt7623_pad_clk_setup(ds);
} else {
u16 lcl_adv = 0, rmt_adv = 0;
u8 flowctrl;
u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE;
switch (phydev->speed) {
case SPEED_1000:
mcr |= PMCR_FORCE_SPEED_1000;
break;
case SPEED_100:
mcr |= PMCR_FORCE_SPEED_100;
break;
};
if (phydev->link)
mcr |= PMCR_FORCE_LNK;
if (phydev->duplex) {
mcr |= PMCR_FORCE_FDX;
if (phydev->pause)
rmt_adv = LPA_PAUSE_CAP;
if (phydev->asym_pause)
rmt_adv |= LPA_PAUSE_ASYM;
if (phydev->advertising & ADVERTISED_Pause)
lcl_adv |= ADVERTISE_PAUSE_CAP;
if (phydev->advertising & ADVERTISED_Asym_Pause)
lcl_adv |= ADVERTISE_PAUSE_ASYM;
flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
if (flowctrl & FLOW_CTRL_TX)
mcr |= PMCR_TX_FC_EN;
if (flowctrl & FLOW_CTRL_RX)
mcr |= PMCR_RX_FC_EN;
}
mt7530_write(priv, MT7530_PMCR_P(port), mcr);
} }
} }

1
drivers/net/dsa/mt7530.h
View File

@ -151,6 +151,7 @@ enum mt7530_stp_state {
#define PMCR_TX_FC_EN BIT(5) #define PMCR_TX_FC_EN BIT(5)
#define PMCR_RX_FC_EN BIT(4) #define PMCR_RX_FC_EN BIT(4)
#define PMCR_FORCE_SPEED_1000 BIT(3) #define PMCR_FORCE_SPEED_1000 BIT(3)
#define PMCR_FORCE_SPEED_100 BIT(2)
#define PMCR_FORCE_FDX BIT(1) #define PMCR_FORCE_FDX BIT(1)
#define PMCR_FORCE_LNK BIT(0) #define PMCR_FORCE_LNK BIT(0)
#define PMCR_COMMON_LINK (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \ #define PMCR_COMMON_LINK (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \